1/* 2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8/dts-v1/; 9 10#include "dra74x.dtsi" 11#include "dra7-evm-common.dtsi" 12#include "dra74x-mmc-iodelay.dtsi" 13 14/ { 15 model = "TI DRA742"; 16 compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7"; 17 18 memory@0 { 19 device_type = "memory"; 20 reg = <0x0 0x80000000 0x0 0x60000000>; /* 1536 MB */ 21 }; 22 23 evm_1v8_sw: fixedregulator-evm_1v8 { 24 compatible = "regulator-fixed"; 25 regulator-name = "evm_1v8"; 26 vin-supply = <&smps9_reg>; 27 regulator-min-microvolt = <1800000>; 28 regulator-max-microvolt = <1800000>; 29 }; 30 31 evm_3v3_sd: fixedregulator-sd { 32 compatible = "regulator-fixed"; 33 regulator-name = "evm_3v3_sd"; 34 regulator-min-microvolt = <3300000>; 35 regulator-max-microvolt = <3300000>; 36 enable-active-high; 37 gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>; 38 }; 39 40 evm_3v3_sw: fixedregulator-evm_3v3_sw { 41 compatible = "regulator-fixed"; 42 regulator-name = "evm_3v3_sw"; 43 vin-supply = <&sysen1>; 44 regulator-min-microvolt = <3300000>; 45 regulator-max-microvolt = <3300000>; 46 }; 47 48 aic_dvdd: fixedregulator-aic_dvdd { 49 /* TPS77018DBVT */ 50 compatible = "regulator-fixed"; 51 regulator-name = "aic_dvdd"; 52 vin-supply = <&evm_3v3_sw>; 53 regulator-min-microvolt = <1800000>; 54 regulator-max-microvolt = <1800000>; 55 }; 56 57 extcon_usb2: extcon_usb2 { 58 compatible = "linux,extcon-usb-gpio"; 59 id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>; 60 }; 61 62 vtt_fixed: fixedregulator-vtt { 63 compatible = "regulator-fixed"; 64 regulator-name = "vtt_fixed"; 65 regulator-min-microvolt = <1350000>; 66 regulator-max-microvolt = <1350000>; 67 regulator-always-on; 68 regulator-boot-on; 69 enable-active-high; 70 vin-supply = <&sysen2>; 71 gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>; 72 }; 73 74}; 75 76&dra7_pmx_core { 77 dcan1_pins_default: dcan1_pins_default { 78 pinctrl-single,pins = < 79 DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ 80 DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */ 81 >; 82 }; 83 84 dcan1_pins_sleep: dcan1_pins_sleep { 85 pinctrl-single,pins = < 86 DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */ 87 DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */ 88 >; 89 }; 90 91 mmc1_pins_default: mmc1_pins_default { 92 pinctrl-single,pins = < 93 DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */ 94 DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */ 95 DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ 96 DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ 97 DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ 98 DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ 99 DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ 100 >; 101 }; 102 103 mmc2_pins_default: mmc2_pins_default { 104 pinctrl-single,pins = < 105 DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */ 106 DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */ 107 DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */ 108 DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */ 109 DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */ 110 DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */ 111 DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */ 112 DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */ 113 DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */ 114 DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */ 115 >; 116 }; 117}; 118 119&i2c1 { 120 status = "okay"; 121 clock-frequency = <400000>; 122 123 tps659038: tps659038@58 { 124 compatible = "ti,tps659038"; 125 reg = <0x58>; 126 ti,palmas-override-powerhold; 127 ti,system-power-controller; 128 129 tps659038_pmic { 130 compatible = "ti,tps659038-pmic"; 131 132 regulators { 133 smps123_reg: smps123 { 134 /* VDD_MPU */ 135 regulator-name = "smps123"; 136 regulator-min-microvolt = < 850000>; 137 regulator-max-microvolt = <1250000>; 138 regulator-always-on; 139 regulator-boot-on; 140 }; 141 142 smps45_reg: smps45 { 143 /* VDD_DSPEVE */ 144 regulator-name = "smps45"; 145 regulator-min-microvolt = < 850000>; 146 regulator-max-microvolt = <1250000>; 147 regulator-always-on; 148 regulator-boot-on; 149 }; 150 151 smps6_reg: smps6 { 152 /* VDD_GPU - over VDD_SMPS6 */ 153 regulator-name = "smps6"; 154 regulator-min-microvolt = <850000>; 155 regulator-max-microvolt = <1250000>; 156 regulator-always-on; 157 regulator-boot-on; 158 }; 159 160 smps7_reg: smps7 { 161 /* CORE_VDD */ 162 regulator-name = "smps7"; 163 regulator-min-microvolt = <850000>; 164 regulator-max-microvolt = <1150000>; 165 regulator-always-on; 166 regulator-boot-on; 167 }; 168 169 smps8_reg: smps8 { 170 /* VDD_IVAHD */ 171 regulator-name = "smps8"; 172 regulator-min-microvolt = < 850000>; 173 regulator-max-microvolt = <1250000>; 174 regulator-always-on; 175 regulator-boot-on; 176 }; 177 178 smps9_reg: smps9 { 179 /* VDDS1V8 */ 180 regulator-name = "smps9"; 181 regulator-min-microvolt = <1800000>; 182 regulator-max-microvolt = <1800000>; 183 regulator-always-on; 184 regulator-boot-on; 185 }; 186 187 ldo1_reg: ldo1 { 188 /* LDO1_OUT --> SDIO */ 189 regulator-name = "ldo1"; 190 regulator-min-microvolt = <1800000>; 191 regulator-max-microvolt = <3300000>; 192 regulator-always-on; 193 regulator-boot-on; 194 }; 195 196 ldo2_reg: ldo2 { 197 /* VDD_RTCIO */ 198 /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */ 199 regulator-name = "ldo2"; 200 regulator-min-microvolt = <3300000>; 201 regulator-max-microvolt = <3300000>; 202 regulator-always-on; 203 regulator-boot-on; 204 }; 205 206 ldo3_reg: ldo3 { 207 /* VDDA_1V8_PHY */ 208 regulator-name = "ldo3"; 209 regulator-min-microvolt = <1800000>; 210 regulator-max-microvolt = <1800000>; 211 regulator-always-on; 212 regulator-boot-on; 213 }; 214 215 ldo9_reg: ldo9 { 216 /* VDD_RTC */ 217 regulator-name = "ldo9"; 218 regulator-min-microvolt = <1050000>; 219 regulator-max-microvolt = <1050000>; 220 regulator-always-on; 221 regulator-boot-on; 222 regulator-allow-bypass; 223 }; 224 225 ldoln_reg: ldoln { 226 /* VDDA_1V8_PLL */ 227 regulator-name = "ldoln"; 228 regulator-min-microvolt = <1800000>; 229 regulator-max-microvolt = <1800000>; 230 regulator-always-on; 231 regulator-boot-on; 232 }; 233 234 ldousb_reg: ldousb { 235 /* VDDA_3V_USB: VDDA_USBHS33 */ 236 regulator-name = "ldousb"; 237 regulator-min-microvolt = <3300000>; 238 regulator-max-microvolt = <3300000>; 239 regulator-boot-on; 240 }; 241 242 /* REGEN1 is unused */ 243 244 regen2: regen2 { 245 /* Needed for PMIC internal resources */ 246 regulator-name = "regen2"; 247 regulator-boot-on; 248 regulator-always-on; 249 }; 250 251 /* REGEN3 is unused */ 252 253 sysen1: sysen1 { 254 /* PMIC_REGEN_3V3 */ 255 regulator-name = "sysen1"; 256 regulator-boot-on; 257 regulator-always-on; 258 }; 259 260 sysen2: sysen2 { 261 /* PMIC_REGEN_DDR */ 262 regulator-name = "sysen2"; 263 regulator-boot-on; 264 regulator-always-on; 265 }; 266 }; 267 }; 268 }; 269 270 pcf_lcd: gpio@20 { 271 compatible = "ti,pcf8575", "nxp,pcf8575"; 272 reg = <0x20>; 273 gpio-controller; 274 #gpio-cells = <2>; 275 interrupt-parent = <&gpio6>; 276 interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 277 interrupt-controller; 278 #interrupt-cells = <2>; 279 }; 280 281 pcf_gpio_21: gpio@21 { 282 compatible = "ti,pcf8575", "nxp,pcf8575"; 283 reg = <0x21>; 284 lines-initial-states = <0x1408>; 285 gpio-controller; 286 #gpio-cells = <2>; 287 interrupt-parent = <&gpio6>; 288 interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 289 interrupt-controller; 290 #interrupt-cells = <2>; 291 }; 292 293 tlv320aic3106: tlv320aic3106@19 { 294 #sound-dai-cells = <0>; 295 compatible = "ti,tlv320aic3106"; 296 reg = <0x19>; 297 adc-settle-ms = <40>; 298 ai3x-micbias-vg = <1>; /* 2.0V */ 299 status = "okay"; 300 301 /* Regulators */ 302 AVDD-supply = <&evm_3v3_sw>; 303 IOVDD-supply = <&evm_3v3_sw>; 304 DRVDD-supply = <&evm_3v3_sw>; 305 DVDD-supply = <&aic_dvdd>; 306 }; 307}; 308 309&i2c2 { 310 status = "okay"; 311 clock-frequency = <400000>; 312 313 pcf_hdmi: gpio@26 { 314 compatible = "ti,pcf8575", "nxp,pcf8575"; 315 reg = <0x26>; 316 gpio-controller; 317 #gpio-cells = <2>; 318 p1 { 319 /* vin6_sel_s0: high: VIN6, low: audio */ 320 gpio-hog; 321 gpios = <1 GPIO_ACTIVE_HIGH>; 322 output-low; 323 line-name = "vin6_sel_s0"; 324 }; 325 }; 326}; 327 328&mmc1 { 329 status = "okay"; 330 vmmc-supply = <&evm_3v3_sd>; 331 vqmmc-supply = <&ldo1_reg>; 332 bus-width = <4>; 333 /* 334 * SDCD signal is not being used here - using the fact that GPIO mode 335 * is always hardwired. 336 */ 337 cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; 338 pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50-rev11", "sdr104-rev11", "ddr50", "sdr104"; 339 pinctrl-0 = <&mmc1_pins_default>; 340 pinctrl-1 = <&mmc1_pins_hs>; 341 pinctrl-2 = <&mmc1_pins_sdr12>; 342 pinctrl-3 = <&mmc1_pins_sdr25>; 343 pinctrl-4 = <&mmc1_pins_sdr50>; 344 pinctrl-5 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev11_conf>; 345 pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev11_conf>; 346 pinctrl-7 = <&mmc1_pins_ddr50 &mmc1_iodelay_ddr_rev20_conf>; 347 pinctrl-8 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>; 348}; 349 350&mmc2 { 351 status = "okay"; 352 vmmc-supply = <&evm_1v8_sw>; 353 bus-width = <8>; 354 pinctrl-names = "default", "hs", "ddr_1_8v-rev11", "ddr_1_8v", "hs200_1_8v-rev11", "hs200_1_8v"; 355 pinctrl-0 = <&mmc2_pins_default>; 356 pinctrl-1 = <&mmc2_pins_hs>; 357 pinctrl-2 = <&mmc2_pins_ddr_1_8v_rev11 &mmc2_iodelay_ddr_1_8v_rev11_conf>; 358 pinctrl-3 = <&mmc2_pins_ddr_rev20>; 359 pinctrl-4 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev11_conf>; 360 pinctrl-5 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_rev20_conf>; 361}; 362 363&cpu0 { 364 cpu0-supply = <&smps123_reg>; 365}; 366 367&omap_dwc3_2 { 368 extcon = <&extcon_usb2>; 369}; 370 371&elm { 372 status = "okay"; 373}; 374 375&gpmc { 376 /* 377 * For the existing IOdelay configuration via U-Boot we don't 378 * support NAND on dra7-evm. Keep it disabled. Enabling it 379 * requires a different configuration by U-Boot. 380 */ 381 status = "disabled"; 382 ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */ 383 nand@0,0 { 384 compatible = "ti,omap2-nand"; 385 reg = <0 0 4>; /* device IO registers */ 386 interrupt-parent = <&gpmc>; 387 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ 388 <1 IRQ_TYPE_NONE>; /* termcount */ 389 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */ 390 ti,nand-xfer-type = "prefetch-dma"; 391 ti,nand-ecc-opt = "bch8"; 392 ti,elm-id = <&elm>; 393 nand-bus-width = <16>; 394 gpmc,device-width = <2>; 395 gpmc,sync-clk-ps = <0>; 396 gpmc,cs-on-ns = <0>; 397 gpmc,cs-rd-off-ns = <80>; 398 gpmc,cs-wr-off-ns = <80>; 399 gpmc,adv-on-ns = <0>; 400 gpmc,adv-rd-off-ns = <60>; 401 gpmc,adv-wr-off-ns = <60>; 402 gpmc,we-on-ns = <10>; 403 gpmc,we-off-ns = <50>; 404 gpmc,oe-on-ns = <4>; 405 gpmc,oe-off-ns = <40>; 406 gpmc,access-ns = <40>; 407 gpmc,wr-access-ns = <80>; 408 gpmc,rd-cycle-ns = <80>; 409 gpmc,wr-cycle-ns = <80>; 410 gpmc,bus-turnaround-ns = <0>; 411 gpmc,cycle2cycle-delay-ns = <0>; 412 gpmc,clk-activation-ns = <0>; 413 gpmc,wr-data-mux-bus-ns = <0>; 414 /* MTD partition table */ 415 /* All SPL-* partitions are sized to minimal length 416 * which can be independently programmable. For 417 * NAND flash this is equal to size of erase-block */ 418 #address-cells = <1>; 419 #size-cells = <1>; 420 partition@0 { 421 label = "NAND.SPL"; 422 reg = <0x00000000 0x000020000>; 423 }; 424 partition@1 { 425 label = "NAND.SPL.backup1"; 426 reg = <0x00020000 0x00020000>; 427 }; 428 partition@2 { 429 label = "NAND.SPL.backup2"; 430 reg = <0x00040000 0x00020000>; 431 }; 432 partition@3 { 433 label = "NAND.SPL.backup3"; 434 reg = <0x00060000 0x00020000>; 435 }; 436 partition@4 { 437 label = "NAND.u-boot-spl-os"; 438 reg = <0x00080000 0x00040000>; 439 }; 440 partition@5 { 441 label = "NAND.u-boot"; 442 reg = <0x000c0000 0x00100000>; 443 }; 444 partition@6 { 445 label = "NAND.u-boot-env"; 446 reg = <0x001c0000 0x00020000>; 447 }; 448 partition@7 { 449 label = "NAND.u-boot-env.backup1"; 450 reg = <0x001e0000 0x00020000>; 451 }; 452 partition@8 { 453 label = "NAND.kernel"; 454 reg = <0x00200000 0x00800000>; 455 }; 456 partition@9 { 457 label = "NAND.file-system"; 458 reg = <0x00a00000 0x0f600000>; 459 }; 460 }; 461}; 462 463&usb2_phy1 { 464 phy-supply = <&ldousb_reg>; 465}; 466 467&usb2_phy2 { 468 phy-supply = <&ldousb_reg>; 469}; 470 471&gpio7 { 472 ti,no-reset-on-init; 473 ti,no-idle-on-init; 474}; 475 476&mac { 477 status = "okay"; 478 dual_emac; 479}; 480 481&cpsw_emac0 { 482 phy-handle = <ðphy0>; 483 phy-mode = "rgmii"; 484 dual_emac_res_vlan = <1>; 485}; 486 487&cpsw_emac1 { 488 phy-handle = <ðphy1>; 489 phy-mode = "rgmii"; 490 dual_emac_res_vlan = <2>; 491}; 492 493&davinci_mdio { 494 ethphy0: ethernet-phy@2 { 495 reg = <2>; 496 }; 497 498 ethphy1: ethernet-phy@3 { 499 reg = <3>; 500 }; 501}; 502 503&dcan1 { 504 status = "ok"; 505 pinctrl-names = "default", "sleep", "active"; 506 pinctrl-0 = <&dcan1_pins_sleep>; 507 pinctrl-1 = <&dcan1_pins_sleep>; 508 pinctrl-2 = <&dcan1_pins_default>; 509}; 510 511&pcie1_rc { 512 status = "okay"; 513}; 514