1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright 2019 Gateworks Corporation 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/input/linux-event-codes.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9 10/ { 11 /* these are used by bootloader for disabling nodes */ 12 aliases { 13 led0 = &led0; 14 led1 = &led1; 15 led2 = &led2; 16 mmc0 = &usdhc3; 17 }; 18 19 chosen { 20 stdout-path = &uart2; 21 }; 22 23 memory@10000000 { 24 device_type = "memory"; 25 reg = <0x10000000 0x20000000>; 26 }; 27 28 gpio-keys { 29 compatible = "gpio-keys"; 30 #address-cells = <1>; 31 #size-cells = <0>; 32 33 user-pb { 34 label = "user_pb"; 35 gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>; 36 linux,code = <BTN_0>; 37 }; 38 39 user-pb1x { 40 label = "user_pb1x"; 41 linux,code = <BTN_1>; 42 interrupt-parent = <&gsc>; 43 interrupts = <0>; 44 }; 45 46 key-erased { 47 label = "key-erased"; 48 linux,code = <BTN_2>; 49 interrupt-parent = <&gsc>; 50 interrupts = <1>; 51 }; 52 53 eeprom-wp { 54 label = "eeprom_wp"; 55 linux,code = <BTN_3>; 56 interrupt-parent = <&gsc>; 57 interrupts = <2>; 58 }; 59 60 tamper { 61 label = "tamper"; 62 linux,code = <BTN_4>; 63 interrupt-parent = <&gsc>; 64 interrupts = <5>; 65 }; 66 67 switch-hold { 68 label = "switch_hold"; 69 linux,code = <BTN_5>; 70 interrupt-parent = <&gsc>; 71 interrupts = <7>; 72 }; 73 }; 74 75 leds { 76 compatible = "gpio-leds"; 77 pinctrl-names = "default"; 78 pinctrl-0 = <&pinctrl_gpio_leds>; 79 80 led0: user1 { 81 label = "user1"; 82 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ 83 default-state = "on"; 84 linux,default-trigger = "heartbeat"; 85 }; 86 87 led1: user2 { 88 label = "user2"; 89 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ 90 default-state = "off"; 91 }; 92 93 led2: user3 { 94 label = "user3"; 95 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ 96 default-state = "off"; 97 }; 98 }; 99 100 pps { 101 compatible = "pps-gpio"; 102 pinctrl-names = "default"; 103 pinctrl-0 = <&pinctrl_pps>; 104 gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; 105 status = "okay"; 106 }; 107 108 reg_3p3v: regulator-3p3v { 109 compatible = "regulator-fixed"; 110 regulator-name = "3P3V"; 111 regulator-min-microvolt = <3300000>; 112 regulator-max-microvolt = <3300000>; 113 regulator-always-on; 114 }; 115 116 reg_5p0v: regulator-5p0v { 117 compatible = "regulator-fixed"; 118 regulator-name = "5P0V"; 119 regulator-min-microvolt = <5000000>; 120 regulator-max-microvolt = <5000000>; 121 regulator-always-on; 122 }; 123 124 reg_wl: regulator-wl { 125 pinctrl-names = "default"; 126 pinctrl-0 = <&pinctrl_reg_wl>; 127 compatible = "regulator-fixed"; 128 regulator-name = "wl"; 129 gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; 130 startup-delay-us = <100>; 131 enable-active-high; 132 regulator-min-microvolt = <3300000>; 133 regulator-max-microvolt = <3300000>; 134 }; 135}; 136 137 138&ecspi3 { 139 cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>; 140 pinctrl-names = "default"; 141 pinctrl-0 = <&pinctrl_ecspi3>; 142 status = "okay"; 143}; 144 145&fec { 146 pinctrl-names = "default"; 147 pinctrl-0 = <&pinctrl_enet>; 148 phy-mode = "rgmii-id"; 149 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; 150 phy-reset-duration = <10>; 151 phy-reset-post-delay = <100>; 152 status = "okay"; 153}; 154 155&gpmi { 156 pinctrl-names = "default"; 157 pinctrl-0 = <&pinctrl_gpmi_nand>; 158 status = "okay"; 159}; 160 161&i2c1 { 162 clock-frequency = <100000>; 163 pinctrl-names = "default"; 164 pinctrl-0 = <&pinctrl_i2c1>; 165 status = "okay"; 166 167 gsc: gsc@20 { 168 compatible = "gw,gsc"; 169 reg = <0x20>; 170 interrupt-parent = <&gpio1>; 171 interrupts = <4 IRQ_TYPE_LEVEL_LOW>; 172 interrupt-controller; 173 #interrupt-cells = <1>; 174 #size-cells = <0>; 175 176 adc { 177 compatible = "gw,gsc-adc"; 178 #address-cells = <1>; 179 #size-cells = <0>; 180 181 channel@6 { 182 gw,mode = <0>; 183 reg = <0x06>; 184 label = "temp"; 185 }; 186 187 channel@8 { 188 gw,mode = <3>; 189 reg = <0x08>; 190 label = "vdd_bat"; 191 }; 192 193 channel@82 { 194 gw,mode = <2>; 195 reg = <0x82>; 196 label = "vdd_vin"; 197 gw,voltage-divider-ohms = <22100 1000>; 198 gw,voltage-offset-microvolt = <800000>; 199 }; 200 201 channel@84 { 202 gw,mode = <2>; 203 reg = <0x84>; 204 label = "vdd_5p0"; 205 gw,voltage-divider-ohms = <22100 10000>; 206 }; 207 208 channel@86 { 209 gw,mode = <2>; 210 reg = <0x86>; 211 label = "vdd_3p3"; 212 gw,voltage-divider-ohms = <10000 10000>; 213 }; 214 215 channel@88 { 216 gw,mode = <2>; 217 reg = <0x88>; 218 label = "vdd_2p5"; 219 gw,voltage-divider-ohms = <10000 10000>; 220 }; 221 222 channel@8c { 223 gw,mode = <2>; 224 reg = <0x8c>; 225 label = "vdd_3p0"; 226 }; 227 228 channel@8e { 229 gw,mode = <2>; 230 reg = <0x8e>; 231 label = "vdd_arm"; 232 }; 233 234 channel@90 { 235 gw,mode = <2>; 236 reg = <0x90>; 237 label = "vdd_soc"; 238 }; 239 240 channel@92 { 241 gw,mode = <2>; 242 reg = <0x92>; 243 label = "vdd_1p5"; 244 }; 245 246 channel@98 { 247 gw,mode = <2>; 248 reg = <0x98>; 249 label = "vdd_1p8"; 250 }; 251 252 channel@9a { 253 gw,mode = <2>; 254 reg = <0x9a>; 255 label = "vdd_1p0"; 256 gw,voltage-divider-ohms = <10000 10000>; 257 }; 258 259 channel@9c { 260 gw,mode = <2>; 261 reg = <0x9c>; 262 label = "vdd_an1"; 263 gw,voltage-divider-ohms = <10000 10000>; 264 }; 265 266 channel@a2 { 267 gw,mode = <2>; 268 reg = <0xa2>; 269 label = "vdd_gsc"; 270 gw,voltage-divider-ohms = <10000 10000>; 271 }; 272 }; 273 }; 274 275 gsc_gpio: gpio@23 { 276 compatible = "nxp,pca9555"; 277 reg = <0x23>; 278 gpio-controller; 279 #gpio-cells = <2>; 280 interrupt-parent = <&gsc>; 281 interrupts = <4>; 282 }; 283 284 eeprom@50 { 285 compatible = "atmel,24c02"; 286 reg = <0x50>; 287 pagesize = <16>; 288 }; 289 290 eeprom@51 { 291 compatible = "atmel,24c02"; 292 reg = <0x51>; 293 pagesize = <16>; 294 }; 295 296 eeprom@52 { 297 compatible = "atmel,24c02"; 298 reg = <0x52>; 299 pagesize = <16>; 300 }; 301 302 eeprom@53 { 303 compatible = "atmel,24c02"; 304 reg = <0x53>; 305 pagesize = <16>; 306 }; 307 308 rtc@68 { 309 compatible = "dallas,ds1672"; 310 reg = <0x68>; 311 }; 312}; 313 314&i2c2 { 315 clock-frequency = <100000>; 316 pinctrl-names = "default"; 317 pinctrl-0 = <&pinctrl_i2c2>; 318 status = "okay"; 319}; 320 321&i2c3 { 322 clock-frequency = <100000>; 323 pinctrl-names = "default"; 324 pinctrl-0 = <&pinctrl_i2c3>; 325 status = "okay"; 326 327 accel@19 { 328 pinctrl-names = "default"; 329 pinctrl-0 = <&pinctrl_accel>; 330 compatible = "st,lis2de12"; 331 reg = <0x19>; 332 st,drdy-int-pin = <1>; 333 interrupt-parent = <&gpio7>; 334 interrupts = <13 0>; 335 interrupt-names = "INT1"; 336 }; 337}; 338 339&pcie { 340 pinctrl-names = "default"; 341 pinctrl-0 = <&pinctrl_pcie>; 342 reset-gpio = <&gpio3 20 GPIO_ACTIVE_LOW>; 343 status = "okay"; 344}; 345 346&pwm2 { 347 pinctrl-names = "default"; 348 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ 349 status = "disabled"; 350}; 351 352&pwm3 { 353 pinctrl-names = "default"; 354 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ 355 status = "disabled"; 356}; 357 358/* off-board RS232 */ 359&uart1 { 360 pinctrl-names = "default"; 361 pinctrl-0 = <&pinctrl_uart1>; 362 status = "okay"; 363}; 364 365/* serial console */ 366&uart2 { 367 pinctrl-names = "default"; 368 pinctrl-0 = <&pinctrl_uart2>; 369 status = "okay"; 370}; 371 372/* cc1352 */ 373&uart3 { 374 pinctrl-names = "default"; 375 pinctrl-0 = <&pinctrl_uart3>; 376 uart-has-rtscts; 377 status = "okay"; 378}; 379 380/* Sterling-LWB Bluetooth */ 381&uart4 { 382 pinctrl-names = "default"; 383 pinctrl-0 = <&pinctrl_uart4>,<&pinctrl_bten>; 384 uart-has-rtscts; 385 status = "okay"; 386 387 bluetooth { 388 compatible = "brcm,bcm4330-bt"; 389 shutdown-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; 390 }; 391}; 392 393/* GPS */ 394&uart5 { 395 pinctrl-names = "default"; 396 pinctrl-0 = <&pinctrl_uart5>; 397 status = "okay"; 398}; 399 400&usbotg { 401 vbus-supply = <®_5p0v>; 402 pinctrl-names = "default"; 403 pinctrl-0 = <&pinctrl_usbotg>; 404 disable-over-current; 405 dr_mode = "host"; 406 status = "okay"; 407}; 408 409&usbh1 { 410 status = "okay"; 411}; 412 413/* Sterling-LWB SDIO WiFi */ 414&usdhc2 { 415 pinctrl-names = "default"; 416 pinctrl-0 = <&pinctrl_usdhc2>; 417 vmmc-supply = <®_wl>; 418 non-removable; 419 bus-width = <4>; 420 status = "okay"; 421}; 422 423&usdhc3 { 424 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 425 pinctrl-0 = <&pinctrl_usdhc3>; 426 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 427 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 428 cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; 429 vmmc-supply = <®_3p3v>; 430 status = "okay"; 431}; 432 433&wdog1 { 434 pinctrl-names = "default"; 435 pinctrl-0 = <&pinctrl_wdog>; 436 fsl,ext-reset-output; 437}; 438 439&iomuxc { 440 pinctrl_accel: accelmuxgrp { 441 fsl,pins = < 442 MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b1 443 >; 444 }; 445 446 pinctrl_bten: btengrp { 447 fsl,pins = < 448 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b1 449 >; 450 }; 451 452 pinctrl_ecspi3: escpi3grp { 453 fsl,pins = < 454 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 455 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 456 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 457 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1 458 >; 459 }; 460 461 pinctrl_enet: enetgrp { 462 fsl,pins = < 463 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 464 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 465 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 466 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 467 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 468 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 469 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 470 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 471 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 472 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 473 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 474 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 475 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 476 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 477 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 478 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 479 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 480 >; 481 }; 482 483 pinctrl_gpio_leds: gpioledsgrp { 484 fsl,pins = < 485 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 486 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 487 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 488 >; 489 }; 490 491 pinctrl_gpmi_nand: gpminandgrp { 492 fsl,pins = < 493 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 494 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 495 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 496 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 497 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 498 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 499 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 500 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 501 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 502 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 503 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 504 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 505 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 506 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 507 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 508 >; 509 }; 510 511 pinctrl_i2c1: i2c1grp { 512 fsl,pins = < 513 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 514 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 515 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0 516 >; 517 }; 518 519 pinctrl_i2c2: i2c2grp { 520 fsl,pins = < 521 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 522 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 523 >; 524 }; 525 526 pinctrl_i2c3: i2c3grp { 527 fsl,pins = < 528 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 529 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 530 >; 531 }; 532 533 pinctrl_pcie: pciegrp { 534 fsl,pins = < 535 MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0 536 >; 537 }; 538 539 pinctrl_pps: ppsgrp { 540 fsl,pins = < 541 MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x1b0b1 542 >; 543 }; 544 545 pinctrl_pwm2: pwm2grp { 546 fsl,pins = < 547 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 548 >; 549 }; 550 551 pinctrl_pwm3: pwm3grp { 552 fsl,pins = < 553 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 554 >; 555 }; 556 557 pinctrl_reg_wl: regwlgrp { 558 fsl,pins = < 559 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b1 560 >; 561 }; 562 563 pinctrl_uart1: uart1grp { 564 fsl,pins = < 565 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 566 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 567 >; 568 }; 569 570 pinctrl_uart2: uart2grp { 571 fsl,pins = < 572 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 573 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 574 >; 575 }; 576 577 pinctrl_uart3: uart3grp { 578 fsl,pins = < 579 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 580 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 581 MX6QDL_PAD_EIM_D23__UART3_RTS_B 0x1b0b1 582 MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x1b0b1 583 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x4001b0b1 /* DIO20 */ 584 MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x4001b0b1 /* DIO14 */ 585 MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x4001b0b1 /* DIO15 */ 586 MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1b0b1 /* TMS */ 587 MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1b0b1 /* TCK */ 588 MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1b0b1 /* TDO */ 589 MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x1b0b1 /* TDI */ 590 MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x4001b0b1 /* RST# */ 591 >; 592 }; 593 594 pinctrl_uart4: uart4grp { 595 fsl,pins = < 596 MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 597 MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 598 MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 599 MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 600 >; 601 }; 602 603 pinctrl_uart5: uart5grp { 604 fsl,pins = < 605 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 606 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 607 >; 608 }; 609 610 pinctrl_usbotg: usbotggrp { 611 fsl,pins = < 612 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059 613 >; 614 }; 615 616 pinctrl_usdhc2: usdhc2grp { 617 fsl,pins = < 618 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 619 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 620 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 621 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 622 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 623 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 624 >; 625 }; 626 627 pinctrl_usdhc3: usdhc3grp { 628 fsl,pins = < 629 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 630 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 631 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 632 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 633 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 634 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 635 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ 636 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 637 >; 638 }; 639 640 pinctrl_usdhc3_100mhz: usdhc3grp100mhz { 641 fsl,pins = < 642 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 643 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x170b9 644 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 645 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 646 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 647 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 648 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ 649 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 650 >; 651 }; 652 653 pinctrl_usdhc3_200mhz: usdhc3grp200mhz { 654 fsl,pins = < 655 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 656 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 657 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 658 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 659 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 660 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 661 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ 662 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 663 >; 664 }; 665 666 pinctrl_wdog: wdoggrp { 667 fsl,pins = < 668 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 669 >; 670 }; 671}; 672