1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) STMicroelectronics 2019 - All Rights Reserved
4 * Copyright (c) 2020 Amarula Solutions(India)
5 * Author: Jagan Teki <jagan@amarulasolutions.com>
6 */
7
8#include <dt-bindings/clock/stm32mp1-clksrc.h>
9#include "stm32mp15-u-boot.dtsi"
10#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
11
12&vin {
13	u-boot,dm-pre-reloc;
14};
15
16&vddcore {
17	u-boot,dm-pre-reloc;
18};
19
20&vdd {
21	u-boot,dm-pre-reloc;
22};
23
24&vddq_ddr {
25	u-boot,dm-pre-reloc;
26};
27
28&rcc {
29	st,clksrc = <
30		CLK_MPU_PLL1P
31		CLK_AXI_PLL2P
32		CLK_MCU_PLL3P
33		CLK_PLL12_HSE
34		CLK_PLL3_HSE
35		CLK_PLL4_HSE
36		CLK_RTC_LSE
37		CLK_MCO1_DISABLED
38		CLK_MCO2_DISABLED
39	>;
40
41	st,clkdiv = <
42		1 /*MPU*/
43		0 /*AXI*/
44		0 /*MCU*/
45		1 /*APB1*/
46		1 /*APB2*/
47		1 /*APB3*/
48		1 /*APB4*/
49		2 /*APB5*/
50		23 /*RTC*/
51		0 /*MCO1*/
52		0 /*MCO2*/
53	>;
54
55	st,pkcs = <
56		CLK_CKPER_HSE
57		CLK_FMC_ACLK
58		CLK_QSPI_ACLK
59		CLK_ETH_DISABLED
60		CLK_SDMMC12_PLL4P
61		CLK_DSI_DSIPLL
62		CLK_STGEN_HSE
63		CLK_USBPHY_HSE
64		CLK_SPI2S1_PLL3Q
65		CLK_SPI2S23_PLL3Q
66		CLK_SPI45_HSI
67		CLK_SPI6_HSI
68		CLK_I2C46_HSI
69		CLK_SDMMC3_PLL4P
70		CLK_USBO_USBPHY
71		CLK_ADC_CKPER
72		CLK_CEC_LSE
73		CLK_I2C12_HSI
74		CLK_I2C35_HSI
75		CLK_UART1_HSI
76		CLK_UART24_HSI
77		CLK_UART35_HSI
78		CLK_UART6_HSI
79		CLK_UART78_HSI
80		CLK_SPDIF_PLL4P
81		CLK_FDCAN_PLL4R
82		CLK_SAI1_PLL3Q
83		CLK_SAI2_PLL3Q
84		CLK_SAI3_PLL3Q
85		CLK_SAI4_PLL3Q
86		CLK_RNG1_LSI
87		CLK_RNG2_LSI
88		CLK_LPTIM1_PCLK1
89		CLK_LPTIM23_PCLK3
90		CLK_LPTIM45_LSE
91	>;
92
93	/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
94	pll2: st,pll@1 {
95		compatible = "st,stm32mp1-pll";
96		reg = <1>;
97		cfg = < 2 65 1 0 0 PQR(1,1,1) >;
98		frac = < 0x1400 >;
99		u-boot,dm-pre-reloc;
100	};
101
102	/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
103	pll3: st,pll@2 {
104		compatible = "st,stm32mp1-pll";
105		reg = <2>;
106		cfg = < 1 33 1 16 36 PQR(1,1,1) >;
107		frac = < 0x1a04 >;
108		u-boot,dm-pre-reloc;
109	};
110
111	/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
112	pll4: st,pll@3 {
113		compatible = "st,stm32mp1-pll";
114		reg = <3>;
115		cfg = < 3 98 5 7 7 PQR(1,1,1) >;
116		u-boot,dm-pre-reloc;
117	};
118};
119