1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2// Copyright (C) 2016 ARM Ltd. 3 4#include <sunxi-h3-h5.dtsi> 5 6/ { 7 cpus { 8 #address-cells = <1>; 9 #size-cells = <0>; 10 11 cpu0: cpu@0 { 12 compatible = "arm,cortex-a53"; 13 device_type = "cpu"; 14 reg = <0>; 15 enable-method = "psci"; 16 }; 17 18 cpu1: cpu@1 { 19 compatible = "arm,cortex-a53"; 20 device_type = "cpu"; 21 reg = <1>; 22 enable-method = "psci"; 23 }; 24 25 cpu2: cpu@2 { 26 compatible = "arm,cortex-a53"; 27 device_type = "cpu"; 28 reg = <2>; 29 enable-method = "psci"; 30 }; 31 32 cpu3: cpu@3 { 33 compatible = "arm,cortex-a53"; 34 device_type = "cpu"; 35 reg = <3>; 36 enable-method = "psci"; 37 }; 38 }; 39 40 pmu { 41 compatible = "arm,cortex-a53-pmu", 42 "arm,armv8-pmuv3"; 43 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 44 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 45 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 46 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 47 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 48 }; 49 50 psci { 51 compatible = "arm,psci-0.2"; 52 method = "smc"; 53 }; 54 55 timer { 56 compatible = "arm,armv8-timer"; 57 interrupts = <GIC_PPI 13 58 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 59 <GIC_PPI 14 60 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 61 <GIC_PPI 11 62 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 63 <GIC_PPI 10 64 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 65 }; 66 67 soc { 68 syscon: system-control@1c00000 { 69 compatible = "allwinner,sun50i-h5-system-control"; 70 reg = <0x01c00000 0x1000>; 71 #address-cells = <1>; 72 #size-cells = <1>; 73 ranges; 74 75 sram_c1: sram@18000 { 76 compatible = "mmio-sram"; 77 reg = <0x00018000 0x1c000>; 78 #address-cells = <1>; 79 #size-cells = <1>; 80 ranges = <0 0x00018000 0x1c000>; 81 82 ve_sram: sram-section@0 { 83 compatible = "allwinner,sun50i-h5-sram-c1", 84 "allwinner,sun4i-a10-sram-c1"; 85 reg = <0x000000 0x1c000>; 86 }; 87 }; 88 }; 89 90 video-codec@1c0e000 { 91 compatible = "allwinner,sun50i-h5-video-engine"; 92 reg = <0x01c0e000 0x1000>; 93 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, 94 <&ccu CLK_DRAM_VE>; 95 clock-names = "ahb", "mod", "ram"; 96 resets = <&ccu RST_BUS_VE>; 97 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 98 allwinner,sram = <&ve_sram 1>; 99 }; 100 101 crypto: crypto@1c15000 { 102 compatible = "allwinner,sun50i-h5-crypto"; 103 reg = <0x01c15000 0x1000>; 104 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 105 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>; 106 clock-names = "bus", "mod"; 107 resets = <&ccu RST_BUS_CE>; 108 }; 109 110 mali: gpu@1e80000 { 111 compatible = "allwinner,sun50i-h5-mali", "arm,mali-450"; 112 reg = <0x01e80000 0x30000>; 113 /* 114 * While the datasheet lists an interrupt for the 115 * PMU, the actual silicon does not have the PMU 116 * block. Reads all return zero, and writes are 117 * ignored. 118 */ 119 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 120 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 121 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 122 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 123 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 124 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 125 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 126 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 127 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 128 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 129 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 130 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 131 interrupt-names = "gp", 132 "gpmmu", 133 "pp", 134 "pp0", 135 "ppmmu0", 136 "pp1", 137 "ppmmu1", 138 "pp2", 139 "ppmmu2", 140 "pp3", 141 "ppmmu3", 142 "pmu"; 143 clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>; 144 clock-names = "bus", "core"; 145 resets = <&ccu RST_BUS_GPU>; 146 147 assigned-clocks = <&ccu CLK_GPU>; 148 assigned-clock-rates = <384000000>; 149 }; 150 151 ths: thermal-sensor@1c25000 { 152 compatible = "allwinner,sun50i-h5-ths"; 153 reg = <0x01c25000 0x400>; 154 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 155 resets = <&ccu RST_BUS_THS>; 156 clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>; 157 clock-names = "bus", "mod"; 158 nvmem-cells = <&ths_calibration>; 159 nvmem-cell-names = "calibration"; 160 #thermal-sensor-cells = <1>; 161 }; 162 }; 163 164 thermal-zones { 165 cpu_thermal: cpu-thermal { 166 polling-delay-passive = <0>; 167 polling-delay = <0>; 168 thermal-sensors = <&ths 0>; 169 }; 170 171 gpu_thermal { 172 polling-delay-passive = <0>; 173 polling-delay = <0>; 174 thermal-sensors = <&ths 1>; 175 }; 176 }; 177}; 178 179&ccu { 180 compatible = "allwinner,sun50i-h5-ccu"; 181}; 182 183&display_clocks { 184 compatible = "allwinner,sun50i-h5-de2-clk"; 185}; 186 187&mmc0 { 188 compatible = "allwinner,sun50i-h5-mmc", 189 "allwinner,sun50i-a64-mmc"; 190 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 191 clock-names = "ahb", "mmc"; 192}; 193 194&mmc1 { 195 compatible = "allwinner,sun50i-h5-mmc", 196 "allwinner,sun50i-a64-mmc"; 197 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 198 clock-names = "ahb", "mmc"; 199}; 200 201&mmc2 { 202 compatible = "allwinner,sun50i-h5-emmc", 203 "allwinner,sun50i-a64-emmc"; 204 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 205 clock-names = "ahb", "mmc"; 206}; 207 208&pio { 209 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 210 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 211 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 212 compatible = "allwinner,sun50i-h5-pinctrl"; 213}; 214 215&rtc { 216 compatible = "allwinner,sun50i-h5-rtc"; 217}; 218 219&sid { 220 compatible = "allwinner,sun50i-h5-sid"; 221}; 222