1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * dts file for Xilinx ZynqMP zc1751-xm019-dc5
4 *
5 * (C) Copyright 2015 - 2020, Xilinx, Inc.
6 *
7 * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
8 * Michal Simek <michal.simek@xilinx.com>
9 */
10
11/dts-v1/;
12
13#include "zynqmp.dtsi"
14#include "zynqmp-clk-ccf.dtsi"
15#include <dt-bindings/gpio/gpio.h>
16#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
17
18/ {
19	model = "ZynqMP zc1751-xm019-dc5 RevA";
20	compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
21
22	aliases {
23		ethernet0 = &gem1;
24		gpio0 = &gpio;
25		i2c0 = &i2c0;
26		i2c1 = &i2c1;
27		mmc0 = &sdhci0;
28		serial0 = &uart0;
29		serial1 = &uart1;
30	};
31
32	chosen {
33		bootargs = "earlycon";
34		stdout-path = "serial0:115200n8";
35	};
36
37	memory@0 {
38		device_type = "memory";
39		reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
40	};
41};
42
43&fpd_dma_chan1 {
44	status = "okay";
45};
46
47&fpd_dma_chan2 {
48	status = "okay";
49};
50
51&fpd_dma_chan3 {
52	status = "okay";
53};
54
55&fpd_dma_chan4 {
56	status = "okay";
57};
58
59&fpd_dma_chan5 {
60	status = "okay";
61};
62
63&fpd_dma_chan6 {
64	status = "okay";
65};
66
67&fpd_dma_chan7 {
68	status = "okay";
69};
70
71&fpd_dma_chan8 {
72	status = "okay";
73};
74
75&gem1 {
76	status = "okay";
77	phy-handle = <&phy0>;
78	phy-mode = "rgmii-id";
79	pinctrl-names = "default";
80	pinctrl-0 = <&pinctrl_gem1_default>;
81	phy0: ethernet-phy@0 {
82		reg = <0>;
83	};
84};
85
86&gpio {
87	status = "okay";
88};
89
90&i2c0 {
91	status = "okay";
92	pinctrl-names = "default", "gpio";
93	pinctrl-0 = <&pinctrl_i2c0_default>;
94	pinctrl-1 = <&pinctrl_i2c0_gpio>;
95	scl-gpios = <&gpio 74 GPIO_ACTIVE_HIGH>;
96	sda-gpios = <&gpio 75 GPIO_ACTIVE_HIGH>;
97};
98
99&i2c1 {
100	status = "okay";
101	pinctrl-names = "default", "gpio";
102	pinctrl-0 = <&pinctrl_i2c1_default>;
103	pinctrl-1 = <&pinctrl_i2c1_gpio>;
104	scl-gpios = <&gpio 76 GPIO_ACTIVE_HIGH>;
105	sda-gpios = <&gpio 77 GPIO_ACTIVE_HIGH>;
106
107};
108
109&pinctrl0 {
110	status = "okay";
111	pinctrl_i2c0_default: i2c0-default {
112		mux {
113			groups = "i2c0_18_grp";
114			function = "i2c0";
115		};
116
117		conf {
118			groups = "i2c0_18_grp";
119			bias-pull-up;
120			slew-rate = <SLEW_RATE_SLOW>;
121			power-source = <IO_STANDARD_LVCMOS18>;
122		};
123	};
124
125	pinctrl_i2c0_gpio: i2c0-gpio {
126		mux {
127			groups = "gpio0_74_grp", "gpio0_75_grp";
128			function = "gpio0";
129		};
130
131		conf {
132			groups = "gpio0_74_grp", "gpio0_75_grp";
133			slew-rate = <SLEW_RATE_SLOW>;
134			power-source = <IO_STANDARD_LVCMOS18>;
135		};
136	};
137
138	pinctrl_i2c1_default: i2c1-default {
139		mux {
140			groups = "i2c1_19_grp";
141			function = "i2c1";
142		};
143
144		conf {
145			groups = "i2c1_19_grp";
146			bias-pull-up;
147			slew-rate = <SLEW_RATE_SLOW>;
148			power-source = <IO_STANDARD_LVCMOS18>;
149		};
150	};
151
152	pinctrl_i2c1_gpio: i2c1-gpio {
153		mux {
154			groups = "gpio0_76_grp", "gpio0_77_grp";
155			function = "gpio0";
156		};
157
158		conf {
159			groups = "gpio0_76_grp", "gpio0_77_grp";
160			slew-rate = <SLEW_RATE_SLOW>;
161			power-source = <IO_STANDARD_LVCMOS18>;
162		};
163	};
164
165	pinctrl_uart0_default: uart0-default {
166		mux {
167			groups = "uart0_17_grp";
168			function = "uart0";
169		};
170
171		conf {
172			groups = "uart0_17_grp";
173			slew-rate = <SLEW_RATE_SLOW>;
174			power-source = <IO_STANDARD_LVCMOS18>;
175		};
176
177		conf-rx {
178			pins = "MIO70";
179			bias-high-impedance;
180		};
181
182		conf-tx {
183			pins = "MIO71";
184			bias-disable;
185		};
186	};
187
188	pinctrl_uart1_default: uart1-default {
189		mux {
190			groups = "uart1_18_grp";
191			function = "uart1";
192		};
193
194		conf {
195			groups = "uart1_18_grp";
196			slew-rate = <SLEW_RATE_SLOW>;
197			power-source = <IO_STANDARD_LVCMOS18>;
198		};
199
200		conf-rx {
201			pins = "MIO73";
202			bias-high-impedance;
203		};
204
205		conf-tx {
206			pins = "MIO72";
207			bias-disable;
208		};
209	};
210
211	pinctrl_gem1_default: gem1-default {
212		mux {
213			function = "ethernet1";
214			groups = "ethernet1_0_grp";
215		};
216
217		conf {
218			groups = "ethernet1_0_grp";
219			slew-rate = <SLEW_RATE_SLOW>;
220			power-source = <IO_STANDARD_LVCMOS18>;
221		};
222
223		conf-rx {
224			pins = "MIO44", "MIO45", "MIO46", "MIO47", "MIO48",
225									"MIO49";
226			bias-high-impedance;
227			low-power-disable;
228		};
229
230		conf-tx {
231			pins = "MIO38", "MIO39", "MIO40", "MIO41", "MIO42",
232									"MIO43";
233			bias-disable;
234			low-power-enable;
235		};
236
237		mux-mdio {
238			function = "mdio1";
239			groups = "mdio1_0_grp";
240		};
241
242		conf-mdio {
243			groups = "mdio1_0_grp";
244			slew-rate = <SLEW_RATE_SLOW>;
245			power-source = <IO_STANDARD_LVCMOS18>;
246			bias-disable;
247		};
248	};
249
250	pinctrl_sdhci0_default: sdhci0-default {
251		mux {
252			groups = "sdio0_0_grp";
253			function = "sdio0";
254		};
255
256		conf {
257			groups = "sdio0_0_grp";
258			slew-rate = <SLEW_RATE_SLOW>;
259			power-source = <IO_STANDARD_LVCMOS18>;
260			bias-disable;
261		};
262
263		mux-cd {
264			groups = "sdio0_cd_0_grp";
265			function = "sdio0_cd";
266		};
267
268		conf-cd {
269			groups = "sdio0_cd_0_grp";
270			bias-high-impedance;
271			bias-pull-up;
272			slew-rate = <SLEW_RATE_SLOW>;
273			power-source = <IO_STANDARD_LVCMOS18>;
274		};
275
276		mux-wp {
277			groups = "sdio0_wp_0_grp";
278			function = "sdio0_wp";
279		};
280
281		conf-wp {
282			groups = "sdio0_wp_0_grp";
283			bias-high-impedance;
284			bias-pull-up;
285			slew-rate = <SLEW_RATE_SLOW>;
286			power-source = <IO_STANDARD_LVCMOS18>;
287		};
288	};
289
290	pinctrl_watchdog0_default: watchdog0-default {
291		mux-clk {
292			groups = "swdt0_clk_1_grp";
293			function = "swdt0_clk";
294		};
295
296		conf-clk {
297			groups = "swdt0_clk_1_grp";
298			bias-pull-up;
299		};
300
301		mux-rst {
302			groups = "swdt0_rst_1_grp";
303			function = "swdt0_rst";
304		};
305
306		conf-rst {
307			groups = "swdt0_rst_1_grp";
308			bias-disable;
309			slew-rate = <SLEW_RATE_SLOW>;
310		};
311	};
312
313	pinctrl_ttc0_default: ttc0-default {
314		mux-clk {
315			groups = "ttc0_clk_0_grp";
316			function = "ttc0_clk";
317		};
318
319		conf-clk {
320			groups = "ttc0_clk_0_grp";
321			bias-pull-up;
322		};
323
324		mux-wav {
325			groups = "ttc0_wav_0_grp";
326			function = "ttc0_wav";
327		};
328
329		conf-wav {
330			groups = "ttc0_wav_0_grp";
331			bias-disable;
332			slew-rate = <SLEW_RATE_SLOW>;
333		};
334	};
335
336	pinctrl_ttc1_default: ttc1-default {
337		mux-clk {
338			groups = "ttc1_clk_0_grp";
339			function = "ttc1_clk";
340		};
341
342		conf-clk {
343			groups = "ttc1_clk_0_grp";
344			bias-pull-up;
345		};
346
347		mux-wav {
348			groups = "ttc1_wav_0_grp";
349			function = "ttc1_wav";
350		};
351
352		conf-wav {
353			groups = "ttc1_wav_0_grp";
354			bias-disable;
355			slew-rate = <SLEW_RATE_SLOW>;
356		};
357	};
358
359	pinctrl_ttc2_default: ttc2-default {
360		mux-clk {
361			groups = "ttc2_clk_0_grp";
362			function = "ttc2_clk";
363		};
364
365		conf-clk {
366			groups = "ttc2_clk_0_grp";
367			bias-pull-up;
368		};
369
370		mux-wav {
371			groups = "ttc2_wav_0_grp";
372			function = "ttc2_wav";
373		};
374
375		conf-wav {
376			groups = "ttc2_wav_0_grp";
377			bias-disable;
378			slew-rate = <SLEW_RATE_SLOW>;
379		};
380	};
381
382	pinctrl_ttc3_default: ttc3-default {
383		mux-clk {
384			groups = "ttc3_clk_0_grp";
385			function = "ttc3_clk";
386		};
387
388		conf-clk {
389			groups = "ttc3_clk_0_grp";
390			bias-pull-up;
391		};
392
393		mux-wav {
394			groups = "ttc3_wav_0_grp";
395			function = "ttc3_wav";
396		};
397
398		conf-wav {
399			groups = "ttc3_wav_0_grp";
400			bias-disable;
401			slew-rate = <SLEW_RATE_SLOW>;
402		};
403	};
404};
405
406&sdhci0 {
407	status = "okay";
408	pinctrl-names = "default";
409	pinctrl-0 = <&pinctrl_sdhci0_default>;
410	no-1-8-v;
411	xlnx,mio-bank = <0>;
412};
413
414&ttc0 {
415	status = "okay";
416	pinctrl-names = "default";
417	pinctrl-0 = <&pinctrl_ttc0_default>;
418};
419
420&ttc1 {
421	status = "okay";
422	pinctrl-names = "default";
423	pinctrl-0 = <&pinctrl_ttc1_default>;
424};
425
426&ttc2 {
427	status = "okay";
428	pinctrl-names = "default";
429	pinctrl-0 = <&pinctrl_ttc2_default>;
430};
431
432&ttc3 {
433	status = "okay";
434	pinctrl-names = "default";
435	pinctrl-0 = <&pinctrl_ttc3_default>;
436};
437
438&uart0 {
439	status = "okay";
440	pinctrl-names = "default";
441	pinctrl-0 = <&pinctrl_uart0_default>;
442};
443
444&uart1 {
445	status = "okay";
446	pinctrl-names = "default";
447	pinctrl-0 = <&pinctrl_uart1_default>;
448};
449
450&watchdog0 {
451	status = "okay";
452	pinctrl-names = "default";
453	pinctrl-0 = <&pinctrl_watchdog0_default>;
454};
455