1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2014 Google, Inc
4 * (C) Copyright 2008
5 * Graeme Russ, graeme.russ@gmail.com.
6 *
7 * Some portions from coreboot src/mainboard/google/link/romstage.c
8 * and src/cpu/intel/model_206ax/bootblock.c
9 * Copyright (C) 2007-2010 coresystems GmbH
10 * Copyright (C) 2011 Google Inc.
11 */
12
13 #include <common.h>
14 #include <cpu_func.h>
15 #include <dm.h>
16 #include <errno.h>
17 #include <fdtdec.h>
18 #include <init.h>
19 #include <log.h>
20 #include <pch.h>
21 #include <asm/cpu.h>
22 #include <asm/cpu_common.h>
23 #include <asm/global_data.h>
24 #include <asm/intel_regs.h>
25 #include <asm/io.h>
26 #include <asm/lapic.h>
27 #include <asm/lpc_common.h>
28 #include <asm/microcode.h>
29 #include <asm/msr.h>
30 #include <asm/mtrr.h>
31 #include <asm/pci.h>
32 #include <asm/post.h>
33 #include <asm/processor.h>
34 #include <asm/arch/model_206ax.h>
35 #include <asm/arch/pch.h>
36 #include <asm/arch/sandybridge.h>
37
38 DECLARE_GLOBAL_DATA_PTR;
39
set_flex_ratio_to_tdp_nominal(void)40 static int set_flex_ratio_to_tdp_nominal(void)
41 {
42 /* Minimum CPU revision for configurable TDP support */
43 if (cpuid_eax(1) < IVB_CONFIG_TDP_MIN_CPUID)
44 return -EINVAL;
45
46 return cpu_set_flex_ratio_to_tdp_nominal();
47 }
48
arch_cpu_init(void)49 int arch_cpu_init(void)
50 {
51 post_code(POST_CPU_INIT);
52
53 return x86_cpu_init_f();
54 }
55
arch_cpu_init_dm(void)56 int arch_cpu_init_dm(void)
57 {
58 struct pci_controller *hose;
59 struct udevice *bus, *dev;
60 int ret;
61
62 post_code(0x70);
63 ret = uclass_get_device(UCLASS_PCI, 0, &bus);
64 post_code(0x71);
65 if (ret)
66 return ret;
67 post_code(0x72);
68 hose = dev_get_uclass_priv(bus);
69
70 /* TODO(sjg@chromium.org): Get rid of gd->hose */
71 gd->hose = hose;
72
73 ret = uclass_first_device_err(UCLASS_LPC, &dev);
74 if (ret)
75 return ret;
76
77 /*
78 * We should do as little as possible before the serial console is
79 * up. Perhaps this should move to later. Our next lot of init
80 * happens in checkcpu() when we have a console
81 */
82 ret = set_flex_ratio_to_tdp_nominal();
83 if (ret)
84 return ret;
85
86 return 0;
87 }
88
89 #define PCH_EHCI0_TEMP_BAR0 0xe8000000
90 #define PCH_EHCI1_TEMP_BAR0 0xe8000400
91 #define PCH_XHCI_TEMP_BAR0 0xe8001000
92
93 /*
94 * Setup USB controller MMIO BAR to prevent the reference code from
95 * resetting the controller.
96 *
97 * The BAR will be re-assigned during device enumeration so these are only
98 * temporary.
99 *
100 * This is used to speed up the resume path.
101 */
enable_usb_bar(struct udevice * bus)102 static void enable_usb_bar(struct udevice *bus)
103 {
104 pci_dev_t usb0 = PCH_EHCI1_DEV;
105 pci_dev_t usb1 = PCH_EHCI2_DEV;
106 pci_dev_t usb3 = PCH_XHCI_DEV;
107 ulong cmd;
108
109 /* USB Controller 1 */
110 pci_bus_write_config(bus, usb0, PCI_BASE_ADDRESS_0,
111 PCH_EHCI0_TEMP_BAR0, PCI_SIZE_32);
112 pci_bus_read_config(bus, usb0, PCI_COMMAND, &cmd, PCI_SIZE_32);
113 cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
114 pci_bus_write_config(bus, usb0, PCI_COMMAND, cmd, PCI_SIZE_32);
115
116 /* USB Controller 2 */
117 pci_bus_write_config(bus, usb1, PCI_BASE_ADDRESS_0,
118 PCH_EHCI1_TEMP_BAR0, PCI_SIZE_32);
119 pci_bus_read_config(bus, usb1, PCI_COMMAND, &cmd, PCI_SIZE_32);
120 cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
121 pci_bus_write_config(bus, usb1, PCI_COMMAND, cmd, PCI_SIZE_32);
122
123 /* USB3 Controller 1 */
124 pci_bus_write_config(bus, usb3, PCI_BASE_ADDRESS_0,
125 PCH_XHCI_TEMP_BAR0, PCI_SIZE_32);
126 pci_bus_read_config(bus, usb3, PCI_COMMAND, &cmd, PCI_SIZE_32);
127 cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
128 pci_bus_write_config(bus, usb3, PCI_COMMAND, cmd, PCI_SIZE_32);
129 }
130
checkcpu(void)131 int checkcpu(void)
132 {
133 enum pei_boot_mode_t boot_mode = PEI_BOOT_NONE;
134 struct udevice *dev, *lpc;
135 uint32_t pm1_cnt;
136 uint16_t pm1_sts;
137 int ret;
138
139 /* TODO: cmos_post_init() */
140 if (readl(MCHBAR_REG(SSKPD)) == 0xCAFE) {
141 debug("soft reset detected\n");
142 boot_mode = PEI_BOOT_SOFT_RESET;
143
144 /* System is not happy after keyboard reset... */
145 debug("Issuing CF9 warm reset\n");
146 reset_cpu();
147 }
148
149 ret = cpu_common_init();
150 if (ret) {
151 debug("%s: cpu_common_init() failed\n", __func__);
152 return ret;
153 }
154
155 /* Check PM1_STS[15] to see if we are waking from Sx */
156 pm1_sts = inw(DEFAULT_PMBASE + PM1_STS);
157
158 /* Read PM1_CNT[12:10] to determine which Sx state */
159 pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
160
161 if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) {
162 debug("Resume from S3 detected, but disabled.\n");
163 } else {
164 /*
165 * TODO: An indication of life might be possible here (e.g.
166 * keyboard light)
167 */
168 }
169 post_code(POST_EARLY_INIT);
170
171 /* Enable SPD ROMs and DDR-III DRAM */
172 ret = uclass_first_device_err(UCLASS_I2C, &dev);
173 if (ret) {
174 debug("%s: Failed to get I2C (ret=%d)\n", __func__, ret);
175 return ret;
176 }
177
178 /* Prepare USB controller early in S3 resume */
179 if (boot_mode == PEI_BOOT_RESUME) {
180 uclass_first_device(UCLASS_LPC, &lpc);
181 enable_usb_bar(pci_get_controller(lpc->parent));
182 }
183
184 gd->arch.pei_boot_mode = boot_mode;
185
186 return 0;
187 }
188
print_cpuinfo(void)189 int print_cpuinfo(void)
190 {
191 char processor_name[CPU_MAX_NAME_LEN];
192 const char *name;
193
194 /* Print processor name */
195 name = cpu_get_name(processor_name);
196 printf("CPU: %s\n", name);
197
198 post_code(POST_CPU_INFO);
199
200 return 0;
201 }
202
board_debug_uart_init(void)203 void board_debug_uart_init(void)
204 {
205 /* This enables the debug UART */
206 pci_x86_write_config(PCH_LPC_DEV, LPC_EN, COMA_LPC_EN, PCI_SIZE_16);
207 }
208