1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2007 Freescale Semiconductor, Inc.
4 * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
5 *
6 * This files is mostly identical to the original from
7 * board/freescale/mpc8308rdb/sdram.c
8 */
9
10 #include <common.h>
11 #include <init.h>
12 #include <mpc83xx.h>
13 #include <asm/global_data.h>
14
15 #include <asm/bitops.h>
16 #include <asm/io.h>
17
18 #include <asm/processor.h>
19
20 DECLARE_GLOBAL_DATA_PTR;
21
22 /* Fixed sdram init -- doesn't use serial presence detect.
23 *
24 * This is useful for faster booting in configs where the RAM is unlikely
25 * to be changed, or for things like NAND booting where space is tight.
26 */
fixed_sdram(void)27 static long fixed_sdram(void)
28 {
29 immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
30 u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
31 u32 msize_log2 = __ilog2(msize);
32
33 out_be32(&im->sysconf.ddrlaw[0].bar,
34 CONFIG_SYS_SDRAM_BASE & 0xfffff000);
35 out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
36 out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
37
38 out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
39 out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
40
41 /* Currently we use only one CS, so disable the other bank. */
42 out_be32(&im->ddr.cs_config[1], 0);
43
44 out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
45 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
46 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
47 out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
48 out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
49
50 out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
51 out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
52 out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
53 out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2);
54
55 out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
56 sync();
57
58 /* enable DDR controller */
59 setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
60 sync();
61
62 return get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
63 }
64
dram_init(void)65 int dram_init(void)
66 {
67 immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
68 u32 msize;
69
70 if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
71 return -1;
72
73 /* DDR SDRAM */
74 msize = fixed_sdram();
75
76 /* set total bus SDRAM size(bytes) -- DDR */
77 gd->ram_size = msize;
78
79 return 0;
80 }
81