1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Cirrus Logic CS8900A Ethernet
4 *
5 * (C) 2009 Ben Warren , biggerbadderben@gmail.com
6 * Converted to use CONFIG_NET_MULTI API
7 *
8 * (C) 2003 Wolfgang Denk, wd@denx.de
9 * Extension to synchronize ethaddr environment variable
10 * against value in EEPROM
11 *
12 * (C) Copyright 2002
13 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
14 * Marius Groeger <mgroeger@sysgo.de>
15 *
16 * Copyright (C) 1999 Ben Williamson <benw@pobox.com>
17 *
18 * This program is loaded into SRAM in bootstrap mode, where it waits
19 * for commands on UART1 to read and write memory, jump to code etc.
20 * A design goal for this program is to be entirely independent of the
21 * target board. Anything with a CL-PS7111 or EP7211 should be able to run
22 * this code in bootstrap mode. All the board specifics can be handled on
23 * the host.
24 */
25
26 #include <common.h>
27 #include <command.h>
28 #include <log.h>
29 #include <asm/io.h>
30 #include <net.h>
31 #include <malloc.h>
32 #include <linux/delay.h>
33 #include "cs8900.h"
34
35 #undef DEBUG
36
37 /* packet page register access functions */
38
39 #ifdef CONFIG_CS8900_BUS32
40
41 #define REG_WRITE(v, a) writel((v),(a))
42 #define REG_READ(a) readl((a))
43
44 /* we don't need 16 bit initialisation on 32 bit bus */
45 #define get_reg_init_bus(r,d) get_reg((r),(d))
46
47 #else
48
49 #define REG_WRITE(v, a) writew((v),(a))
50 #define REG_READ(a) readw((a))
51
get_reg_init_bus(struct eth_device * dev,int regno)52 static u16 get_reg_init_bus(struct eth_device *dev, int regno)
53 {
54 /* force 16 bit busmode */
55 struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv);
56 uint8_t volatile * const iob = (uint8_t volatile * const)dev->iobase;
57
58 readb(iob);
59 readb(iob + 1);
60 readb(iob);
61 readb(iob + 1);
62 readb(iob);
63
64 REG_WRITE(regno, &priv->regs->pptr);
65 return REG_READ(&priv->regs->pdata);
66 }
67 #endif
68
get_reg(struct eth_device * dev,int regno)69 static u16 get_reg(struct eth_device *dev, int regno)
70 {
71 struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv);
72 REG_WRITE(regno, &priv->regs->pptr);
73 return REG_READ(&priv->regs->pdata);
74 }
75
76
put_reg(struct eth_device * dev,int regno,u16 val)77 static void put_reg(struct eth_device *dev, int regno, u16 val)
78 {
79 struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv);
80 REG_WRITE(regno, &priv->regs->pptr);
81 REG_WRITE(val, &priv->regs->pdata);
82 }
83
cs8900_reset(struct eth_device * dev)84 static void cs8900_reset(struct eth_device *dev)
85 {
86 int tmo;
87 u16 us;
88
89 /* reset NIC */
90 put_reg(dev, PP_SelfCTL, get_reg(dev, PP_SelfCTL) | PP_SelfCTL_Reset);
91
92 /* wait for 200ms */
93 udelay(200000);
94 /* Wait until the chip is reset */
95
96 tmo = get_timer(0) + 1 * CONFIG_SYS_HZ;
97 while ((((us = get_reg_init_bus(dev, PP_SelfSTAT)) &
98 PP_SelfSTAT_InitD) == 0) && tmo < get_timer(0))
99 /*NOP*/;
100 }
101
cs8900_reginit(struct eth_device * dev)102 static void cs8900_reginit(struct eth_device *dev)
103 {
104 /* receive only error free packets addressed to this card */
105 put_reg(dev, PP_RxCTL,
106 PP_RxCTL_IA | PP_RxCTL_Broadcast | PP_RxCTL_RxOK);
107 /* do not generate any interrupts on receive operations */
108 put_reg(dev, PP_RxCFG, 0);
109 /* do not generate any interrupts on transmit operations */
110 put_reg(dev, PP_TxCFG, 0);
111 /* do not generate any interrupts on buffer operations */
112 put_reg(dev, PP_BufCFG, 0);
113 /* enable transmitter/receiver mode */
114 put_reg(dev, PP_LineCTL, PP_LineCTL_Rx | PP_LineCTL_Tx);
115 }
116
cs8900_get_enetaddr(struct eth_device * dev)117 void cs8900_get_enetaddr(struct eth_device *dev)
118 {
119 int i;
120
121 /* verify chip id */
122 if (get_reg_init_bus(dev, PP_ChipID) != 0x630e)
123 return;
124 cs8900_reset(dev);
125 if ((get_reg(dev, PP_SelfSTAT) &
126 (PP_SelfSTAT_EEPROM | PP_SelfSTAT_EEPROM_OK)) ==
127 (PP_SelfSTAT_EEPROM | PP_SelfSTAT_EEPROM_OK)) {
128
129 /* Load the MAC from EEPROM */
130 for (i = 0; i < 3; i++) {
131 u32 Addr;
132
133 Addr = get_reg(dev, PP_IA + i * 2);
134 dev->enetaddr[i * 2] = Addr & 0xFF;
135 dev->enetaddr[i * 2 + 1] = Addr >> 8;
136 }
137 }
138 }
139
cs8900_halt(struct eth_device * dev)140 void cs8900_halt(struct eth_device *dev)
141 {
142 /* disable transmitter/receiver mode */
143 put_reg(dev, PP_LineCTL, 0);
144
145 /* "shutdown" to show ChipID or kernel wouldn't find he cs8900 ... */
146 get_reg_init_bus(dev, PP_ChipID);
147 }
148
cs8900_init(struct eth_device * dev,struct bd_info * bd)149 static int cs8900_init(struct eth_device *dev, struct bd_info * bd)
150 {
151 uchar *enetaddr = dev->enetaddr;
152 u16 id;
153
154 /* verify chip id */
155 id = get_reg_init_bus(dev, PP_ChipID);
156 if (id != 0x630e) {
157 printf ("CS8900 Ethernet chip not found: "
158 "ID=0x%04x instead 0x%04x\n", id, 0x630e);
159 return 1;
160 }
161
162 cs8900_reset (dev);
163 /* set the ethernet address */
164 put_reg(dev, PP_IA + 0, enetaddr[0] | (enetaddr[1] << 8));
165 put_reg(dev, PP_IA + 2, enetaddr[2] | (enetaddr[3] << 8));
166 put_reg(dev, PP_IA + 4, enetaddr[4] | (enetaddr[5] << 8));
167
168 cs8900_reginit(dev);
169 return 0;
170 }
171
172 /* Get a data block via Ethernet */
cs8900_recv(struct eth_device * dev)173 static int cs8900_recv(struct eth_device *dev)
174 {
175 int i;
176 u16 rxlen;
177 u16 *addr;
178 u16 status;
179
180 struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv);
181
182 status = get_reg(dev, PP_RER);
183
184 if ((status & PP_RER_RxOK) == 0)
185 return 0;
186
187 status = REG_READ(&priv->regs->rtdata);
188 rxlen = REG_READ(&priv->regs->rtdata);
189
190 if (rxlen > PKTSIZE_ALIGN + PKTALIGN)
191 debug("packet too big!\n");
192 for (addr = (u16 *)net_rx_packets[0], i = rxlen >> 1; i > 0; i--)
193 *addr++ = REG_READ(&priv->regs->rtdata);
194 if (rxlen & 1)
195 *addr++ = REG_READ(&priv->regs->rtdata);
196
197 /* Pass the packet up to the protocol layers. */
198 net_process_received_packet(net_rx_packets[0], rxlen);
199 return rxlen;
200 }
201
202 /* Send a data block via Ethernet. */
cs8900_send(struct eth_device * dev,void * packet,int length)203 static int cs8900_send(struct eth_device *dev, void *packet, int length)
204 {
205 volatile u16 *addr;
206 int tmo;
207 u16 s;
208 struct cs8900_priv *priv = (struct cs8900_priv *)(dev->priv);
209
210 retry:
211 /* initiate a transmit sequence */
212 REG_WRITE(PP_TxCmd_TxStart_Full, &priv->regs->txcmd);
213 REG_WRITE(length, &priv->regs->txlen);
214
215 /* Test to see if the chip has allocated memory for the packet */
216 if ((get_reg(dev, PP_BusSTAT) & PP_BusSTAT_TxRDY) == 0) {
217 /* Oops... this should not happen! */
218 debug("cs: unable to send packet; retrying...\n");
219 for (tmo = get_timer(0) + 5 * CONFIG_SYS_HZ;
220 get_timer(0) < tmo;)
221 /*NOP*/;
222 cs8900_reset(dev);
223 cs8900_reginit(dev);
224 goto retry;
225 }
226
227 /* Write the contents of the packet */
228 /* assume even number of bytes */
229 for (addr = packet; length > 0; length -= 2)
230 REG_WRITE(*addr++, &priv->regs->rtdata);
231
232 /* wait for transfer to succeed */
233 tmo = get_timer(0) + 5 * CONFIG_SYS_HZ;
234 while ((s = get_reg(dev, PP_TER) & ~0x1F) == 0) {
235 if (get_timer(0) >= tmo)
236 break;
237 }
238
239 /* nothing */ ;
240 if((s & (PP_TER_CRS | PP_TER_TxOK)) != PP_TER_TxOK) {
241 debug("\ntransmission error %#x\n", s);
242 }
243
244 return 0;
245 }
246
cs8900_e2prom_ready(struct eth_device * dev)247 static void cs8900_e2prom_ready(struct eth_device *dev)
248 {
249 while (get_reg(dev, PP_SelfSTAT) & SI_BUSY)
250 ;
251 }
252
253 /***********************************************************/
254 /* read a 16-bit word out of the EEPROM */
255 /***********************************************************/
256
cs8900_e2prom_read(struct eth_device * dev,u8 addr,u16 * value)257 int cs8900_e2prom_read(struct eth_device *dev,
258 u8 addr, u16 *value)
259 {
260 cs8900_e2prom_ready(dev);
261 put_reg(dev, PP_EECMD, EEPROM_READ_CMD | addr);
262 cs8900_e2prom_ready(dev);
263 *value = get_reg(dev, PP_EEData);
264
265 return 0;
266 }
267
268
269 /***********************************************************/
270 /* write a 16-bit word into the EEPROM */
271 /***********************************************************/
272
cs8900_e2prom_write(struct eth_device * dev,u8 addr,u16 value)273 int cs8900_e2prom_write(struct eth_device *dev, u8 addr, u16 value)
274 {
275 cs8900_e2prom_ready(dev);
276 put_reg(dev, PP_EECMD, EEPROM_WRITE_EN);
277 cs8900_e2prom_ready(dev);
278 put_reg(dev, PP_EEData, value);
279 put_reg(dev, PP_EECMD, EEPROM_WRITE_CMD | addr);
280 cs8900_e2prom_ready(dev);
281 put_reg(dev, PP_EECMD, EEPROM_WRITE_DIS);
282 cs8900_e2prom_ready(dev);
283
284 return 0;
285 }
286
cs8900_initialize(u8 dev_num,int base_addr)287 int cs8900_initialize(u8 dev_num, int base_addr)
288 {
289 struct eth_device *dev;
290 struct cs8900_priv *priv;
291
292 dev = malloc(sizeof(*dev));
293 if (!dev) {
294 return 0;
295 }
296 memset(dev, 0, sizeof(*dev));
297
298 priv = malloc(sizeof(*priv));
299 if (!priv) {
300 free(dev);
301 return 0;
302 }
303 memset(priv, 0, sizeof(*priv));
304 priv->regs = (struct cs8900_regs *)base_addr;
305
306 dev->iobase = base_addr;
307 dev->priv = priv;
308 dev->init = cs8900_init;
309 dev->halt = cs8900_halt;
310 dev->send = cs8900_send;
311 dev->recv = cs8900_recv;
312
313 /* Load MAC address from EEPROM */
314 cs8900_get_enetaddr(dev);
315
316 sprintf(dev->name, "%s-%hu", CS8900_DRIVERNAME, dev_num);
317
318 eth_register(dev);
319 return 0;
320 }
321