1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2000-2004
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 *
6 * (C) Copyright 2007 Freescale Semiconductor, Inc.
7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
8 *
9 * Conversion to DM
10 * (C) 2019 Angelo Dureghello <angelo.dureghello@timesys.com>
11 */
12
13 #include <common.h>
14 #include <env.h>
15 #include <hang.h>
16 #include <malloc.h>
17 #include <command.h>
18 #include <config.h>
19 #include <net.h>
20 #include <miiphy.h>
21 #include <asm/global_data.h>
22 #include <linux/delay.h>
23 #include <linux/mii.h>
24 #include <asm/immap.h>
25 #include <asm/fsl_mcdmafec.h>
26
27 #include "MCD_dma.h"
28
29 #undef ET_DEBUG
30 #undef MII_DEBUG
31
32 /* Ethernet Transmit and Receive Buffers */
33 #define DBUF_LENGTH 1520
34 #define PKT_MAXBUF_SIZE 1518
35 #define FIFO_ERRSTAT (FIFO_STAT_RXW | FIFO_STAT_UF | FIFO_STAT_OF)
36
37 /* RxBD bits definitions */
38 #define BD_ENET_RX_ERR (BD_ENET_RX_LG | BD_ENET_RX_NO | BD_ENET_RX_CR | \
39 BD_ENET_RX_OV | BD_ENET_RX_TR)
40
41 DECLARE_GLOBAL_DATA_PTR;
42
init_eth_info(struct fec_info_dma * info)43 static void init_eth_info(struct fec_info_dma *info)
44 {
45 /* setup Receive and Transmit buffer descriptor */
46 #ifdef CONFIG_SYS_FEC_BUF_USE_SRAM
47 static u32 tmp;
48
49 if (info->index == 0)
50 tmp = CONFIG_SYS_INIT_RAM_ADDR + 0x1000;
51 else
52 info->rxbd = (cbd_t *)DBUF_LENGTH;
53
54 info->rxbd = (cbd_t *)((u32)info->rxbd + tmp);
55 tmp = (u32)info->rxbd;
56 info->txbd =
57 (cbd_t *)((u32)info->txbd + tmp +
58 (PKTBUFSRX * sizeof(cbd_t)));
59 tmp = (u32)info->txbd;
60 info->txbuf =
61 (char *)((u32)info->txbuf + tmp +
62 (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
63 tmp = (u32)info->txbuf;
64 #else
65 info->rxbd =
66 (cbd_t *)memalign(CONFIG_SYS_CACHELINE_SIZE,
67 (PKTBUFSRX * sizeof(cbd_t)));
68 info->txbd =
69 (cbd_t *)memalign(CONFIG_SYS_CACHELINE_SIZE,
70 (CONFIG_SYS_TX_ETH_BUFFER * sizeof(cbd_t)));
71 info->txbuf =
72 (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, DBUF_LENGTH);
73 #endif
74
75 #ifdef ET_DEBUG
76 printf("rxbd %x txbd %x\n", (int)info->rxbd, (int)info->txbd);
77 #endif
78 info->phy_name = (char *)memalign(CONFIG_SYS_CACHELINE_SIZE, 32);
79 }
80
fec_halt(struct udevice * dev)81 static void fec_halt(struct udevice *dev)
82 {
83 struct fec_info_dma *info = dev_get_priv(dev);
84 volatile fecdma_t *fecp = (fecdma_t *)info->iobase;
85 int counter = 0xffff;
86
87 /* issue graceful stop command to the FEC transmitter if necessary */
88 fecp->tcr |= FEC_TCR_GTS;
89
90 /* wait for graceful stop to register */
91 while ((counter--) && (!(fecp->eir & FEC_EIR_GRA)))
92 ;
93
94 /* Disable DMA tasks */
95 MCD_killDma(info->tx_task);
96 MCD_killDma(info->rx_task);
97
98 /* Disable the Ethernet Controller */
99 fecp->ecr &= ~FEC_ECR_ETHER_EN;
100
101 /* Clear FIFO status registers */
102 fecp->rfsr &= FIFO_ERRSTAT;
103 fecp->tfsr &= FIFO_ERRSTAT;
104
105 fecp->frst = 0x01000000;
106
107 /* Issue a reset command to the FEC chip */
108 fecp->ecr |= FEC_ECR_RESET;
109
110 /* wait at least 20 clock cycles */
111 mdelay(10);
112
113 #ifdef ET_DEBUG
114 printf("Ethernet task stopped\n");
115 #endif
116 }
117
118 #ifdef ET_DEBUG
dbg_fec_regs(struct eth_device * dev)119 static void dbg_fec_regs(struct eth_device *dev)
120 {
121 struct fec_info_dma *info = dev->priv;
122 volatile fecdma_t *fecp = (fecdma_t *)info->iobase;
123
124 printf("=====\n");
125 printf("ievent %x - %x\n", (int)&fecp->eir, fecp->eir);
126 printf("imask %x - %x\n", (int)&fecp->eimr, fecp->eimr);
127 printf("ecntrl %x - %x\n", (int)&fecp->ecr, fecp->ecr);
128 printf("mii_mframe %x - %x\n", (int)&fecp->mmfr, fecp->mmfr);
129 printf("mii_speed %x - %x\n", (int)&fecp->mscr, fecp->mscr);
130 printf("mii_ctrlstat %x - %x\n", (int)&fecp->mibc, fecp->mibc);
131 printf("r_cntrl %x - %x\n", (int)&fecp->rcr, fecp->rcr);
132 printf("r hash %x - %x\n", (int)&fecp->rhr, fecp->rhr);
133 printf("x_cntrl %x - %x\n", (int)&fecp->tcr, fecp->tcr);
134 printf("padr_l %x - %x\n", (int)&fecp->palr, fecp->palr);
135 printf("padr_u %x - %x\n", (int)&fecp->paur, fecp->paur);
136 printf("op_pause %x - %x\n", (int)&fecp->opd, fecp->opd);
137 printf("iadr_u %x - %x\n", (int)&fecp->iaur, fecp->iaur);
138 printf("iadr_l %x - %x\n", (int)&fecp->ialr, fecp->ialr);
139 printf("gadr_u %x - %x\n", (int)&fecp->gaur, fecp->gaur);
140 printf("gadr_l %x - %x\n", (int)&fecp->galr, fecp->galr);
141 printf("x_wmrk %x - %x\n", (int)&fecp->tfwr, fecp->tfwr);
142 printf("r_fdata %x - %x\n", (int)&fecp->rfdr, fecp->rfdr);
143 printf("r_fstat %x - %x\n", (int)&fecp->rfsr, fecp->rfsr);
144 printf("r_fctrl %x - %x\n", (int)&fecp->rfcr, fecp->rfcr);
145 printf("r_flrfp %x - %x\n", (int)&fecp->rlrfp, fecp->rlrfp);
146 printf("r_flwfp %x - %x\n", (int)&fecp->rlwfp, fecp->rlwfp);
147 printf("r_frfar %x - %x\n", (int)&fecp->rfar, fecp->rfar);
148 printf("r_frfrp %x - %x\n", (int)&fecp->rfrp, fecp->rfrp);
149 printf("r_frfwp %x - %x\n", (int)&fecp->rfwp, fecp->rfwp);
150 printf("t_fdata %x - %x\n", (int)&fecp->tfdr, fecp->tfdr);
151 printf("t_fstat %x - %x\n", (int)&fecp->tfsr, fecp->tfsr);
152 printf("t_fctrl %x - %x\n", (int)&fecp->tfcr, fecp->tfcr);
153 printf("t_flrfp %x - %x\n", (int)&fecp->tlrfp, fecp->tlrfp);
154 printf("t_flwfp %x - %x\n", (int)&fecp->tlwfp, fecp->tlwfp);
155 printf("t_ftfar %x - %x\n", (int)&fecp->tfar, fecp->tfar);
156 printf("t_ftfrp %x - %x\n", (int)&fecp->tfrp, fecp->tfrp);
157 printf("t_ftfwp %x - %x\n", (int)&fecp->tfwp, fecp->tfwp);
158 printf("frst %x - %x\n", (int)&fecp->frst, fecp->frst);
159 printf("ctcwr %x - %x\n", (int)&fecp->ctcwr, fecp->ctcwr);
160 }
161 #endif
162
set_fec_duplex_speed(volatile fecdma_t * fecp,int dup_spd)163 static void set_fec_duplex_speed(volatile fecdma_t *fecp, int dup_spd)
164 {
165 struct bd_info *bd = gd->bd;
166
167 if ((dup_spd >> 16) == FULL) {
168 /* Set maximum frame length */
169 fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE |
170 FEC_RCR_PROM | 0x100;
171 fecp->tcr = FEC_TCR_FDEN;
172 } else {
173 /* Half duplex mode */
174 fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) |
175 FEC_RCR_MII_MODE | FEC_RCR_DRT;
176 fecp->tcr &= ~FEC_TCR_FDEN;
177 }
178
179 if ((dup_spd & 0xFFFF) == _100BASET) {
180 #ifdef MII_DEBUG
181 printf("100Mbps\n");
182 #endif
183 bd->bi_ethspeed = 100;
184 } else {
185 #ifdef MII_DEBUG
186 printf("10Mbps\n");
187 #endif
188 bd->bi_ethspeed = 10;
189 }
190 }
191
fec_set_hwaddr(volatile fecdma_t * fecp,u8 * mac)192 static void fec_set_hwaddr(volatile fecdma_t *fecp, u8 *mac)
193 {
194 u8 curr_byte; /* byte for which to compute the CRC */
195 int byte; /* loop - counter */
196 int bit; /* loop - counter */
197 u32 crc = 0xffffffff; /* initial value */
198
199 for (byte = 0; byte < 6; byte++) {
200 curr_byte = mac[byte];
201 for (bit = 0; bit < 8; bit++) {
202 if ((curr_byte & 0x01) ^ (crc & 0x01)) {
203 crc >>= 1;
204 crc = crc ^ 0xedb88320;
205 } else {
206 crc >>= 1;
207 }
208 curr_byte >>= 1;
209 }
210 }
211
212 crc = crc >> 26;
213
214 /* Set individual hash table register */
215 if (crc >= 32) {
216 fecp->ialr = (1 << (crc - 32));
217 fecp->iaur = 0;
218 } else {
219 fecp->ialr = 0;
220 fecp->iaur = (1 << crc);
221 }
222
223 /* Set physical address */
224 fecp->palr = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3];
225 fecp->paur = (mac[4] << 24) + (mac[5] << 16) + 0x8808;
226
227 /* Clear multicast address hash table */
228 fecp->gaur = 0;
229 fecp->galr = 0;
230 }
231
fec_init(struct udevice * dev)232 static int fec_init(struct udevice *dev)
233 {
234 struct fec_info_dma *info = dev_get_priv(dev);
235 volatile fecdma_t *fecp = (fecdma_t *)info->iobase;
236 int rval, i;
237 uchar enetaddr[6];
238
239 #ifdef ET_DEBUG
240 printf("fec_init: iobase 0x%08x ...\n", info->iobase);
241 #endif
242
243 fecpin_setclear(info, 1);
244 fec_halt(dev);
245
246 #if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \
247 defined (CONFIG_SYS_DISCOVER_PHY)
248
249 mii_init();
250 set_fec_duplex_speed(fecp, info->dup_spd);
251 #else
252 #ifndef CONFIG_SYS_DISCOVER_PHY
253 set_fec_duplex_speed(fecp, (FECDUPLEX << 16) | FECSPEED);
254 #endif /* ifndef CONFIG_SYS_DISCOVER_PHY */
255 #endif /* CONFIG_CMD_MII || CONFIG_MII */
256
257 /* We use strictly polling mode only */
258 fecp->eimr = 0;
259
260 /* Clear any pending interrupt */
261 fecp->eir = 0xffffffff;
262
263 /* Set station address */
264 if (info->index == 0)
265 rval = eth_env_get_enetaddr("ethaddr", enetaddr);
266 else
267 rval = eth_env_get_enetaddr("eth1addr", enetaddr);
268
269 if (!rval) {
270 puts("Please set a valid MAC address\n");
271 return -EINVAL;
272 }
273
274 fec_set_hwaddr(fecp, enetaddr);
275
276 /* Set Opcode/Pause Duration Register */
277 fecp->opd = 0x00010020;
278
279 /* Setup Buffers and Buffer Descriptors */
280 info->rx_idx = 0;
281 info->tx_idx = 0;
282
283 /* Setup Receiver Buffer Descriptors (13.14.24.18)
284 * Settings: Empty, Wrap */
285 for (i = 0; i < PKTBUFSRX; i++) {
286 info->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
287 info->rxbd[i].cbd_datlen = PKTSIZE_ALIGN;
288 info->rxbd[i].cbd_bufaddr = (uint) net_rx_packets[i];
289 }
290 info->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
291
292 /* Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
293 * Settings: Last, Tx CRC */
294 for (i = 0; i < CONFIG_SYS_TX_ETH_BUFFER; i++) {
295 info->txbd[i].cbd_sc = 0;
296 info->txbd[i].cbd_datlen = 0;
297 info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]);
298 }
299 info->txbd[CONFIG_SYS_TX_ETH_BUFFER - 1].cbd_sc |= BD_ENET_TX_WRAP;
300
301 info->used_tbd_idx = 0;
302 info->clean_tbd_num = CONFIG_SYS_TX_ETH_BUFFER;
303
304 /* Set Rx FIFO alarm and granularity value */
305 fecp->rfcr = 0x0c000000;
306 fecp->rfar = 0x0000030c;
307
308 /* Set Tx FIFO granularity value */
309 fecp->tfcr = FIFO_CTRL_FRAME | FIFO_CTRL_GR(6) | 0x00040000;
310 fecp->tfar = 0x00000080;
311
312 fecp->tfwr = 0x2;
313 fecp->ctcwr = 0x03000000;
314
315 /* Enable DMA receive task */
316 MCD_startDma(info->rx_task,
317 (s8 *)info->rxbd,
318 0,
319 (s8 *)&fecp->rfdr,
320 4,
321 0,
322 4,
323 info->rx_init,
324 info->rx_pri,
325 (MCD_FECRX_DMA | MCD_TT_FLAGS_DEF),
326 (MCD_NO_CSUM | MCD_NO_BYTE_SWAP)
327 );
328
329 /* Enable DMA tx task with no ready buffer descriptors */
330 MCD_startDma(info->tx_task,
331 (s8 *)info->txbd,
332 0,
333 (s8 *)&fecp->tfdr,
334 4,
335 0,
336 4,
337 info->tx_init,
338 info->tx_pri,
339 (MCD_FECTX_DMA | MCD_TT_FLAGS_DEF),
340 (MCD_NO_CSUM | MCD_NO_BYTE_SWAP)
341 );
342
343 /* Now enable the transmit and receive processing */
344 fecp->ecr |= FEC_ECR_ETHER_EN;
345
346 return 0;
347 }
348
mcdmafec_init(struct udevice * dev)349 static int mcdmafec_init(struct udevice *dev)
350 {
351 return fec_init(dev);
352 }
353
mcdmafec_send(struct udevice * dev,void * packet,int length)354 static int mcdmafec_send(struct udevice *dev, void *packet, int length)
355 {
356 struct fec_info_dma *info = dev_get_priv(dev);
357 cbd_t *p_tbd, *p_used_tbd;
358 u16 phy_status;
359
360 miiphy_read(dev->name, info->phy_addr, MII_BMSR, &phy_status);
361
362 /* process all the consumed TBDs */
363 while (info->clean_tbd_num < CONFIG_SYS_TX_ETH_BUFFER) {
364 p_used_tbd = &info->txbd[info->used_tbd_idx];
365 if (p_used_tbd->cbd_sc & BD_ENET_TX_READY) {
366 #ifdef ET_DEBUG
367 printf("Cannot clean TBD %d, in use\n",
368 info->clean_tbd_num);
369 #endif
370 return 0;
371 }
372
373 /* clean this buffer descriptor */
374 if (info->used_tbd_idx == (CONFIG_SYS_TX_ETH_BUFFER - 1))
375 p_used_tbd->cbd_sc = BD_ENET_TX_WRAP;
376 else
377 p_used_tbd->cbd_sc = 0;
378
379 /* update some indeces for a correct handling of TBD ring */
380 info->clean_tbd_num++;
381 info->used_tbd_idx = (info->used_tbd_idx + 1)
382 % CONFIG_SYS_TX_ETH_BUFFER;
383 }
384
385 /* Check for valid length of data. */
386 if (length > 1500 || length <= 0)
387 return -1;
388
389 /* Check the number of vacant TxBDs. */
390 if (info->clean_tbd_num < 1) {
391 printf("No available TxBDs ...\n");
392 return -1;
393 }
394
395 /* Get the first TxBD to send the mac header */
396 p_tbd = &info->txbd[info->tx_idx];
397 p_tbd->cbd_datlen = length;
398 p_tbd->cbd_bufaddr = (u32)packet;
399 p_tbd->cbd_sc |= BD_ENET_TX_LAST | BD_ENET_TX_TC | BD_ENET_TX_READY;
400 info->tx_idx = (info->tx_idx + 1) % CONFIG_SYS_TX_ETH_BUFFER;
401
402 /* Enable DMA transmit task */
403 MCD_continDma(info->tx_task);
404
405 info->clean_tbd_num -= 1;
406
407 /* wait until frame is sent . */
408 while (p_tbd->cbd_sc & BD_ENET_TX_READY)
409 udelay(10);
410
411 return (int)(info->txbd[info->tx_idx].cbd_sc & BD_ENET_TX_STATS);
412 }
413
mcdmafec_recv(struct udevice * dev,int flags,uchar ** packetp)414 static int mcdmafec_recv(struct udevice *dev, int flags, uchar **packetp)
415 {
416 struct fec_info_dma *info = dev_get_priv(dev);
417 volatile fecdma_t *fecp = (fecdma_t *)info->iobase;
418
419 cbd_t *prbd = &info->rxbd[info->rx_idx];
420 u32 ievent;
421 int frame_length, len = 0;
422
423 /* Check if any critical events have happened */
424 ievent = fecp->eir;
425 if (ievent != 0) {
426 fecp->eir = ievent;
427
428 if (ievent & (FEC_EIR_BABT | FEC_EIR_TXERR | FEC_EIR_RXERR)) {
429 printf("fec_recv: error\n");
430 fec_halt(dev);
431 fec_init(dev);
432 return 0;
433 }
434
435 if (ievent & FEC_EIR_HBERR) {
436 /* Heartbeat error */
437 fecp->tcr |= FEC_TCR_GTS;
438 }
439
440 if (ievent & FEC_EIR_GRA) {
441 /* Graceful stop complete */
442 if (fecp->tcr & FEC_TCR_GTS) {
443 printf("fec_recv: tcr_gts\n");
444 fec_halt(dev);
445 fecp->tcr &= ~FEC_TCR_GTS;
446 fec_init(dev);
447 }
448 }
449 }
450
451 if (!(prbd->cbd_sc & BD_ENET_RX_EMPTY)) {
452 if ((prbd->cbd_sc & BD_ENET_RX_LAST) &&
453 !(prbd->cbd_sc & BD_ENET_RX_ERR) &&
454 ((prbd->cbd_datlen - 4) > 14)) {
455 /* Get buffer address and size */
456 frame_length = prbd->cbd_datlen - 4;
457
458 /* Fill the buffer and pass it to upper layers */
459 net_process_received_packet((uchar *)prbd->cbd_bufaddr,
460 frame_length);
461 len = frame_length;
462 }
463
464 /* Reset buffer descriptor as empty */
465 if (info->rx_idx == (PKTBUFSRX - 1))
466 prbd->cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
467 else
468 prbd->cbd_sc = BD_ENET_RX_EMPTY;
469
470 prbd->cbd_datlen = PKTSIZE_ALIGN;
471
472 /* Now, we have an empty RxBD, restart the DMA receive task */
473 MCD_continDma(info->rx_task);
474
475 /* Increment BD count */
476 info->rx_idx = (info->rx_idx + 1) % PKTBUFSRX;
477 }
478
479 return len;
480 }
481
mcdmafec_halt(struct udevice * dev)482 static void mcdmafec_halt(struct udevice *dev)
483 {
484 fec_halt(dev);
485 }
486
487 static const struct eth_ops mcdmafec_ops = {
488 .start = mcdmafec_init,
489 .send = mcdmafec_send,
490 .recv = mcdmafec_recv,
491 .stop = mcdmafec_halt,
492 };
493
494 /*
495 * Boot sequence, called just after mcffec_of_to_plat,
496 * as DM way, it replaces old mcffec_initialize.
497 */
mcdmafec_probe(struct udevice * dev)498 static int mcdmafec_probe(struct udevice *dev)
499 {
500 struct fec_info_dma *info = dev_get_priv(dev);
501 struct eth_pdata *pdata = dev_get_plat(dev);
502 int node = dev_of_offset(dev);
503 int retval;
504 const u32 *val;
505
506 info->index = dev_seq(dev);
507 info->iobase = pdata->iobase;
508 info->miibase = pdata->iobase;
509 info->phy_addr = -1;
510
511 val = fdt_getprop(gd->fdt_blob, node, "rx-task", NULL);
512 if (val)
513 info->rx_task = fdt32_to_cpu(*val);
514
515 val = fdt_getprop(gd->fdt_blob, node, "tx-task", NULL);
516 if (val)
517 info->tx_task = fdt32_to_cpu(*val);
518
519 val = fdt_getprop(gd->fdt_blob, node, "rx-prioprity", NULL);
520 if (val)
521 info->rx_pri = fdt32_to_cpu(*val);
522
523 val = fdt_getprop(gd->fdt_blob, node, "tx-prioprity", NULL);
524 if (val)
525 info->tx_pri = fdt32_to_cpu(*val);
526
527 val = fdt_getprop(gd->fdt_blob, node, "rx-init", NULL);
528 if (val)
529 info->rx_init = fdt32_to_cpu(*val);
530
531 val = fdt_getprop(gd->fdt_blob, node, "tx-init", NULL);
532 if (val)
533 info->tx_init = fdt32_to_cpu(*val);
534
535 #ifdef CONFIG_SYS_FEC_BUF_USE_SRAM
536 u32 tmp = CONFIG_SYS_INIT_RAM_ADDR + 0x1000;
537 #endif
538 init_eth_info(info);
539
540 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
541 info->bus = mdio_alloc();
542 if (!info->bus)
543 return -ENOMEM;
544 strncpy(info->bus->name, dev->name, MDIO_NAME_LEN);
545 info->bus->read = mcffec_miiphy_read;
546 info->bus->write = mcffec_miiphy_write;
547
548 retval = mdio_register(info->bus);
549 if (retval < 0)
550 return retval;
551 #endif
552
553 return 0;
554 }
555
mcdmafec_remove(struct udevice * dev)556 static int mcdmafec_remove(struct udevice *dev)
557 {
558 struct fec_info_dma *priv = dev_get_priv(dev);
559
560 mdio_unregister(priv->bus);
561 mdio_free(priv->bus);
562
563 return 0;
564 }
565
566 /*
567 * Boot sequence, called 1st
568 */
mcdmafec_of_to_plat(struct udevice * dev)569 static int mcdmafec_of_to_plat(struct udevice *dev)
570 {
571 struct eth_pdata *pdata = dev_get_plat(dev);
572 const u32 *val;
573
574 pdata->iobase = dev_read_addr(dev);
575 /* Default to 10Mbit/s */
576 pdata->max_speed = 10;
577
578 val = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL);
579 if (val)
580 pdata->max_speed = fdt32_to_cpu(*val);
581
582 return 0;
583 }
584
585 static const struct udevice_id mcdmafec_ids[] = {
586 { .compatible = "fsl,mcf-dma-fec" },
587 { }
588 };
589
590 U_BOOT_DRIVER(mcffec) = {
591 .name = "mcdmafec",
592 .id = UCLASS_ETH,
593 .of_match = mcdmafec_ids,
594 .of_to_plat = mcdmafec_of_to_plat,
595 .probe = mcdmafec_probe,
596 .remove = mcdmafec_remove,
597 .ops = &mcdmafec_ops,
598 .priv_auto = sizeof(struct fec_info_dma),
599 .plat_auto = sizeof(struct eth_pdata),
600 };
601