1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Faraday FTGMAC100 Ethernet
4 *
5 * (C) Copyright 2009 Faraday Technology
6 * Po-Yu Chuang <ratbert@faraday-tech.com>
7 *
8 * (C) Copyright 2010 Andes Technology
9 * Macpaul Lin <macpaul@andestech.com>
10 *
11 * Copyright (C) 2018, IBM Corporation.
12 */
13
14 #include <common.h>
15 #include <clk.h>
16 #include <cpu_func.h>
17 #include <dm.h>
18 #include <log.h>
19 #include <malloc.h>
20 #include <miiphy.h>
21 #include <net.h>
22 #include <wait_bit.h>
23 #include <asm/cache.h>
24 #include <dm/device_compat.h>
25 #include <linux/bitops.h>
26 #include <linux/io.h>
27 #include <linux/iopoll.h>
28
29 #include "ftgmac100.h"
30
31 /* Min frame ethernet frame size without FCS */
32 #define ETH_ZLEN 60
33
34 /* Receive Buffer Size Register - HW default is 0x640 */
35 #define FTGMAC100_RBSR_DEFAULT 0x640
36
37 /* PKTBUFSTX/PKTBUFSRX must both be power of 2 */
38 #define PKTBUFSTX 4 /* must be power of 2 */
39
40 /* Timeout for transmit */
41 #define FTGMAC100_TX_TIMEOUT_MS 1000
42
43 /* Timeout for a mdio read/write operation */
44 #define FTGMAC100_MDIO_TIMEOUT_USEC 10000
45
46 /*
47 * MDC clock cycle threshold
48 *
49 * 20us * 100 = 2ms > (1 / 2.5Mhz) * 0x34
50 */
51 #define MDC_CYCTHR 0x34
52
53 /*
54 * ftgmac100 model variants
55 */
56 enum ftgmac100_model {
57 FTGMAC100_MODEL_FARADAY,
58 FTGMAC100_MODEL_ASPEED,
59 };
60
61 /**
62 * struct ftgmac100_data - private data for the FTGMAC100 driver
63 *
64 * @iobase: The base address of the hardware registers
65 * @txdes: The array of transmit descriptors
66 * @rxdes: The array of receive descriptors
67 * @tx_index: Transmit descriptor index in @txdes
68 * @rx_index: Receive descriptor index in @rxdes
69 * @phy_addr: The PHY interface address to use
70 * @phydev: The PHY device backing the MAC
71 * @bus: The mdio bus
72 * @phy_mode: The mode of the PHY interface (rgmii, rmii, ...)
73 * @max_speed: Maximum speed of Ethernet connection supported by MAC
74 * @clks: The bulk of clocks assigned to the device in the DT
75 * @rxdes0_edorr_mask: The bit number identifying the end of the RX ring buffer
76 * @txdes0_edotr_mask: The bit number identifying the end of the TX ring buffer
77 */
78 struct ftgmac100_data {
79 struct ftgmac100 *iobase;
80
81 struct ftgmac100_txdes txdes[PKTBUFSTX] __aligned(ARCH_DMA_MINALIGN);
82 struct ftgmac100_rxdes rxdes[PKTBUFSRX] __aligned(ARCH_DMA_MINALIGN);
83 int tx_index;
84 int rx_index;
85
86 u32 phy_addr;
87 struct phy_device *phydev;
88 struct mii_dev *bus;
89 u32 phy_mode;
90 u32 max_speed;
91
92 struct clk_bulk clks;
93
94 /* End of RX/TX ring buffer bits. Depend on model */
95 u32 rxdes0_edorr_mask;
96 u32 txdes0_edotr_mask;
97 };
98
99 /*
100 * struct mii_bus functions
101 */
ftgmac100_mdio_read(struct mii_dev * bus,int phy_addr,int dev_addr,int reg_addr)102 static int ftgmac100_mdio_read(struct mii_dev *bus, int phy_addr, int dev_addr,
103 int reg_addr)
104 {
105 struct ftgmac100_data *priv = bus->priv;
106 struct ftgmac100 *ftgmac100 = priv->iobase;
107 int phycr;
108 int data;
109 int ret;
110
111 phycr = FTGMAC100_PHYCR_MDC_CYCTHR(MDC_CYCTHR) |
112 FTGMAC100_PHYCR_PHYAD(phy_addr) |
113 FTGMAC100_PHYCR_REGAD(reg_addr) |
114 FTGMAC100_PHYCR_MIIRD;
115 writel(phycr, &ftgmac100->phycr);
116
117 ret = readl_poll_timeout(&ftgmac100->phycr, phycr,
118 !(phycr & FTGMAC100_PHYCR_MIIRD),
119 FTGMAC100_MDIO_TIMEOUT_USEC);
120 if (ret) {
121 pr_err("%s: mdio read failed (phy:%d reg:%x)\n",
122 priv->phydev->dev->name, phy_addr, reg_addr);
123 return ret;
124 }
125
126 data = readl(&ftgmac100->phydata);
127
128 return FTGMAC100_PHYDATA_MIIRDATA(data);
129 }
130
ftgmac100_mdio_write(struct mii_dev * bus,int phy_addr,int dev_addr,int reg_addr,u16 value)131 static int ftgmac100_mdio_write(struct mii_dev *bus, int phy_addr, int dev_addr,
132 int reg_addr, u16 value)
133 {
134 struct ftgmac100_data *priv = bus->priv;
135 struct ftgmac100 *ftgmac100 = priv->iobase;
136 int phycr;
137 int data;
138 int ret;
139
140 phycr = FTGMAC100_PHYCR_MDC_CYCTHR(MDC_CYCTHR) |
141 FTGMAC100_PHYCR_PHYAD(phy_addr) |
142 FTGMAC100_PHYCR_REGAD(reg_addr) |
143 FTGMAC100_PHYCR_MIIWR;
144 data = FTGMAC100_PHYDATA_MIIWDATA(value);
145
146 writel(data, &ftgmac100->phydata);
147 writel(phycr, &ftgmac100->phycr);
148
149 ret = readl_poll_timeout(&ftgmac100->phycr, phycr,
150 !(phycr & FTGMAC100_PHYCR_MIIWR),
151 FTGMAC100_MDIO_TIMEOUT_USEC);
152 if (ret) {
153 pr_err("%s: mdio write failed (phy:%d reg:%x)\n",
154 priv->phydev->dev->name, phy_addr, reg_addr);
155 }
156
157 return ret;
158 }
159
ftgmac100_mdio_init(struct udevice * dev)160 static int ftgmac100_mdio_init(struct udevice *dev)
161 {
162 struct ftgmac100_data *priv = dev_get_priv(dev);
163 struct mii_dev *bus;
164 int ret;
165
166 bus = mdio_alloc();
167 if (!bus)
168 return -ENOMEM;
169
170 bus->read = ftgmac100_mdio_read;
171 bus->write = ftgmac100_mdio_write;
172 bus->priv = priv;
173
174 ret = mdio_register_seq(bus, dev_seq(dev));
175 if (ret) {
176 free(bus);
177 return ret;
178 }
179
180 priv->bus = bus;
181
182 return 0;
183 }
184
ftgmac100_phy_adjust_link(struct ftgmac100_data * priv)185 static int ftgmac100_phy_adjust_link(struct ftgmac100_data *priv)
186 {
187 struct ftgmac100 *ftgmac100 = priv->iobase;
188 struct phy_device *phydev = priv->phydev;
189 u32 maccr;
190
191 if (!phydev->link) {
192 dev_err(phydev->dev, "No link\n");
193 return -EREMOTEIO;
194 }
195
196 /* read MAC control register and clear related bits */
197 maccr = readl(&ftgmac100->maccr) &
198 ~(FTGMAC100_MACCR_GIGA_MODE |
199 FTGMAC100_MACCR_FAST_MODE |
200 FTGMAC100_MACCR_FULLDUP);
201
202 if (phy_interface_is_rgmii(phydev) && phydev->speed == 1000)
203 maccr |= FTGMAC100_MACCR_GIGA_MODE;
204
205 if (phydev->speed == 100)
206 maccr |= FTGMAC100_MACCR_FAST_MODE;
207
208 if (phydev->duplex)
209 maccr |= FTGMAC100_MACCR_FULLDUP;
210
211 /* update MII config into maccr */
212 writel(maccr, &ftgmac100->maccr);
213
214 return 0;
215 }
216
ftgmac100_phy_init(struct udevice * dev)217 static int ftgmac100_phy_init(struct udevice *dev)
218 {
219 struct ftgmac100_data *priv = dev_get_priv(dev);
220 struct phy_device *phydev;
221 int ret;
222
223 phydev = phy_connect(priv->bus, priv->phy_addr, dev, priv->phy_mode);
224 if (!phydev)
225 return -ENODEV;
226
227 phydev->supported &= PHY_GBIT_FEATURES;
228 if (priv->max_speed) {
229 ret = phy_set_supported(phydev, priv->max_speed);
230 if (ret)
231 return ret;
232 }
233 phydev->advertising = phydev->supported;
234 priv->phydev = phydev;
235 phy_config(phydev);
236
237 return 0;
238 }
239
240 /*
241 * Reset MAC
242 */
ftgmac100_reset(struct ftgmac100_data * priv)243 static void ftgmac100_reset(struct ftgmac100_data *priv)
244 {
245 struct ftgmac100 *ftgmac100 = priv->iobase;
246
247 debug("%s()\n", __func__);
248
249 setbits_le32(&ftgmac100->maccr, FTGMAC100_MACCR_SW_RST);
250
251 while (readl(&ftgmac100->maccr) & FTGMAC100_MACCR_SW_RST)
252 ;
253 }
254
255 /*
256 * Set MAC address
257 */
ftgmac100_set_mac(struct ftgmac100_data * priv,const unsigned char * mac)258 static int ftgmac100_set_mac(struct ftgmac100_data *priv,
259 const unsigned char *mac)
260 {
261 struct ftgmac100 *ftgmac100 = priv->iobase;
262 unsigned int maddr = mac[0] << 8 | mac[1];
263 unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5];
264
265 debug("%s(%x %x)\n", __func__, maddr, laddr);
266
267 writel(maddr, &ftgmac100->mac_madr);
268 writel(laddr, &ftgmac100->mac_ladr);
269
270 return 0;
271 }
272
273 /*
274 * Get MAC address
275 */
ftgmac100_get_mac(struct ftgmac100_data * priv,unsigned char * mac)276 static int ftgmac100_get_mac(struct ftgmac100_data *priv,
277 unsigned char *mac)
278 {
279 struct ftgmac100 *ftgmac100 = priv->iobase;
280 unsigned int maddr = readl(&ftgmac100->mac_madr);
281 unsigned int laddr = readl(&ftgmac100->mac_ladr);
282
283 debug("%s(%x %x)\n", __func__, maddr, laddr);
284
285 mac[0] = (maddr >> 8) & 0xff;
286 mac[1] = maddr & 0xff;
287 mac[2] = (laddr >> 24) & 0xff;
288 mac[3] = (laddr >> 16) & 0xff;
289 mac[4] = (laddr >> 8) & 0xff;
290 mac[5] = laddr & 0xff;
291
292 return 0;
293 }
294
295 /*
296 * disable transmitter, receiver
297 */
ftgmac100_stop(struct udevice * dev)298 static void ftgmac100_stop(struct udevice *dev)
299 {
300 struct ftgmac100_data *priv = dev_get_priv(dev);
301 struct ftgmac100 *ftgmac100 = priv->iobase;
302
303 debug("%s()\n", __func__);
304
305 writel(0, &ftgmac100->maccr);
306
307 phy_shutdown(priv->phydev);
308 }
309
ftgmac100_start(struct udevice * dev)310 static int ftgmac100_start(struct udevice *dev)
311 {
312 struct eth_pdata *plat = dev_get_plat(dev);
313 struct ftgmac100_data *priv = dev_get_priv(dev);
314 struct ftgmac100 *ftgmac100 = priv->iobase;
315 struct phy_device *phydev = priv->phydev;
316 unsigned int maccr;
317 ulong start, end;
318 int ret;
319 int i;
320
321 debug("%s()\n", __func__);
322
323 ftgmac100_reset(priv);
324
325 /* set the ethernet address */
326 ftgmac100_set_mac(priv, plat->enetaddr);
327
328 /* disable all interrupts */
329 writel(0, &ftgmac100->ier);
330
331 /* initialize descriptors */
332 priv->tx_index = 0;
333 priv->rx_index = 0;
334
335 for (i = 0; i < PKTBUFSTX; i++) {
336 priv->txdes[i].txdes3 = 0;
337 priv->txdes[i].txdes0 = 0;
338 }
339 priv->txdes[PKTBUFSTX - 1].txdes0 = priv->txdes0_edotr_mask;
340
341 start = ((ulong)&priv->txdes[0]) & ~(ARCH_DMA_MINALIGN - 1);
342 end = start + roundup(sizeof(priv->txdes), ARCH_DMA_MINALIGN);
343 flush_dcache_range(start, end);
344
345 for (i = 0; i < PKTBUFSRX; i++) {
346 priv->rxdes[i].rxdes3 = (unsigned int)net_rx_packets[i];
347 priv->rxdes[i].rxdes0 = 0;
348 }
349 priv->rxdes[PKTBUFSRX - 1].rxdes0 = priv->rxdes0_edorr_mask;
350
351 start = ((ulong)&priv->rxdes[0]) & ~(ARCH_DMA_MINALIGN - 1);
352 end = start + roundup(sizeof(priv->rxdes), ARCH_DMA_MINALIGN);
353 flush_dcache_range(start, end);
354
355 /* transmit ring */
356 writel((u32)priv->txdes, &ftgmac100->txr_badr);
357
358 /* receive ring */
359 writel((u32)priv->rxdes, &ftgmac100->rxr_badr);
360
361 /* poll receive descriptor automatically */
362 writel(FTGMAC100_APTC_RXPOLL_CNT(1), &ftgmac100->aptc);
363
364 /* config receive buffer size register */
365 writel(FTGMAC100_RBSR_SIZE(FTGMAC100_RBSR_DEFAULT), &ftgmac100->rbsr);
366
367 /* enable transmitter, receiver */
368 maccr = FTGMAC100_MACCR_TXMAC_EN |
369 FTGMAC100_MACCR_RXMAC_EN |
370 FTGMAC100_MACCR_TXDMA_EN |
371 FTGMAC100_MACCR_RXDMA_EN |
372 FTGMAC100_MACCR_CRC_APD |
373 FTGMAC100_MACCR_FULLDUP |
374 FTGMAC100_MACCR_RX_RUNT |
375 FTGMAC100_MACCR_RX_BROADPKT;
376
377 writel(maccr, &ftgmac100->maccr);
378
379 ret = phy_startup(phydev);
380 if (ret) {
381 dev_err(phydev->dev, "Could not start PHY\n");
382 return ret;
383 }
384
385 ret = ftgmac100_phy_adjust_link(priv);
386 if (ret) {
387 dev_err(phydev->dev, "Could not adjust link\n");
388 return ret;
389 }
390
391 printf("%s: link up, %d Mbps %s-duplex mac:%pM\n", phydev->dev->name,
392 phydev->speed, phydev->duplex ? "full" : "half", plat->enetaddr);
393
394 return 0;
395 }
396
ftgmac100_free_pkt(struct udevice * dev,uchar * packet,int length)397 static int ftgmac100_free_pkt(struct udevice *dev, uchar *packet, int length)
398 {
399 struct ftgmac100_data *priv = dev_get_priv(dev);
400 struct ftgmac100_rxdes *curr_des = &priv->rxdes[priv->rx_index];
401 ulong des_start = ((ulong)curr_des) & ~(ARCH_DMA_MINALIGN - 1);
402 ulong des_end = des_start +
403 roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
404
405 /* Release buffer to DMA and flush descriptor */
406 curr_des->rxdes0 &= ~FTGMAC100_RXDES0_RXPKT_RDY;
407 flush_dcache_range(des_start, des_end);
408
409 /* Move to next descriptor */
410 priv->rx_index = (priv->rx_index + 1) % PKTBUFSRX;
411
412 return 0;
413 }
414
415 /*
416 * Get a data block via Ethernet
417 */
ftgmac100_recv(struct udevice * dev,int flags,uchar ** packetp)418 static int ftgmac100_recv(struct udevice *dev, int flags, uchar **packetp)
419 {
420 struct ftgmac100_data *priv = dev_get_priv(dev);
421 struct ftgmac100_rxdes *curr_des = &priv->rxdes[priv->rx_index];
422 unsigned short rxlen;
423 ulong des_start = ((ulong)curr_des) & ~(ARCH_DMA_MINALIGN - 1);
424 ulong des_end = des_start +
425 roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
426 ulong data_start = curr_des->rxdes3;
427 ulong data_end;
428
429 invalidate_dcache_range(des_start, des_end);
430
431 if (!(curr_des->rxdes0 & FTGMAC100_RXDES0_RXPKT_RDY))
432 return -EAGAIN;
433
434 if (curr_des->rxdes0 & (FTGMAC100_RXDES0_RX_ERR |
435 FTGMAC100_RXDES0_CRC_ERR |
436 FTGMAC100_RXDES0_FTL |
437 FTGMAC100_RXDES0_RUNT |
438 FTGMAC100_RXDES0_RX_ODD_NB)) {
439 return -EAGAIN;
440 }
441
442 rxlen = FTGMAC100_RXDES0_VDBC(curr_des->rxdes0);
443
444 debug("%s(): RX buffer %d, %x received\n",
445 __func__, priv->rx_index, rxlen);
446
447 /* Invalidate received data */
448 data_end = data_start + roundup(rxlen, ARCH_DMA_MINALIGN);
449 invalidate_dcache_range(data_start, data_end);
450 *packetp = (uchar *)data_start;
451
452 return rxlen;
453 }
454
ftgmac100_read_txdesc(const void * desc)455 static u32 ftgmac100_read_txdesc(const void *desc)
456 {
457 const struct ftgmac100_txdes *txdes = desc;
458 ulong des_start = ((ulong)txdes) & ~(ARCH_DMA_MINALIGN - 1);
459 ulong des_end = des_start + roundup(sizeof(*txdes), ARCH_DMA_MINALIGN);
460
461 invalidate_dcache_range(des_start, des_end);
462
463 return txdes->txdes0;
464 }
465
BUILD_WAIT_FOR_BIT(ftgmac100_txdone,u32,ftgmac100_read_txdesc)466 BUILD_WAIT_FOR_BIT(ftgmac100_txdone, u32, ftgmac100_read_txdesc)
467
468 /*
469 * Send a data block via Ethernet
470 */
471 static int ftgmac100_send(struct udevice *dev, void *packet, int length)
472 {
473 struct ftgmac100_data *priv = dev_get_priv(dev);
474 struct ftgmac100 *ftgmac100 = priv->iobase;
475 struct ftgmac100_txdes *curr_des = &priv->txdes[priv->tx_index];
476 ulong des_start = ((ulong)curr_des) & ~(ARCH_DMA_MINALIGN - 1);
477 ulong des_end = des_start +
478 roundup(sizeof(*curr_des), ARCH_DMA_MINALIGN);
479 ulong data_start;
480 ulong data_end;
481 int rc;
482
483 invalidate_dcache_range(des_start, des_end);
484
485 if (curr_des->txdes0 & FTGMAC100_TXDES0_TXDMA_OWN) {
486 dev_err(dev, "no TX descriptor available\n");
487 return -EPERM;
488 }
489
490 debug("%s(%x, %x)\n", __func__, (int)packet, length);
491
492 length = (length < ETH_ZLEN) ? ETH_ZLEN : length;
493
494 curr_des->txdes3 = (unsigned int)packet;
495
496 /* Flush data to be sent */
497 data_start = curr_des->txdes3;
498 data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
499 flush_dcache_range(data_start, data_end);
500
501 /* Only one segment on TXBUF */
502 curr_des->txdes0 &= priv->txdes0_edotr_mask;
503 curr_des->txdes0 |= FTGMAC100_TXDES0_FTS |
504 FTGMAC100_TXDES0_LTS |
505 FTGMAC100_TXDES0_TXBUF_SIZE(length) |
506 FTGMAC100_TXDES0_TXDMA_OWN ;
507
508 /* Flush modified buffer descriptor */
509 flush_dcache_range(des_start, des_end);
510
511 /* Start transmit */
512 writel(1, &ftgmac100->txpd);
513
514 rc = wait_for_bit_ftgmac100_txdone(curr_des,
515 FTGMAC100_TXDES0_TXDMA_OWN, false,
516 FTGMAC100_TX_TIMEOUT_MS, true);
517 if (rc)
518 return rc;
519
520 debug("%s(): packet sent\n", __func__);
521
522 /* Move to next descriptor */
523 priv->tx_index = (priv->tx_index + 1) % PKTBUFSTX;
524
525 return 0;
526 }
527
ftgmac100_write_hwaddr(struct udevice * dev)528 static int ftgmac100_write_hwaddr(struct udevice *dev)
529 {
530 struct eth_pdata *pdata = dev_get_plat(dev);
531 struct ftgmac100_data *priv = dev_get_priv(dev);
532
533 return ftgmac100_set_mac(priv, pdata->enetaddr);
534 }
535
ftgmac_read_hwaddr(struct udevice * dev)536 static int ftgmac_read_hwaddr(struct udevice *dev)
537 {
538 struct eth_pdata *pdata = dev_get_plat(dev);
539 struct ftgmac100_data *priv = dev_get_priv(dev);
540
541 return ftgmac100_get_mac(priv, pdata->enetaddr);
542 }
543
ftgmac100_of_to_plat(struct udevice * dev)544 static int ftgmac100_of_to_plat(struct udevice *dev)
545 {
546 struct eth_pdata *pdata = dev_get_plat(dev);
547 struct ftgmac100_data *priv = dev_get_priv(dev);
548 const char *phy_mode;
549
550 pdata->iobase = dev_read_addr(dev);
551 pdata->phy_interface = -1;
552 phy_mode = dev_read_string(dev, "phy-mode");
553 if (phy_mode)
554 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
555 if (pdata->phy_interface == -1) {
556 dev_err(dev, "Invalid PHY interface '%s'\n", phy_mode);
557 return -EINVAL;
558 }
559
560 pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0);
561
562 if (dev_get_driver_data(dev) == FTGMAC100_MODEL_ASPEED) {
563 priv->rxdes0_edorr_mask = BIT(30);
564 priv->txdes0_edotr_mask = BIT(30);
565 } else {
566 priv->rxdes0_edorr_mask = BIT(15);
567 priv->txdes0_edotr_mask = BIT(15);
568 }
569
570 return clk_get_bulk(dev, &priv->clks);
571 }
572
ftgmac100_probe(struct udevice * dev)573 static int ftgmac100_probe(struct udevice *dev)
574 {
575 struct eth_pdata *pdata = dev_get_plat(dev);
576 struct ftgmac100_data *priv = dev_get_priv(dev);
577 int ret;
578
579 priv->iobase = (struct ftgmac100 *)pdata->iobase;
580 priv->phy_mode = pdata->phy_interface;
581 priv->max_speed = pdata->max_speed;
582 priv->phy_addr = 0;
583
584 #ifdef CONFIG_PHY_ADDR
585 priv->phy_addr = CONFIG_PHY_ADDR;
586 #endif
587
588 ret = clk_enable_bulk(&priv->clks);
589 if (ret)
590 goto out;
591
592 ret = ftgmac100_mdio_init(dev);
593 if (ret) {
594 dev_err(dev, "Failed to initialize mdiobus: %d\n", ret);
595 goto out;
596 }
597
598 ret = ftgmac100_phy_init(dev);
599 if (ret) {
600 dev_err(dev, "Failed to initialize PHY: %d\n", ret);
601 goto out;
602 }
603
604 ftgmac_read_hwaddr(dev);
605
606 out:
607 if (ret)
608 clk_release_bulk(&priv->clks);
609
610 return ret;
611 }
612
ftgmac100_remove(struct udevice * dev)613 static int ftgmac100_remove(struct udevice *dev)
614 {
615 struct ftgmac100_data *priv = dev_get_priv(dev);
616
617 free(priv->phydev);
618 mdio_unregister(priv->bus);
619 mdio_free(priv->bus);
620 clk_release_bulk(&priv->clks);
621
622 return 0;
623 }
624
625 static const struct eth_ops ftgmac100_ops = {
626 .start = ftgmac100_start,
627 .send = ftgmac100_send,
628 .recv = ftgmac100_recv,
629 .stop = ftgmac100_stop,
630 .free_pkt = ftgmac100_free_pkt,
631 .write_hwaddr = ftgmac100_write_hwaddr,
632 };
633
634 static const struct udevice_id ftgmac100_ids[] = {
635 { .compatible = "faraday,ftgmac100", .data = FTGMAC100_MODEL_FARADAY },
636 { .compatible = "aspeed,ast2500-mac", .data = FTGMAC100_MODEL_ASPEED },
637 { }
638 };
639
640 U_BOOT_DRIVER(ftgmac100) = {
641 .name = "ftgmac100",
642 .id = UCLASS_ETH,
643 .of_match = ftgmac100_ids,
644 .of_to_plat = ftgmac100_of_to_plat,
645 .probe = ftgmac100_probe,
646 .remove = ftgmac100_remove,
647 .ops = &ftgmac100_ops,
648 .priv_auto = sizeof(struct ftgmac100_data),
649 .plat_auto = sizeof(struct eth_pdata),
650 .flags = DM_FLAG_ALLOC_PRIV_DMA,
651 };
652