1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2005-2006 Atmel Corporation 4 */ 5 #ifndef __DRIVERS_MACB_H__ 6 #define __DRIVERS_MACB_H__ 7 8 #define MACB_GREGS_NBR 16 9 #define MACB_GREGS_VERSION 2 10 #define MACB_MAX_QUEUES 8 11 12 /* MACB register offsets */ 13 #define MACB_NCR 0x0000 /* Network Control */ 14 #define MACB_NCFGR 0x0004 /* Network Config */ 15 #define MACB_NSR 0x0008 /* Network Status */ 16 #define MACB_TAR 0x000c /* AT91RM9200 only */ 17 #define MACB_TCR 0x0010 /* AT91RM9200 only */ 18 #define MACB_TSR 0x0014 /* Transmit Status */ 19 #define MACB_RBQP 0x0018 /* RX Q Base Address */ 20 #define MACB_TBQP 0x001c /* TX Q Base Address */ 21 #define MACB_RSR 0x0020 /* Receive Status */ 22 #define MACB_ISR 0x0024 /* Interrupt Status */ 23 #define MACB_IER 0x0028 /* Interrupt Enable */ 24 #define MACB_IDR 0x002c /* Interrupt Disable */ 25 #define MACB_IMR 0x0030 /* Interrupt Mask */ 26 #define MACB_MAN 0x0034 /* PHY Maintenance */ 27 #define MACB_PTR 0x0038 28 #define MACB_PFR 0x003c 29 #define MACB_FTO 0x0040 30 #define MACB_SCF 0x0044 31 #define MACB_MCF 0x0048 32 #define MACB_FRO 0x004c 33 #define MACB_FCSE 0x0050 34 #define MACB_ALE 0x0054 35 #define MACB_DTF 0x0058 36 #define MACB_LCOL 0x005c 37 #define MACB_EXCOL 0x0060 38 #define MACB_TUND 0x0064 39 #define MACB_CSE 0x0068 40 #define MACB_RRE 0x006c 41 #define MACB_ROVR 0x0070 42 #define MACB_RSE 0x0074 43 #define MACB_ELE 0x0078 44 #define MACB_RJA 0x007c 45 #define MACB_USF 0x0080 46 #define MACB_STE 0x0084 47 #define MACB_RLE 0x0088 48 #define MACB_TPF 0x008c 49 #define MACB_HRB 0x0090 50 #define MACB_HRT 0x0094 51 #define MACB_SA1B 0x0098 52 #define MACB_SA1T 0x009c 53 #define MACB_SA2B 0x00a0 54 #define MACB_SA2T 0x00a4 55 #define MACB_SA3B 0x00a8 56 #define MACB_SA3T 0x00ac 57 #define MACB_SA4B 0x00b0 58 #define MACB_SA4T 0x00b4 59 #define MACB_TID 0x00b8 60 #define MACB_TPQ 0x00bc 61 #define MACB_USRIO 0x00c0 62 #define MACB_WOL 0x00c4 63 #define MACB_MID 0x00fc 64 #define MACB_TBQPH 0x04C8 65 #define MACB_RBQPH 0x04D4 66 67 /* GEM register offsets. */ 68 #define GEM_NCFGR 0x0004 /* Network Config */ 69 #define GEM_USRIO 0x000c /* User IO */ 70 #define GEM_DMACFG 0x0010 /* DMA Configuration */ 71 #define GEM_JML 0x0048 /* Jumbo Max Length */ 72 #define GEM_HRB 0x0080 /* Hash Bottom */ 73 #define GEM_HRT 0x0084 /* Hash Top */ 74 #define GEM_SA1B 0x0088 /* Specific1 Bottom */ 75 #define GEM_SA1T 0x008C /* Specific1 Top */ 76 #define GEM_SA2B 0x0090 /* Specific2 Bottom */ 77 #define GEM_SA2T 0x0094 /* Specific2 Top */ 78 #define GEM_SA3B 0x0098 /* Specific3 Bottom */ 79 #define GEM_SA3T 0x009C /* Specific3 Top */ 80 #define GEM_SA4B 0x00A0 /* Specific4 Bottom */ 81 #define GEM_SA4T 0x00A4 /* Specific4 Top */ 82 #define GEM_EFTSH 0x00e8 /* PTP Event Frame Transmitted Seconds Register 47:32 */ 83 #define GEM_EFRSH 0x00ec /* PTP Event Frame Received Seconds Register 47:32 */ 84 #define GEM_PEFTSH 0x00f0 /* PTP Peer Event Frame Transmitted Seconds Register 47:32 */ 85 #define GEM_PEFRSH 0x00f4 /* PTP Peer Event Frame Received Seconds Register 47:32 */ 86 #define GEM_OTX 0x0100 /* Octets transmitted */ 87 #define GEM_OCTTXL 0x0100 /* Octets transmitted [31:0] */ 88 #define GEM_OCTTXH 0x0104 /* Octets transmitted [47:32] */ 89 #define GEM_TXCNT 0x0108 /* Frames Transmitted counter */ 90 #define GEM_TXBCCNT 0x010c /* Broadcast Frames counter */ 91 #define GEM_TXMCCNT 0x0110 /* Multicast Frames counter */ 92 #define GEM_TXPAUSECNT 0x0114 /* Pause Frames Transmitted Counter */ 93 #define GEM_TX64CNT 0x0118 /* 64 byte Frames TX counter */ 94 #define GEM_TX65CNT 0x011c /* 65-127 byte Frames TX counter */ 95 #define GEM_TX128CNT 0x0120 /* 128-255 byte Frames TX counter */ 96 #define GEM_TX256CNT 0x0124 /* 256-511 byte Frames TX counter */ 97 #define GEM_TX512CNT 0x0128 /* 512-1023 byte Frames TX counter */ 98 #define GEM_TX1024CNT 0x012c /* 1024-1518 byte Frames TX counter */ 99 #define GEM_TX1519CNT 0x0130 /* 1519+ byte Frames TX counter */ 100 #define GEM_TXURUNCNT 0x0134 /* TX under run error counter */ 101 #define GEM_SNGLCOLLCNT 0x0138 /* Single Collision Frame Counter */ 102 #define GEM_MULTICOLLCNT 0x013c /* Multiple Collision Frame Counter */ 103 #define GEM_EXCESSCOLLCNT 0x0140 /* Excessive Collision Frame Counter */ 104 #define GEM_LATECOLLCNT 0x0144 /* Late Collision Frame Counter */ 105 #define GEM_TXDEFERCNT 0x0148 /* Deferred Transmission Frame Counter */ 106 #define GEM_TXCSENSECNT 0x014c /* Carrier Sense Error Counter */ 107 #define GEM_ORX 0x0150 /* Octets received */ 108 #define GEM_OCTRXL 0x0150 /* Octets received [31:0] */ 109 #define GEM_OCTRXH 0x0154 /* Octets received [47:32] */ 110 #define GEM_RXCNT 0x0158 /* Frames Received Counter */ 111 #define GEM_RXBROADCNT 0x015c /* Broadcast Frames Received Counter */ 112 #define GEM_RXMULTICNT 0x0160 /* Multicast Frames Received Counter */ 113 #define GEM_RXPAUSECNT 0x0164 /* Pause Frames Received Counter */ 114 #define GEM_RX64CNT 0x0168 /* 64 byte Frames RX Counter */ 115 #define GEM_RX65CNT 0x016c /* 65-127 byte Frames RX Counter */ 116 #define GEM_RX128CNT 0x0170 /* 128-255 byte Frames RX Counter */ 117 #define GEM_RX256CNT 0x0174 /* 256-511 byte Frames RX Counter */ 118 #define GEM_RX512CNT 0x0178 /* 512-1023 byte Frames RX Counter */ 119 #define GEM_RX1024CNT 0x017c /* 1024-1518 byte Frames RX Counter */ 120 #define GEM_RX1519CNT 0x0180 /* 1519+ byte Frames RX Counter */ 121 #define GEM_RXUNDRCNT 0x0184 /* Undersize Frames Received Counter */ 122 #define GEM_RXOVRCNT 0x0188 /* Oversize Frames Received Counter */ 123 #define GEM_RXJABCNT 0x018c /* Jabbers Received Counter */ 124 #define GEM_RXFCSCNT 0x0190 /* Frame Check Sequence Error Counter */ 125 #define GEM_RXLENGTHCNT 0x0194 /* Length Field Error Counter */ 126 #define GEM_RXSYMBCNT 0x0198 /* Symbol Error Counter */ 127 #define GEM_RXALIGNCNT 0x019c /* Alignment Error Counter */ 128 #define GEM_RXRESERRCNT 0x01a0 /* Receive Resource Error Counter */ 129 #define GEM_RXORCNT 0x01a4 /* Receive Overrun Counter */ 130 #define GEM_RXIPCCNT 0x01a8 /* IP header Checksum Error Counter */ 131 #define GEM_RXTCPCCNT 0x01ac /* TCP Checksum Error Counter */ 132 #define GEM_RXUDPCCNT 0x01b0 /* UDP Checksum Error Counter */ 133 #define GEM_TISUBN 0x01bc /* 1588 Timer Increment Sub-ns */ 134 #define GEM_TSH 0x01c0 /* 1588 Timer Seconds High */ 135 #define GEM_TSL 0x01d0 /* 1588 Timer Seconds Low */ 136 #define GEM_TN 0x01d4 /* 1588 Timer Nanoseconds */ 137 #define GEM_TA 0x01d8 /* 1588 Timer Adjust */ 138 #define GEM_TI 0x01dc /* 1588 Timer Increment */ 139 #define GEM_EFTSL 0x01e0 /* PTP Event Frame Tx Seconds Low */ 140 #define GEM_EFTN 0x01e4 /* PTP Event Frame Tx Nanoseconds */ 141 #define GEM_EFRSL 0x01e8 /* PTP Event Frame Rx Seconds Low */ 142 #define GEM_EFRN 0x01ec /* PTP Event Frame Rx Nanoseconds */ 143 #define GEM_PEFTSL 0x01f0 /* PTP Peer Event Frame Tx Secs Low */ 144 #define GEM_PEFTN 0x01f4 /* PTP Peer Event Frame Tx Ns */ 145 #define GEM_PEFRSL 0x01f8 /* PTP Peer Event Frame Rx Sec Low */ 146 #define GEM_PEFRN 0x01fc /* PTP Peer Event Frame Rx Ns */ 147 #define GEM_DCFG1 0x0280 /* Design Config 1 */ 148 #define GEM_DCFG2 0x0284 /* Design Config 2 */ 149 #define GEM_DCFG3 0x0288 /* Design Config 3 */ 150 #define GEM_DCFG4 0x028c /* Design Config 4 */ 151 #define GEM_DCFG5 0x0290 /* Design Config 5 */ 152 #define GEM_DCFG6 0x0294 /* Design Config 6 */ 153 #define GEM_DCFG7 0x0298 /* Design Config 7 */ 154 #define GEM_DCFG8 0x029C /* Design Config 8 */ 155 #define GEM_DCFG10 0x02A4 /* Design Config 10 */ 156 157 #define GEM_TXBDCTRL 0x04cc /* TX Buffer Descriptor control register */ 158 #define GEM_RXBDCTRL 0x04d0 /* RX Buffer Descriptor control register */ 159 160 /* Screener Type 2 match registers */ 161 #define GEM_SCRT2 0x540 162 163 /* EtherType registers */ 164 #define GEM_ETHT 0x06E0 165 166 /* Type 2 compare registers */ 167 #define GEM_T2CMPW0 0x0700 168 #define GEM_T2CMPW1 0x0704 169 #define T2CMP_OFST(t2idx) (t2idx * 2) 170 171 /* type 2 compare registers 172 * each location requires 3 compare regs 173 */ 174 #define GEM_IP4SRC_CMP(idx) (idx * 3) 175 #define GEM_IP4DST_CMP(idx) (idx * 3 + 1) 176 #define GEM_PORT_CMP(idx) (idx * 3 + 2) 177 178 /* Which screening type 2 EtherType register will be used (0 - 7) */ 179 #define SCRT2_ETHT 0 180 181 #define GEM_ISR(hw_q) (0x0400 + ((hw_q) << 2)) 182 #define GEM_TBQP(hw_q) (0x0440 + ((hw_q) << 2)) 183 #define GEM_TBQPH(hw_q) (0x04C8) 184 #define GEM_RBQP(hw_q) (0x0480 + ((hw_q) << 2)) 185 #define GEM_RBQS(hw_q) (0x04A0 + ((hw_q) << 2)) 186 #define GEM_RBQPH(hw_q) (0x04D4) 187 #define GEM_IER(hw_q) (0x0600 + ((hw_q) << 2)) 188 #define GEM_IDR(hw_q) (0x0620 + ((hw_q) << 2)) 189 #define GEM_IMR(hw_q) (0x0640 + ((hw_q) << 2)) 190 191 /* Bitfields in NCR */ 192 #define MACB_LB_OFFSET 0 /* reserved */ 193 #define MACB_LB_SIZE 1 194 #define MACB_LLB_OFFSET 1 /* Loop back local */ 195 #define MACB_LLB_SIZE 1 196 #define MACB_RE_OFFSET 2 /* Receive enable */ 197 #define MACB_RE_SIZE 1 198 #define MACB_TE_OFFSET 3 /* Transmit enable */ 199 #define MACB_TE_SIZE 1 200 #define MACB_MPE_OFFSET 4 /* Management port enable */ 201 #define MACB_MPE_SIZE 1 202 #define MACB_CLRSTAT_OFFSET 5 /* Clear stats regs */ 203 #define MACB_CLRSTAT_SIZE 1 204 #define MACB_INCSTAT_OFFSET 6 /* Incremental stats regs */ 205 #define MACB_INCSTAT_SIZE 1 206 #define MACB_WESTAT_OFFSET 7 /* Write enable stats regs */ 207 #define MACB_WESTAT_SIZE 1 208 #define MACB_BP_OFFSET 8 /* Back pressure */ 209 #define MACB_BP_SIZE 1 210 #define MACB_TSTART_OFFSET 9 /* Start transmission */ 211 #define MACB_TSTART_SIZE 1 212 #define MACB_THALT_OFFSET 10 /* Transmit halt */ 213 #define MACB_THALT_SIZE 1 214 #define MACB_NCR_TPF_OFFSET 11 /* Transmit pause frame */ 215 #define MACB_NCR_TPF_SIZE 1 216 #define MACB_TZQ_OFFSET 12 /* Transmit zero quantum pause frame */ 217 #define MACB_TZQ_SIZE 1 218 #define MACB_SRTSM_OFFSET 15 219 #define MACB_OSSMODE_OFFSET 24 /* Enable One Step Synchro Mode */ 220 #define MACB_OSSMODE_SIZE 1 221 222 /* Bitfields in NCFGR */ 223 #define MACB_SPD_OFFSET 0 /* Speed */ 224 #define MACB_SPD_SIZE 1 225 #define MACB_FD_OFFSET 1 /* Full duplex */ 226 #define MACB_FD_SIZE 1 227 #define MACB_BIT_RATE_OFFSET 2 /* Discard non-VLAN frames */ 228 #define MACB_BIT_RATE_SIZE 1 229 #define MACB_JFRAME_OFFSET 3 /* reserved */ 230 #define MACB_JFRAME_SIZE 1 231 #define MACB_CAF_OFFSET 4 /* Copy all frames */ 232 #define MACB_CAF_SIZE 1 233 #define MACB_NBC_OFFSET 5 /* No broadcast */ 234 #define MACB_NBC_SIZE 1 235 #define MACB_NCFGR_MTI_OFFSET 6 /* Multicast hash enable */ 236 #define MACB_NCFGR_MTI_SIZE 1 237 #define MACB_UNI_OFFSET 7 /* Unicast hash enable */ 238 #define MACB_UNI_SIZE 1 239 #define MACB_BIG_OFFSET 8 /* Receive 1536 byte frames */ 240 #define MACB_BIG_SIZE 1 241 #define MACB_EAE_OFFSET 9 /* External address match enable */ 242 #define MACB_EAE_SIZE 1 243 #define MACB_CLK_OFFSET 10 244 #define MACB_CLK_SIZE 2 245 #define MACB_RTY_OFFSET 12 /* Retry test */ 246 #define MACB_RTY_SIZE 1 247 #define MACB_PAE_OFFSET 13 /* Pause enable */ 248 #define MACB_PAE_SIZE 1 249 #define MACB_RM9200_RMII_OFFSET 13 /* AT91RM9200 only */ 250 #define MACB_RM9200_RMII_SIZE 1 /* AT91RM9200 only */ 251 #define MACB_RBOF_OFFSET 14 /* Receive buffer offset */ 252 #define MACB_RBOF_SIZE 2 253 #define MACB_RLCE_OFFSET 16 /* Length field error frame discard */ 254 #define MACB_RLCE_SIZE 1 255 #define MACB_DRFCS_OFFSET 17 /* FCS remove */ 256 #define MACB_DRFCS_SIZE 1 257 #define MACB_EFRHD_OFFSET 18 258 #define MACB_EFRHD_SIZE 1 259 #define MACB_IRXFCS_OFFSET 19 260 #define MACB_IRXFCS_SIZE 1 261 262 /* GEM specific NCFGR bitfields. */ 263 #define GEM_GBE_OFFSET 10 /* Gigabit mode enable */ 264 #define GEM_GBE_SIZE 1 265 #define GEM_PCSSEL_OFFSET 11 266 #define GEM_PCSSEL_SIZE 1 267 #define GEM_CLK_OFFSET 18 /* MDC clock division */ 268 #define GEM_CLK_SIZE 3 269 #define GEM_DBW_OFFSET 21 /* Data bus width */ 270 #define GEM_DBW_SIZE 2 271 #define GEM_RXCOEN_OFFSET 24 272 #define GEM_RXCOEN_SIZE 1 273 #define GEM_SGMIIEN_OFFSET 27 274 #define GEM_SGMIIEN_SIZE 1 275 276 277 /* Constants for data bus width. */ 278 #define GEM_DBW32 0 /* 32 bit AMBA AHB data bus width */ 279 #define GEM_DBW64 1 /* 64 bit AMBA AHB data bus width */ 280 #define GEM_DBW128 2 /* 128 bit AMBA AHB data bus width */ 281 282 /* Bitfields in DMACFG. */ 283 #define GEM_FBLDO_OFFSET 0 /* fixed burst length for DMA */ 284 #define GEM_FBLDO_SIZE 5 285 #define GEM_ENDIA_DESC_OFFSET 6 /* endian swap mode for management descriptor access */ 286 #define GEM_ENDIA_DESC_SIZE 1 287 #define GEM_ENDIA_PKT_OFFSET 7 /* endian swap mode for packet data access */ 288 #define GEM_ENDIA_PKT_SIZE 1 289 #define GEM_RXBMS_OFFSET 8 /* RX packet buffer memory size select */ 290 #define GEM_RXBMS_SIZE 2 291 #define GEM_TXPBMS_OFFSET 10 /* TX packet buffer memory size select */ 292 #define GEM_TXPBMS_SIZE 1 293 #define GEM_TXCOEN_OFFSET 11 /* TX IP/TCP/UDP checksum gen offload */ 294 #define GEM_TXCOEN_SIZE 1 295 #define GEM_RXBS_OFFSET 16 /* DMA receive buffer size */ 296 #define GEM_RXBS_SIZE 8 297 #define GEM_DDRP_OFFSET 24 /* disc_when_no_ahb */ 298 #define GEM_DDRP_SIZE 1 299 #define GEM_RXEXT_OFFSET 28 /* RX extended Buffer Descriptor mode */ 300 #define GEM_RXEXT_SIZE 1 301 #define GEM_TXEXT_OFFSET 29 /* TX extended Buffer Descriptor mode */ 302 #define GEM_TXEXT_SIZE 1 303 #define GEM_ADDR64_OFFSET 30 /* Address bus width - 64b or 32b */ 304 #define GEM_ADDR64_SIZE 1 305 306 307 /* Bitfields in NSR */ 308 #define MACB_NSR_LINK_OFFSET 0 /* pcs_link_state */ 309 #define MACB_NSR_LINK_SIZE 1 310 #define MACB_MDIO_OFFSET 1 /* status of the mdio_in pin */ 311 #define MACB_MDIO_SIZE 1 312 #define MACB_IDLE_OFFSET 2 /* The PHY management logic is idle */ 313 #define MACB_IDLE_SIZE 1 314 315 /* Bitfields in TSR */ 316 #define MACB_UBR_OFFSET 0 /* Used bit read */ 317 #define MACB_UBR_SIZE 1 318 #define MACB_COL_OFFSET 1 /* Collision occurred */ 319 #define MACB_COL_SIZE 1 320 #define MACB_TSR_RLE_OFFSET 2 /* Retry limit exceeded */ 321 #define MACB_TSR_RLE_SIZE 1 322 #define MACB_TGO_OFFSET 3 /* Transmit go */ 323 #define MACB_TGO_SIZE 1 324 #define MACB_BEX_OFFSET 4 /* TX frame corruption due to AHB error */ 325 #define MACB_BEX_SIZE 1 326 #define MACB_RM9200_BNQ_OFFSET 4 /* AT91RM9200 only */ 327 #define MACB_RM9200_BNQ_SIZE 1 /* AT91RM9200 only */ 328 #define MACB_COMP_OFFSET 5 /* Trnasmit complete */ 329 #define MACB_COMP_SIZE 1 330 #define MACB_UND_OFFSET 6 /* Trnasmit under run */ 331 #define MACB_UND_SIZE 1 332 333 /* Bitfields in RSR */ 334 #define MACB_BNA_OFFSET 0 /* Buffer not available */ 335 #define MACB_BNA_SIZE 1 336 #define MACB_REC_OFFSET 1 /* Frame received */ 337 #define MACB_REC_SIZE 1 338 #define MACB_OVR_OFFSET 2 /* Receive overrun */ 339 #define MACB_OVR_SIZE 1 340 341 /* Bitfields in ISR/IER/IDR/IMR */ 342 #define MACB_MFD_OFFSET 0 /* Management frame sent */ 343 #define MACB_MFD_SIZE 1 344 #define MACB_RCOMP_OFFSET 1 /* Receive complete */ 345 #define MACB_RCOMP_SIZE 1 346 #define MACB_RXUBR_OFFSET 2 /* RX used bit read */ 347 #define MACB_RXUBR_SIZE 1 348 #define MACB_TXUBR_OFFSET 3 /* TX used bit read */ 349 #define MACB_TXUBR_SIZE 1 350 #define MACB_ISR_TUND_OFFSET 4 /* Enable TX buffer under run interrupt */ 351 #define MACB_ISR_TUND_SIZE 1 352 #define MACB_ISR_RLE_OFFSET 5 /* EN retry exceeded/late coll interrupt */ 353 #define MACB_ISR_RLE_SIZE 1 354 #define MACB_TXERR_OFFSET 6 /* EN TX frame corrupt from error interrupt */ 355 #define MACB_TXERR_SIZE 1 356 #define MACB_TCOMP_OFFSET 7 /* Enable transmit complete interrupt */ 357 #define MACB_TCOMP_SIZE 1 358 #define MACB_ISR_LINK_OFFSET 9 /* Enable link change interrupt */ 359 #define MACB_ISR_LINK_SIZE 1 360 #define MACB_ISR_ROVR_OFFSET 10 /* Enable receive overrun interrupt */ 361 #define MACB_ISR_ROVR_SIZE 1 362 #define MACB_HRESP_OFFSET 11 /* Enable hrsep not OK interrupt */ 363 #define MACB_HRESP_SIZE 1 364 #define MACB_PFR_OFFSET 12 /* Enable pause frame w/ quantum interrupt */ 365 #define MACB_PFR_SIZE 1 366 #define MACB_PTZ_OFFSET 13 /* Enable pause time zero interrupt */ 367 #define MACB_PTZ_SIZE 1 368 #define MACB_WOL_OFFSET 14 /* Enable wake-on-lan interrupt */ 369 #define MACB_WOL_SIZE 1 370 #define MACB_DRQFR_OFFSET 18 /* PTP Delay Request Frame Received */ 371 #define MACB_DRQFR_SIZE 1 372 #define MACB_SFR_OFFSET 19 /* PTP Sync Frame Received */ 373 #define MACB_SFR_SIZE 1 374 #define MACB_DRQFT_OFFSET 20 /* PTP Delay Request Frame Transmitted */ 375 #define MACB_DRQFT_SIZE 1 376 #define MACB_SFT_OFFSET 21 /* PTP Sync Frame Transmitted */ 377 #define MACB_SFT_SIZE 1 378 #define MACB_PDRQFR_OFFSET 22 /* PDelay Request Frame Received */ 379 #define MACB_PDRQFR_SIZE 1 380 #define MACB_PDRSFR_OFFSET 23 /* PDelay Response Frame Received */ 381 #define MACB_PDRSFR_SIZE 1 382 #define MACB_PDRQFT_OFFSET 24 /* PDelay Request Frame Transmitted */ 383 #define MACB_PDRQFT_SIZE 1 384 #define MACB_PDRSFT_OFFSET 25 /* PDelay Response Frame Transmitted */ 385 #define MACB_PDRSFT_SIZE 1 386 #define MACB_SRI_OFFSET 26 /* TSU Seconds Register Increment */ 387 #define MACB_SRI_SIZE 1 388 389 /* Timer increment fields */ 390 #define MACB_TI_CNS_OFFSET 0 391 #define MACB_TI_CNS_SIZE 8 392 #define MACB_TI_ACNS_OFFSET 8 393 #define MACB_TI_ACNS_SIZE 8 394 #define MACB_TI_NIT_OFFSET 16 395 #define MACB_TI_NIT_SIZE 8 396 397 /* Bitfields in MAN */ 398 #define MACB_DATA_OFFSET 0 /* data */ 399 #define MACB_DATA_SIZE 16 400 #define MACB_CODE_OFFSET 16 /* Must be written to 10 */ 401 #define MACB_CODE_SIZE 2 402 #define MACB_REGA_OFFSET 18 /* Register address */ 403 #define MACB_REGA_SIZE 5 404 #define MACB_PHYA_OFFSET 23 /* PHY address */ 405 #define MACB_PHYA_SIZE 5 406 #define MACB_RW_OFFSET 28 /* Operation. 10 is read. 01 is write. */ 407 #define MACB_RW_SIZE 2 408 #define MACB_SOF_OFFSET 30 /* Must be written to 1 for Clause 22 */ 409 #define MACB_SOF_SIZE 2 410 411 /* Bitfields in USRIO (AVR32) */ 412 #define MACB_MII_OFFSET 0 413 #define MACB_MII_SIZE 1 414 #define MACB_EAM_OFFSET 1 415 #define MACB_EAM_SIZE 1 416 #define MACB_TX_PAUSE_OFFSET 2 417 #define MACB_TX_PAUSE_SIZE 1 418 #define MACB_TX_PAUSE_ZERO_OFFSET 3 419 #define MACB_TX_PAUSE_ZERO_SIZE 1 420 421 /* Bitfields in USRIO (AT91) */ 422 #define MACB_RMII_OFFSET 0 423 #define MACB_RMII_SIZE 1 424 #define GEM_RGMII_OFFSET 0 /* GEM gigabit mode */ 425 #define GEM_RGMII_SIZE 1 426 #define MACB_CLKEN_OFFSET 1 427 #define MACB_CLKEN_SIZE 1 428 429 /* Bitfields in WOL */ 430 #define MACB_IP_OFFSET 0 431 #define MACB_IP_SIZE 16 432 #define MACB_MAG_OFFSET 16 433 #define MACB_MAG_SIZE 1 434 #define MACB_ARP_OFFSET 17 435 #define MACB_ARP_SIZE 1 436 #define MACB_SA1_OFFSET 18 437 #define MACB_SA1_SIZE 1 438 #define MACB_WOL_MTI_OFFSET 19 439 #define MACB_WOL_MTI_SIZE 1 440 441 /* Bitfields in MID */ 442 #define MACB_IDNUM_OFFSET 16 443 #define MACB_IDNUM_SIZE 12 444 #define MACB_REV_OFFSET 0 445 #define MACB_REV_SIZE 16 446 447 /* Bitfields in DCFG1. */ 448 #define GEM_IRQCOR_OFFSET 23 449 #define GEM_IRQCOR_SIZE 1 450 #define GEM_DBWDEF_OFFSET 25 451 #define GEM_DBWDEF_SIZE 3 452 453 /* Bitfields in DCFG2. */ 454 #define GEM_RX_PKT_BUFF_OFFSET 20 455 #define GEM_RX_PKT_BUFF_SIZE 1 456 #define GEM_TX_PKT_BUFF_OFFSET 21 457 #define GEM_TX_PKT_BUFF_SIZE 1 458 459 460 /* Bitfields in DCFG5. */ 461 #define GEM_TSU_OFFSET 8 462 #define GEM_TSU_SIZE 1 463 464 /* Bitfields in DCFG6. */ 465 #define GEM_PBUF_LSO_OFFSET 27 466 #define GEM_PBUF_LSO_SIZE 1 467 #define GEM_DAW64_OFFSET 23 468 #define GEM_DAW64_SIZE 1 469 470 /* Bitfields in DCFG8. */ 471 #define GEM_T1SCR_OFFSET 24 472 #define GEM_T1SCR_SIZE 8 473 #define GEM_T2SCR_OFFSET 16 474 #define GEM_T2SCR_SIZE 8 475 #define GEM_SCR2ETH_OFFSET 8 476 #define GEM_SCR2ETH_SIZE 8 477 #define GEM_SCR2CMP_OFFSET 0 478 #define GEM_SCR2CMP_SIZE 8 479 480 /* Bitfields in DCFG10 */ 481 #define GEM_TXBD_RDBUFF_OFFSET 12 482 #define GEM_TXBD_RDBUFF_SIZE 4 483 #define GEM_RXBD_RDBUFF_OFFSET 8 484 #define GEM_RXBD_RDBUFF_SIZE 4 485 486 /* Bitfields in TISUBN */ 487 #define GEM_SUBNSINCR_OFFSET 0 488 #define GEM_SUBNSINCR_SIZE 16 489 490 /* Bitfields in TI */ 491 #define GEM_NSINCR_OFFSET 0 492 #define GEM_NSINCR_SIZE 8 493 494 /* Bitfields in TSH */ 495 #define GEM_TSH_OFFSET 0 /* TSU timer value (s). MSB [47:32] of seconds timer count */ 496 #define GEM_TSH_SIZE 16 497 498 /* Bitfields in TSL */ 499 #define GEM_TSL_OFFSET 0 /* TSU timer value (s). LSB [31:0] of seconds timer count */ 500 #define GEM_TSL_SIZE 32 501 502 /* Bitfields in TN */ 503 #define GEM_TN_OFFSET 0 /* TSU timer value (ns) */ 504 #define GEM_TN_SIZE 30 505 506 /* Bitfields in TXBDCTRL */ 507 #define GEM_TXTSMODE_OFFSET 4 /* TX Descriptor Timestamp Insertion mode */ 508 #define GEM_TXTSMODE_SIZE 2 509 510 /* Bitfields in RXBDCTRL */ 511 #define GEM_RXTSMODE_OFFSET 4 /* RX Descriptor Timestamp Insertion mode */ 512 #define GEM_RXTSMODE_SIZE 2 513 514 /* Bitfields in SCRT2 */ 515 #define GEM_QUEUE_OFFSET 0 /* Queue Number */ 516 #define GEM_QUEUE_SIZE 4 517 #define GEM_VLANPR_OFFSET 4 /* VLAN Priority */ 518 #define GEM_VLANPR_SIZE 3 519 #define GEM_VLANEN_OFFSET 8 /* VLAN Enable */ 520 #define GEM_VLANEN_SIZE 1 521 #define GEM_ETHT2IDX_OFFSET 9 /* Index to screener type 2 EtherType register */ 522 #define GEM_ETHT2IDX_SIZE 3 523 #define GEM_ETHTEN_OFFSET 12 /* EtherType Enable */ 524 #define GEM_ETHTEN_SIZE 1 525 #define GEM_CMPA_OFFSET 13 /* Compare A - Index to screener type 2 Compare register */ 526 #define GEM_CMPA_SIZE 5 527 #define GEM_CMPAEN_OFFSET 18 /* Compare A Enable */ 528 #define GEM_CMPAEN_SIZE 1 529 #define GEM_CMPB_OFFSET 19 /* Compare B - Index to screener type 2 Compare register */ 530 #define GEM_CMPB_SIZE 5 531 #define GEM_CMPBEN_OFFSET 24 /* Compare B Enable */ 532 #define GEM_CMPBEN_SIZE 1 533 #define GEM_CMPC_OFFSET 25 /* Compare C - Index to screener type 2 Compare register */ 534 #define GEM_CMPC_SIZE 5 535 #define GEM_CMPCEN_OFFSET 30 /* Compare C Enable */ 536 #define GEM_CMPCEN_SIZE 1 537 538 /* Bitfields in ETHT */ 539 #define GEM_ETHTCMP_OFFSET 0 /* EtherType compare value */ 540 #define GEM_ETHTCMP_SIZE 16 541 542 /* Bitfields in T2CMPW0 */ 543 #define GEM_T2CMP_OFFSET 16 /* 0xFFFF0000 compare value */ 544 #define GEM_T2CMP_SIZE 16 545 #define GEM_T2MASK_OFFSET 0 /* 0x0000FFFF compare value or mask */ 546 #define GEM_T2MASK_SIZE 16 547 548 /* Bitfields in T2CMPW1 */ 549 #define GEM_T2DISMSK_OFFSET 9 /* disable mask */ 550 #define GEM_T2DISMSK_SIZE 1 551 #define GEM_T2CMPOFST_OFFSET 7 /* compare offset */ 552 #define GEM_T2CMPOFST_SIZE 2 553 #define GEM_T2OFST_OFFSET 0 /* offset value */ 554 #define GEM_T2OFST_SIZE 7 555 556 /* Offset for screener type 2 compare values (T2CMPOFST). 557 * Note the offset is applied after the specified point, 558 * e.g. GEM_T2COMPOFST_ETYPE denotes the EtherType field, so an offset 559 * of 12 bytes from this would be the source IP address in an IP header 560 */ 561 #define GEM_T2COMPOFST_SOF 0 562 #define GEM_T2COMPOFST_ETYPE 1 563 #define GEM_T2COMPOFST_IPHDR 2 564 #define GEM_T2COMPOFST_TCPUDP 3 565 566 /* offset from EtherType to IP address */ 567 #define ETYPE_SRCIP_OFFSET 12 568 #define ETYPE_DSTIP_OFFSET 16 569 570 /* offset from IP header to port */ 571 #define IPHDR_SRCPORT_OFFSET 0 572 #define IPHDR_DSTPORT_OFFSET 2 573 574 /* Transmit DMA buffer descriptor Word 1 */ 575 #define GEM_DMA_TXVALID_OFFSET 23 /* timestamp has been captured in the Buffer Descriptor */ 576 #define GEM_DMA_TXVALID_SIZE 1 577 578 /* Receive DMA buffer descriptor Word 0 */ 579 #define GEM_DMA_RXVALID_OFFSET 2 /* indicates a valid timestamp in the Buffer Descriptor */ 580 #define GEM_DMA_RXVALID_SIZE 1 581 582 /* DMA buffer descriptor Word 2 (32 bit addressing) or Word 4 (64 bit addressing) */ 583 #define GEM_DMA_SECL_OFFSET 30 /* Timestamp seconds[1:0] */ 584 #define GEM_DMA_SECL_SIZE 2 585 #define GEM_DMA_NSEC_OFFSET 0 /* Timestamp nanosecs [29:0] */ 586 #define GEM_DMA_NSEC_SIZE 30 587 588 /* DMA buffer descriptor Word 3 (32 bit addressing) or Word 5 (64 bit addressing) */ 589 590 /* New hardware supports 12 bit precision of timestamp in DMA buffer descriptor. 591 * Old hardware supports only 6 bit precision but it is enough for PTP. 592 * Less accuracy is used always instead of checking hardware version. 593 */ 594 #define GEM_DMA_SECH_OFFSET 0 /* Timestamp seconds[5:2] */ 595 #define GEM_DMA_SECH_SIZE 4 596 #define GEM_DMA_SEC_WIDTH (GEM_DMA_SECH_SIZE + GEM_DMA_SECL_SIZE) 597 #define GEM_DMA_SEC_TOP (1 << GEM_DMA_SEC_WIDTH) 598 #define GEM_DMA_SEC_MASK (GEM_DMA_SEC_TOP - 1) 599 600 /* Bitfields in ADJ */ 601 #define GEM_ADDSUB_OFFSET 31 602 #define GEM_ADDSUB_SIZE 1 603 /* Constants for CLK */ 604 #define MACB_CLK_DIV8 0 605 #define MACB_CLK_DIV16 1 606 #define MACB_CLK_DIV32 2 607 #define MACB_CLK_DIV64 3 608 609 /* GEM specific constants for CLK */ 610 #define GEM_CLK_DIV8 0 611 #define GEM_CLK_DIV16 1 612 #define GEM_CLK_DIV32 2 613 #define GEM_CLK_DIV48 3 614 #define GEM_CLK_DIV64 4 615 #define GEM_CLK_DIV96 5 616 #define GEM_CLK_DIV128 6 617 #define GEM_CLK_DIV224 7 618 619 /* Constants for MAN register */ 620 #define MACB_MAN_SOF 1 621 #define MACB_MAN_WRITE 1 622 #define MACB_MAN_READ 2 623 #define MACB_MAN_CODE 2 624 625 /* Capability mask bits */ 626 #define MACB_CAPS_ISR_CLEAR_ON_WRITE 0x00000001 627 #define MACB_CAPS_USRIO_HAS_CLKEN 0x00000002 628 #define MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII 0x00000004 629 #define MACB_CAPS_NO_GIGABIT_HALF 0x00000008 630 #define MACB_CAPS_USRIO_DISABLED 0x00000010 631 #define MACB_CAPS_JUMBO 0x00000020 632 #define MACB_CAPS_GEM_HAS_PTP 0x00000040 633 #define MACB_CAPS_BD_RD_PREFETCH 0x00000080 634 #define MACB_CAPS_NEEDS_RSTONUBR 0x00000100 635 #define MACB_CAPS_FIFO_MODE 0x10000000 636 #define MACB_CAPS_GIGABIT_MODE_AVAILABLE 0x20000000 637 #define MACB_CAPS_SG_DISABLED 0x40000000 638 #define MACB_CAPS_MACB_IS_GEM 0x80000000 639 640 /* LSO settings */ 641 #define MACB_LSO_UFO_ENABLE 0x01 642 #define MACB_LSO_TSO_ENABLE 0x02 643 644 /* Bit manipulation macros */ 645 #define MACB_BIT(name) \ 646 (1 << MACB_##name##_OFFSET) 647 #define MACB_BF(name,value) \ 648 (((value) & ((1 << MACB_##name##_SIZE) - 1)) \ 649 << MACB_##name##_OFFSET) 650 #define MACB_BFEXT(name,value)\ 651 (((value) >> MACB_##name##_OFFSET) \ 652 & ((1 << MACB_##name##_SIZE) - 1)) 653 #define MACB_BFINS(name,value,old) \ 654 (((old) & ~(((1 << MACB_##name##_SIZE) - 1) \ 655 << MACB_##name##_OFFSET)) \ 656 | MACB_BF(name,value)) 657 658 #define GEM_BIT(name) \ 659 (1 << GEM_##name##_OFFSET) 660 #define GEM_BF(name, value) \ 661 (((value) & ((1 << GEM_##name##_SIZE) - 1)) \ 662 << GEM_##name##_OFFSET) 663 #define GEM_BFEXT(name, value)\ 664 (((value) >> GEM_##name##_OFFSET) \ 665 & ((1 << GEM_##name##_SIZE) - 1)) 666 #define GEM_BFINS(name, value, old) \ 667 (((old) & ~(((1 << GEM_##name##_SIZE) - 1) \ 668 << GEM_##name##_OFFSET)) \ 669 | GEM_BF(name, value)) 670 671 /* Register access macros */ 672 #define macb_readl(port, reg) \ 673 readl((port)->regs + MACB_##reg) 674 #define macb_writel(port, reg, value) \ 675 writel((value), (port)->regs + MACB_##reg) 676 #define gem_readl(port, reg) \ 677 readl((port)->regs + GEM_##reg) 678 #define gem_writel(port, reg, value) \ 679 writel((value), (port)->regs + GEM_##reg) 680 681 /* DMA descriptor bitfields */ 682 #define MACB_RX_USED_OFFSET 0 683 #define MACB_RX_USED_SIZE 1 684 #define MACB_RX_WRAP_OFFSET 1 685 #define MACB_RX_WRAP_SIZE 1 686 #define MACB_RX_WADDR_OFFSET 2 687 #define MACB_RX_WADDR_SIZE 30 688 689 #define MACB_RX_FRMLEN_OFFSET 0 690 #define MACB_RX_FRMLEN_SIZE 12 691 #define MACB_RX_OFFSET_OFFSET 12 692 #define MACB_RX_OFFSET_SIZE 2 693 #define MACB_RX_SOF_OFFSET 14 694 #define MACB_RX_SOF_SIZE 1 695 #define MACB_RX_EOF_OFFSET 15 696 #define MACB_RX_EOF_SIZE 1 697 #define MACB_RX_CFI_OFFSET 16 698 #define MACB_RX_CFI_SIZE 1 699 #define MACB_RX_VLAN_PRI_OFFSET 17 700 #define MACB_RX_VLAN_PRI_SIZE 3 701 #define MACB_RX_PRI_TAG_OFFSET 20 702 #define MACB_RX_PRI_TAG_SIZE 1 703 #define MACB_RX_VLAN_TAG_OFFSET 21 704 #define MACB_RX_VLAN_TAG_SIZE 1 705 #define MACB_RX_TYPEID_MATCH_OFFSET 22 706 #define MACB_RX_TYPEID_MATCH_SIZE 1 707 #define MACB_RX_SA4_MATCH_OFFSET 23 708 #define MACB_RX_SA4_MATCH_SIZE 1 709 #define MACB_RX_SA3_MATCH_OFFSET 24 710 #define MACB_RX_SA3_MATCH_SIZE 1 711 #define MACB_RX_SA2_MATCH_OFFSET 25 712 #define MACB_RX_SA2_MATCH_SIZE 1 713 #define MACB_RX_SA1_MATCH_OFFSET 26 714 #define MACB_RX_SA1_MATCH_SIZE 1 715 #define MACB_RX_EXT_MATCH_OFFSET 28 716 #define MACB_RX_EXT_MATCH_SIZE 1 717 #define MACB_RX_UHASH_MATCH_OFFSET 29 718 #define MACB_RX_UHASH_MATCH_SIZE 1 719 #define MACB_RX_MHASH_MATCH_OFFSET 30 720 #define MACB_RX_MHASH_MATCH_SIZE 1 721 #define MACB_RX_BROADCAST_OFFSET 31 722 #define MACB_RX_BROADCAST_SIZE 1 723 724 #define MACB_RX_FRMLEN_MASK 0xFFF 725 #define MACB_RX_JFRMLEN_MASK 0x3FFF 726 727 /* RX checksum offload disabled: bit 24 clear in NCFGR */ 728 #define GEM_RX_TYPEID_MATCH_OFFSET 22 729 #define GEM_RX_TYPEID_MATCH_SIZE 2 730 731 /* RX checksum offload enabled: bit 24 set in NCFGR */ 732 #define GEM_RX_CSUM_OFFSET 22 733 #define GEM_RX_CSUM_SIZE 2 734 735 #define MACB_TX_FRMLEN_OFFSET 0 736 #define MACB_TX_FRMLEN_SIZE 11 737 #define MACB_TX_LAST_OFFSET 15 738 #define MACB_TX_LAST_SIZE 1 739 #define MACB_TX_NOCRC_OFFSET 16 740 #define MACB_TX_NOCRC_SIZE 1 741 #define MACB_MSS_MFS_OFFSET 16 742 #define MACB_MSS_MFS_SIZE 14 743 #define MACB_TX_LSO_OFFSET 17 744 #define MACB_TX_LSO_SIZE 2 745 #define MACB_TX_TCP_SEQ_SRC_OFFSET 19 746 #define MACB_TX_TCP_SEQ_SRC_SIZE 1 747 #define MACB_TX_BUF_EXHAUSTED_OFFSET 27 748 #define MACB_TX_BUF_EXHAUSTED_SIZE 1 749 #define MACB_TX_UNDERRUN_OFFSET 28 750 #define MACB_TX_UNDERRUN_SIZE 1 751 #define MACB_TX_ERROR_OFFSET 29 752 #define MACB_TX_ERROR_SIZE 1 753 #define MACB_TX_WRAP_OFFSET 30 754 #define MACB_TX_WRAP_SIZE 1 755 #define MACB_TX_USED_OFFSET 31 756 #define MACB_TX_USED_SIZE 1 757 758 #define GEM_TX_FRMLEN_OFFSET 0 759 #define GEM_TX_FRMLEN_SIZE 14 760 761 /* Buffer descriptor constants */ 762 #define GEM_RX_CSUM_NONE 0 763 #define GEM_RX_CSUM_IP_ONLY 1 764 #define GEM_RX_CSUM_IP_TCP 2 765 #define GEM_RX_CSUM_IP_UDP 3 766 767 /* limit RX checksum offload to TCP and UDP packets */ 768 #define GEM_RX_CSUM_CHECKED_MASK 2 769 #define gem_writel_queue_TBQP(port, value, queue_num) \ 770 writel((value), (port)->regs + GEM_TBQP(queue_num)) 771 #define gem_writel_queue_TBQPH(port, value, queue_num) \ 772 writel((value), (port)->regs + GEM_TBQPH(queue_num)) 773 #define gem_writel_queue_RBQP(port, value, queue_num) \ 774 writel((value), (port)->regs + GEM_RBQP(queue_num)) 775 #define gem_writel_queue_RBQPH(port, value, queue_num) \ 776 writel((value), (port)->regs + GEM_RBQPH(queue_num)) 777 778 #endif /* __DRIVERS_MACB_H__ */ 779