1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * drivers/net/ravb.c
4 * This file is driver for Renesas Ethernet AVB.
5 *
6 * Copyright (C) 2015-2017 Renesas Electronics Corporation
7 *
8 * Based on the SuperH Ethernet driver.
9 */
10
11 #include <common.h>
12 #include <clk.h>
13 #include <cpu_func.h>
14 #include <dm.h>
15 #include <errno.h>
16 #include <log.h>
17 #include <miiphy.h>
18 #include <malloc.h>
19 #include <asm/cache.h>
20 #include <linux/bitops.h>
21 #include <linux/delay.h>
22 #include <linux/mii.h>
23 #include <wait_bit.h>
24 #include <asm/io.h>
25 #include <asm/global_data.h>
26 #include <asm/gpio.h>
27
28 /* Registers */
29 #define RAVB_REG_CCC 0x000
30 #define RAVB_REG_DBAT 0x004
31 #define RAVB_REG_CSR 0x00C
32 #define RAVB_REG_APSR 0x08C
33 #define RAVB_REG_RCR 0x090
34 #define RAVB_REG_TGC 0x300
35 #define RAVB_REG_TCCR 0x304
36 #define RAVB_REG_RIC0 0x360
37 #define RAVB_REG_RIC1 0x368
38 #define RAVB_REG_RIC2 0x370
39 #define RAVB_REG_TIC 0x378
40 #define RAVB_REG_ECMR 0x500
41 #define RAVB_REG_RFLR 0x508
42 #define RAVB_REG_ECSIPR 0x518
43 #define RAVB_REG_PIR 0x520
44 #define RAVB_REG_GECMR 0x5b0
45 #define RAVB_REG_MAHR 0x5c0
46 #define RAVB_REG_MALR 0x5c8
47
48 #define CCC_OPC_CONFIG BIT(0)
49 #define CCC_OPC_OPERATION BIT(1)
50 #define CCC_BOC BIT(20)
51
52 #define CSR_OPS 0x0000000F
53 #define CSR_OPS_CONFIG BIT(1)
54
55 #define APSR_TDM BIT(14)
56
57 #define TCCR_TSRQ0 BIT(0)
58
59 #define RFLR_RFL_MIN 0x05EE
60
61 #define PIR_MDI BIT(3)
62 #define PIR_MDO BIT(2)
63 #define PIR_MMD BIT(1)
64 #define PIR_MDC BIT(0)
65
66 #define ECMR_TRCCM BIT(26)
67 #define ECMR_RZPF BIT(20)
68 #define ECMR_PFR BIT(18)
69 #define ECMR_RXF BIT(17)
70 #define ECMR_RE BIT(6)
71 #define ECMR_TE BIT(5)
72 #define ECMR_DM BIT(1)
73 #define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_PFR | ECMR_RXF)
74
75 /* DMA Descriptors */
76 #define RAVB_NUM_BASE_DESC 16
77 #define RAVB_NUM_TX_DESC 8
78 #define RAVB_NUM_RX_DESC 8
79
80 #define RAVB_TX_QUEUE_OFFSET 0
81 #define RAVB_RX_QUEUE_OFFSET 4
82
83 #define RAVB_DESC_DT(n) ((n) << 28)
84 #define RAVB_DESC_DT_FSINGLE RAVB_DESC_DT(0x7)
85 #define RAVB_DESC_DT_LINKFIX RAVB_DESC_DT(0x9)
86 #define RAVB_DESC_DT_EOS RAVB_DESC_DT(0xa)
87 #define RAVB_DESC_DT_FEMPTY RAVB_DESC_DT(0xc)
88 #define RAVB_DESC_DT_EEMPTY RAVB_DESC_DT(0x3)
89 #define RAVB_DESC_DT_MASK RAVB_DESC_DT(0xf)
90
91 #define RAVB_DESC_DS(n) (((n) & 0xfff) << 0)
92 #define RAVB_DESC_DS_MASK 0xfff
93
94 #define RAVB_RX_DESC_MSC_MC BIT(23)
95 #define RAVB_RX_DESC_MSC_CEEF BIT(22)
96 #define RAVB_RX_DESC_MSC_CRL BIT(21)
97 #define RAVB_RX_DESC_MSC_FRE BIT(20)
98 #define RAVB_RX_DESC_MSC_RTLF BIT(19)
99 #define RAVB_RX_DESC_MSC_RTSF BIT(18)
100 #define RAVB_RX_DESC_MSC_RFE BIT(17)
101 #define RAVB_RX_DESC_MSC_CRC BIT(16)
102 #define RAVB_RX_DESC_MSC_MASK (0xff << 16)
103
104 #define RAVB_RX_DESC_MSC_RX_ERR_MASK \
105 (RAVB_RX_DESC_MSC_CRC | RAVB_RX_DESC_MSC_RFE | RAVB_RX_DESC_MSC_RTLF | \
106 RAVB_RX_DESC_MSC_RTSF | RAVB_RX_DESC_MSC_CEEF)
107
108 #define RAVB_TX_TIMEOUT_MS 1000
109
110 struct ravb_desc {
111 u32 ctrl;
112 u32 dptr;
113 };
114
115 struct ravb_rxdesc {
116 struct ravb_desc data;
117 struct ravb_desc link;
118 u8 __pad[48];
119 u8 packet[PKTSIZE_ALIGN];
120 };
121
122 struct ravb_priv {
123 struct ravb_desc base_desc[RAVB_NUM_BASE_DESC];
124 struct ravb_desc tx_desc[RAVB_NUM_TX_DESC];
125 struct ravb_rxdesc rx_desc[RAVB_NUM_RX_DESC];
126 u32 rx_desc_idx;
127 u32 tx_desc_idx;
128
129 struct phy_device *phydev;
130 struct mii_dev *bus;
131 void __iomem *iobase;
132 struct clk clk;
133 struct gpio_desc reset_gpio;
134 };
135
ravb_flush_dcache(u32 addr,u32 len)136 static inline void ravb_flush_dcache(u32 addr, u32 len)
137 {
138 flush_dcache_range(addr, addr + len);
139 }
140
ravb_invalidate_dcache(u32 addr,u32 len)141 static inline void ravb_invalidate_dcache(u32 addr, u32 len)
142 {
143 u32 start = addr & ~((uintptr_t)ARCH_DMA_MINALIGN - 1);
144 u32 end = roundup(addr + len, ARCH_DMA_MINALIGN);
145 invalidate_dcache_range(start, end);
146 }
147
ravb_send(struct udevice * dev,void * packet,int len)148 static int ravb_send(struct udevice *dev, void *packet, int len)
149 {
150 struct ravb_priv *eth = dev_get_priv(dev);
151 struct ravb_desc *desc = ð->tx_desc[eth->tx_desc_idx];
152 unsigned int start;
153
154 /* Update TX descriptor */
155 ravb_flush_dcache((uintptr_t)packet, len);
156 memset(desc, 0x0, sizeof(*desc));
157 desc->ctrl = RAVB_DESC_DT_FSINGLE | RAVB_DESC_DS(len);
158 desc->dptr = (uintptr_t)packet;
159 ravb_flush_dcache((uintptr_t)desc, sizeof(*desc));
160
161 /* Restart the transmitter if disabled */
162 if (!(readl(eth->iobase + RAVB_REG_TCCR) & TCCR_TSRQ0))
163 setbits_le32(eth->iobase + RAVB_REG_TCCR, TCCR_TSRQ0);
164
165 /* Wait until packet is transmitted */
166 start = get_timer(0);
167 while (get_timer(start) < RAVB_TX_TIMEOUT_MS) {
168 ravb_invalidate_dcache((uintptr_t)desc, sizeof(*desc));
169 if ((desc->ctrl & RAVB_DESC_DT_MASK) != RAVB_DESC_DT_FSINGLE)
170 break;
171 udelay(10);
172 };
173
174 if (get_timer(start) >= RAVB_TX_TIMEOUT_MS)
175 return -ETIMEDOUT;
176
177 eth->tx_desc_idx = (eth->tx_desc_idx + 1) % (RAVB_NUM_TX_DESC - 1);
178 return 0;
179 }
180
ravb_recv(struct udevice * dev,int flags,uchar ** packetp)181 static int ravb_recv(struct udevice *dev, int flags, uchar **packetp)
182 {
183 struct ravb_priv *eth = dev_get_priv(dev);
184 struct ravb_rxdesc *desc = ð->rx_desc[eth->rx_desc_idx];
185 int len;
186 u8 *packet;
187
188 /* Check if the rx descriptor is ready */
189 ravb_invalidate_dcache((uintptr_t)desc, sizeof(*desc));
190 if ((desc->data.ctrl & RAVB_DESC_DT_MASK) == RAVB_DESC_DT_FEMPTY)
191 return -EAGAIN;
192
193 /* Check for errors */
194 if (desc->data.ctrl & RAVB_RX_DESC_MSC_RX_ERR_MASK) {
195 desc->data.ctrl &= ~RAVB_RX_DESC_MSC_MASK;
196 return -EAGAIN;
197 }
198
199 len = desc->data.ctrl & RAVB_DESC_DS_MASK;
200 packet = (u8 *)(uintptr_t)desc->data.dptr;
201 ravb_invalidate_dcache((uintptr_t)packet, len);
202
203 *packetp = packet;
204 return len;
205 }
206
ravb_free_pkt(struct udevice * dev,uchar * packet,int length)207 static int ravb_free_pkt(struct udevice *dev, uchar *packet, int length)
208 {
209 struct ravb_priv *eth = dev_get_priv(dev);
210 struct ravb_rxdesc *desc = ð->rx_desc[eth->rx_desc_idx];
211
212 /* Make current descriptor available again */
213 desc->data.ctrl = RAVB_DESC_DT_FEMPTY | RAVB_DESC_DS(PKTSIZE_ALIGN);
214 ravb_flush_dcache((uintptr_t)desc, sizeof(*desc));
215
216 /* Point to the next descriptor */
217 eth->rx_desc_idx = (eth->rx_desc_idx + 1) % RAVB_NUM_RX_DESC;
218 desc = ð->rx_desc[eth->rx_desc_idx];
219 ravb_invalidate_dcache((uintptr_t)desc, sizeof(*desc));
220
221 return 0;
222 }
223
ravb_reset(struct udevice * dev)224 static int ravb_reset(struct udevice *dev)
225 {
226 struct ravb_priv *eth = dev_get_priv(dev);
227
228 /* Set config mode */
229 writel(CCC_OPC_CONFIG, eth->iobase + RAVB_REG_CCC);
230
231 /* Check the operating mode is changed to the config mode. */
232 return wait_for_bit_le32(eth->iobase + RAVB_REG_CSR,
233 CSR_OPS_CONFIG, true, 100, true);
234 }
235
ravb_base_desc_init(struct ravb_priv * eth)236 static void ravb_base_desc_init(struct ravb_priv *eth)
237 {
238 const u32 desc_size = RAVB_NUM_BASE_DESC * sizeof(struct ravb_desc);
239 int i;
240
241 /* Initialize all descriptors */
242 memset(eth->base_desc, 0x0, desc_size);
243
244 for (i = 0; i < RAVB_NUM_BASE_DESC; i++)
245 eth->base_desc[i].ctrl = RAVB_DESC_DT_EOS;
246
247 ravb_flush_dcache((uintptr_t)eth->base_desc, desc_size);
248
249 /* Register the descriptor base address table */
250 writel((uintptr_t)eth->base_desc, eth->iobase + RAVB_REG_DBAT);
251 }
252
ravb_tx_desc_init(struct ravb_priv * eth)253 static void ravb_tx_desc_init(struct ravb_priv *eth)
254 {
255 const u32 desc_size = RAVB_NUM_TX_DESC * sizeof(struct ravb_desc);
256 int i;
257
258 /* Initialize all descriptors */
259 memset(eth->tx_desc, 0x0, desc_size);
260 eth->tx_desc_idx = 0;
261
262 for (i = 0; i < RAVB_NUM_TX_DESC; i++)
263 eth->tx_desc[i].ctrl = RAVB_DESC_DT_EEMPTY;
264
265 /* Mark the end of the descriptors */
266 eth->tx_desc[RAVB_NUM_TX_DESC - 1].ctrl = RAVB_DESC_DT_LINKFIX;
267 eth->tx_desc[RAVB_NUM_TX_DESC - 1].dptr = (uintptr_t)eth->tx_desc;
268 ravb_flush_dcache((uintptr_t)eth->tx_desc, desc_size);
269
270 /* Point the controller to the TX descriptor list. */
271 eth->base_desc[RAVB_TX_QUEUE_OFFSET].ctrl = RAVB_DESC_DT_LINKFIX;
272 eth->base_desc[RAVB_TX_QUEUE_OFFSET].dptr = (uintptr_t)eth->tx_desc;
273 ravb_flush_dcache((uintptr_t)ð->base_desc[RAVB_TX_QUEUE_OFFSET],
274 sizeof(struct ravb_desc));
275 }
276
ravb_rx_desc_init(struct ravb_priv * eth)277 static void ravb_rx_desc_init(struct ravb_priv *eth)
278 {
279 const u32 desc_size = RAVB_NUM_RX_DESC * sizeof(struct ravb_rxdesc);
280 int i;
281
282 /* Initialize all descriptors */
283 memset(eth->rx_desc, 0x0, desc_size);
284 eth->rx_desc_idx = 0;
285
286 for (i = 0; i < RAVB_NUM_RX_DESC; i++) {
287 eth->rx_desc[i].data.ctrl = RAVB_DESC_DT_EEMPTY |
288 RAVB_DESC_DS(PKTSIZE_ALIGN);
289 eth->rx_desc[i].data.dptr = (uintptr_t)eth->rx_desc[i].packet;
290
291 eth->rx_desc[i].link.ctrl = RAVB_DESC_DT_LINKFIX;
292 eth->rx_desc[i].link.dptr = (uintptr_t)ð->rx_desc[i + 1];
293 }
294
295 /* Mark the end of the descriptors */
296 eth->rx_desc[RAVB_NUM_RX_DESC - 1].link.ctrl = RAVB_DESC_DT_LINKFIX;
297 eth->rx_desc[RAVB_NUM_RX_DESC - 1].link.dptr = (uintptr_t)eth->rx_desc;
298 ravb_flush_dcache((uintptr_t)eth->rx_desc, desc_size);
299
300 /* Point the controller to the rx descriptor list */
301 eth->base_desc[RAVB_RX_QUEUE_OFFSET].ctrl = RAVB_DESC_DT_LINKFIX;
302 eth->base_desc[RAVB_RX_QUEUE_OFFSET].dptr = (uintptr_t)eth->rx_desc;
303 ravb_flush_dcache((uintptr_t)ð->base_desc[RAVB_RX_QUEUE_OFFSET],
304 sizeof(struct ravb_desc));
305 }
306
ravb_phy_config(struct udevice * dev)307 static int ravb_phy_config(struct udevice *dev)
308 {
309 struct ravb_priv *eth = dev_get_priv(dev);
310 struct eth_pdata *pdata = dev_get_plat(dev);
311 struct phy_device *phydev;
312 int mask = 0xffffffff, reg;
313
314 if (dm_gpio_is_valid(ð->reset_gpio)) {
315 dm_gpio_set_value(ð->reset_gpio, 1);
316 mdelay(20);
317 dm_gpio_set_value(ð->reset_gpio, 0);
318 mdelay(1);
319 }
320
321 phydev = phy_find_by_mask(eth->bus, mask, pdata->phy_interface);
322 if (!phydev)
323 return -ENODEV;
324
325 phy_connect_dev(phydev, dev);
326
327 eth->phydev = phydev;
328
329 phydev->supported &= SUPPORTED_100baseT_Full |
330 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg |
331 SUPPORTED_TP | SUPPORTED_MII | SUPPORTED_Pause |
332 SUPPORTED_Asym_Pause;
333
334 if (pdata->max_speed != 1000) {
335 phydev->supported &= ~SUPPORTED_1000baseT_Full;
336 reg = phy_read(phydev, -1, MII_CTRL1000);
337 reg &= ~(BIT(9) | BIT(8));
338 phy_write(phydev, -1, MII_CTRL1000, reg);
339 }
340
341 phy_config(phydev);
342
343 return 0;
344 }
345
346 /* Set Mac address */
ravb_write_hwaddr(struct udevice * dev)347 static int ravb_write_hwaddr(struct udevice *dev)
348 {
349 struct ravb_priv *eth = dev_get_priv(dev);
350 struct eth_pdata *pdata = dev_get_plat(dev);
351 unsigned char *mac = pdata->enetaddr;
352
353 writel((mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3],
354 eth->iobase + RAVB_REG_MAHR);
355
356 writel((mac[4] << 8) | mac[5], eth->iobase + RAVB_REG_MALR);
357
358 return 0;
359 }
360
361 /* E-MAC init function */
ravb_mac_init(struct ravb_priv * eth)362 static int ravb_mac_init(struct ravb_priv *eth)
363 {
364 /* Disable MAC Interrupt */
365 writel(0, eth->iobase + RAVB_REG_ECSIPR);
366
367 /* Recv frame limit set register */
368 writel(RFLR_RFL_MIN, eth->iobase + RAVB_REG_RFLR);
369
370 return 0;
371 }
372
373 /* AVB-DMAC init function */
ravb_dmac_init(struct udevice * dev)374 static int ravb_dmac_init(struct udevice *dev)
375 {
376 struct ravb_priv *eth = dev_get_priv(dev);
377 struct eth_pdata *pdata = dev_get_plat(dev);
378 int ret = 0;
379
380 /* Set CONFIG mode */
381 ret = ravb_reset(dev);
382 if (ret)
383 return ret;
384
385 /* Disable all interrupts */
386 writel(0, eth->iobase + RAVB_REG_RIC0);
387 writel(0, eth->iobase + RAVB_REG_RIC1);
388 writel(0, eth->iobase + RAVB_REG_RIC2);
389 writel(0, eth->iobase + RAVB_REG_TIC);
390
391 /* Set little endian */
392 clrbits_le32(eth->iobase + RAVB_REG_CCC, CCC_BOC);
393
394 /* AVB rx set */
395 writel(0x18000001, eth->iobase + RAVB_REG_RCR);
396
397 /* FIFO size set */
398 writel(0x00222210, eth->iobase + RAVB_REG_TGC);
399
400 /* Delay CLK: 2ns (not applicable on R-Car E3/D3) */
401 if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77990) ||
402 (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77995))
403 return 0;
404
405 if ((pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
406 (pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID))
407 writel(APSR_TDM, eth->iobase + RAVB_REG_APSR);
408
409 return 0;
410 }
411
ravb_config(struct udevice * dev)412 static int ravb_config(struct udevice *dev)
413 {
414 struct ravb_priv *eth = dev_get_priv(dev);
415 struct phy_device *phy = eth->phydev;
416 u32 mask = ECMR_CHG_DM | ECMR_RE | ECMR_TE;
417 int ret;
418
419 /* Configure AVB-DMAC register */
420 ravb_dmac_init(dev);
421
422 /* Configure E-MAC registers */
423 ravb_mac_init(eth);
424 ravb_write_hwaddr(dev);
425
426 ret = phy_startup(phy);
427 if (ret)
428 return ret;
429
430 /* Set the transfer speed */
431 if (phy->speed == 100)
432 writel(0, eth->iobase + RAVB_REG_GECMR);
433 else if (phy->speed == 1000)
434 writel(1, eth->iobase + RAVB_REG_GECMR);
435
436 /* Check if full duplex mode is supported by the phy */
437 if (phy->duplex)
438 mask |= ECMR_DM;
439
440 writel(mask, eth->iobase + RAVB_REG_ECMR);
441
442 return 0;
443 }
444
ravb_start(struct udevice * dev)445 static int ravb_start(struct udevice *dev)
446 {
447 struct ravb_priv *eth = dev_get_priv(dev);
448 int ret;
449
450 ret = ravb_reset(dev);
451 if (ret)
452 return ret;
453
454 ravb_base_desc_init(eth);
455 ravb_tx_desc_init(eth);
456 ravb_rx_desc_init(eth);
457
458 ret = ravb_config(dev);
459 if (ret)
460 return ret;
461
462 /* Setting the control will start the AVB-DMAC process. */
463 writel(CCC_OPC_OPERATION, eth->iobase + RAVB_REG_CCC);
464
465 return 0;
466 }
467
ravb_stop(struct udevice * dev)468 static void ravb_stop(struct udevice *dev)
469 {
470 struct ravb_priv *eth = dev_get_priv(dev);
471
472 phy_shutdown(eth->phydev);
473 ravb_reset(dev);
474 }
475
ravb_probe(struct udevice * dev)476 static int ravb_probe(struct udevice *dev)
477 {
478 struct eth_pdata *pdata = dev_get_plat(dev);
479 struct ravb_priv *eth = dev_get_priv(dev);
480 struct ofnode_phandle_args phandle_args;
481 struct mii_dev *mdiodev;
482 void __iomem *iobase;
483 int ret;
484
485 iobase = map_physmem(pdata->iobase, 0x1000, MAP_NOCACHE);
486 eth->iobase = iobase;
487
488 ret = clk_get_by_index(dev, 0, ð->clk);
489 if (ret < 0)
490 goto err_mdio_alloc;
491
492 ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, &phandle_args);
493 if (!ret) {
494 gpio_request_by_name_nodev(phandle_args.node, "reset-gpios", 0,
495 ð->reset_gpio, GPIOD_IS_OUT);
496 }
497
498 if (!dm_gpio_is_valid(ð->reset_gpio)) {
499 gpio_request_by_name(dev, "reset-gpios", 0, ð->reset_gpio,
500 GPIOD_IS_OUT);
501 }
502
503 mdiodev = mdio_alloc();
504 if (!mdiodev) {
505 ret = -ENOMEM;
506 goto err_mdio_alloc;
507 }
508
509 mdiodev->read = bb_miiphy_read;
510 mdiodev->write = bb_miiphy_write;
511 bb_miiphy_buses[0].priv = eth;
512 snprintf(mdiodev->name, sizeof(mdiodev->name), dev->name);
513
514 ret = mdio_register(mdiodev);
515 if (ret < 0)
516 goto err_mdio_register;
517
518 eth->bus = miiphy_get_dev_by_name(dev->name);
519
520 /* Bring up PHY */
521 ret = clk_enable(ð->clk);
522 if (ret)
523 goto err_mdio_register;
524
525 ret = ravb_reset(dev);
526 if (ret)
527 goto err_mdio_reset;
528
529 ret = ravb_phy_config(dev);
530 if (ret)
531 goto err_mdio_reset;
532
533 return 0;
534
535 err_mdio_reset:
536 clk_disable(ð->clk);
537 err_mdio_register:
538 mdio_free(mdiodev);
539 err_mdio_alloc:
540 unmap_physmem(eth->iobase, MAP_NOCACHE);
541 return ret;
542 }
543
ravb_remove(struct udevice * dev)544 static int ravb_remove(struct udevice *dev)
545 {
546 struct ravb_priv *eth = dev_get_priv(dev);
547
548 clk_disable(ð->clk);
549
550 free(eth->phydev);
551 mdio_unregister(eth->bus);
552 mdio_free(eth->bus);
553 if (dm_gpio_is_valid(ð->reset_gpio))
554 dm_gpio_free(dev, ð->reset_gpio);
555 unmap_physmem(eth->iobase, MAP_NOCACHE);
556
557 return 0;
558 }
559
ravb_bb_init(struct bb_miiphy_bus * bus)560 int ravb_bb_init(struct bb_miiphy_bus *bus)
561 {
562 return 0;
563 }
564
ravb_bb_mdio_active(struct bb_miiphy_bus * bus)565 int ravb_bb_mdio_active(struct bb_miiphy_bus *bus)
566 {
567 struct ravb_priv *eth = bus->priv;
568
569 setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MMD);
570
571 return 0;
572 }
573
ravb_bb_mdio_tristate(struct bb_miiphy_bus * bus)574 int ravb_bb_mdio_tristate(struct bb_miiphy_bus *bus)
575 {
576 struct ravb_priv *eth = bus->priv;
577
578 clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MMD);
579
580 return 0;
581 }
582
ravb_bb_set_mdio(struct bb_miiphy_bus * bus,int v)583 int ravb_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
584 {
585 struct ravb_priv *eth = bus->priv;
586
587 if (v)
588 setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDO);
589 else
590 clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDO);
591
592 return 0;
593 }
594
ravb_bb_get_mdio(struct bb_miiphy_bus * bus,int * v)595 int ravb_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
596 {
597 struct ravb_priv *eth = bus->priv;
598
599 *v = (readl(eth->iobase + RAVB_REG_PIR) & PIR_MDI) >> 3;
600
601 return 0;
602 }
603
ravb_bb_set_mdc(struct bb_miiphy_bus * bus,int v)604 int ravb_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
605 {
606 struct ravb_priv *eth = bus->priv;
607
608 if (v)
609 setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDC);
610 else
611 clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDC);
612
613 return 0;
614 }
615
ravb_bb_delay(struct bb_miiphy_bus * bus)616 int ravb_bb_delay(struct bb_miiphy_bus *bus)
617 {
618 udelay(10);
619
620 return 0;
621 }
622
623 struct bb_miiphy_bus bb_miiphy_buses[] = {
624 {
625 .name = "ravb",
626 .init = ravb_bb_init,
627 .mdio_active = ravb_bb_mdio_active,
628 .mdio_tristate = ravb_bb_mdio_tristate,
629 .set_mdio = ravb_bb_set_mdio,
630 .get_mdio = ravb_bb_get_mdio,
631 .set_mdc = ravb_bb_set_mdc,
632 .delay = ravb_bb_delay,
633 },
634 };
635 int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);
636
637 static const struct eth_ops ravb_ops = {
638 .start = ravb_start,
639 .send = ravb_send,
640 .recv = ravb_recv,
641 .free_pkt = ravb_free_pkt,
642 .stop = ravb_stop,
643 .write_hwaddr = ravb_write_hwaddr,
644 };
645
ravb_of_to_plat(struct udevice * dev)646 int ravb_of_to_plat(struct udevice *dev)
647 {
648 struct eth_pdata *pdata = dev_get_plat(dev);
649 const char *phy_mode;
650 const fdt32_t *cell;
651 int ret = 0;
652
653 pdata->iobase = dev_read_addr(dev);
654 pdata->phy_interface = -1;
655 phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
656 NULL);
657 if (phy_mode)
658 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
659 if (pdata->phy_interface == -1) {
660 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
661 return -EINVAL;
662 }
663
664 pdata->max_speed = 1000;
665 cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL);
666 if (cell)
667 pdata->max_speed = fdt32_to_cpu(*cell);
668
669 sprintf(bb_miiphy_buses[0].name, dev->name);
670
671 return ret;
672 }
673
674 static const struct udevice_id ravb_ids[] = {
675 { .compatible = "renesas,etheravb-r8a7795" },
676 { .compatible = "renesas,etheravb-r8a7796" },
677 { .compatible = "renesas,etheravb-r8a77965" },
678 { .compatible = "renesas,etheravb-r8a77970" },
679 { .compatible = "renesas,etheravb-r8a77990" },
680 { .compatible = "renesas,etheravb-r8a77995" },
681 { .compatible = "renesas,etheravb-rcar-gen3" },
682 { }
683 };
684
685 U_BOOT_DRIVER(eth_ravb) = {
686 .name = "ravb",
687 .id = UCLASS_ETH,
688 .of_match = ravb_ids,
689 .of_to_plat = ravb_of_to_plat,
690 .probe = ravb_probe,
691 .remove = ravb_remove,
692 .ops = &ravb_ops,
693 .priv_auto = sizeof(struct ravb_priv),
694 .plat_auto = sizeof(struct eth_pdata),
695 .flags = DM_FLAG_ALLOC_PRIV_DMA,
696 };
697