1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2016
4 * Author: Amit Singh Tomar, amittomer25@gmail.com
5 *
6 * Ethernet driver for H3/A64/A83T based SoC's
7 *
8 * It is derived from the work done by
9 * LABBE Corentin & Chen-Yu Tsai for Linux, THANKS!
10 *
11 */
12
13 #include <cpu_func.h>
14 #include <log.h>
15 #include <asm/cache.h>
16 #include <asm/global_data.h>
17 #include <asm/io.h>
18 #include <asm/arch/clock.h>
19 #include <asm/arch/gpio.h>
20 #include <common.h>
21 #include <clk.h>
22 #include <dm.h>
23 #include <fdt_support.h>
24 #include <dm/device_compat.h>
25 #include <linux/bitops.h>
26 #include <linux/delay.h>
27 #include <linux/err.h>
28 #include <malloc.h>
29 #include <miiphy.h>
30 #include <net.h>
31 #include <reset.h>
32 #include <dt-bindings/pinctrl/sun4i-a10.h>
33 #include <wait_bit.h>
34 #if CONFIG_IS_ENABLED(DM_GPIO)
35 #include <asm-generic/gpio.h>
36 #endif
37
38 #define MDIO_CMD_MII_BUSY BIT(0)
39 #define MDIO_CMD_MII_WRITE BIT(1)
40
41 #define MDIO_CMD_MII_PHY_REG_ADDR_MASK 0x000001f0
42 #define MDIO_CMD_MII_PHY_REG_ADDR_SHIFT 4
43 #define MDIO_CMD_MII_PHY_ADDR_MASK 0x0001f000
44 #define MDIO_CMD_MII_PHY_ADDR_SHIFT 12
45 #define MDIO_CMD_MII_CLK_CSR_DIV_16 0x0
46 #define MDIO_CMD_MII_CLK_CSR_DIV_32 0x1
47 #define MDIO_CMD_MII_CLK_CSR_DIV_64 0x2
48 #define MDIO_CMD_MII_CLK_CSR_DIV_128 0x3
49 #define MDIO_CMD_MII_CLK_CSR_SHIFT 20
50
51 #define CONFIG_TX_DESCR_NUM 32
52 #define CONFIG_RX_DESCR_NUM 32
53 #define CONFIG_ETH_BUFSIZE 2048 /* Note must be dma aligned */
54
55 /*
56 * The datasheet says that each descriptor can transfers up to 4096 bytes
57 * But later, the register documentation reduces that value to 2048,
58 * using 2048 cause strange behaviours and even BSP driver use 2047
59 */
60 #define CONFIG_ETH_RXSIZE 2044 /* Note must fit in ETH_BUFSIZE */
61
62 #define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM)
63 #define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM)
64
65 #define H3_EPHY_DEFAULT_VALUE 0x58000
66 #define H3_EPHY_DEFAULT_MASK GENMASK(31, 15)
67 #define H3_EPHY_ADDR_SHIFT 20
68 #define REG_PHY_ADDR_MASK GENMASK(4, 0)
69 #define H3_EPHY_LED_POL BIT(17) /* 1: active low, 0: active high */
70 #define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */
71 #define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */
72
73 #define SC_RMII_EN BIT(13)
74 #define SC_EPIT BIT(2) /* 1: RGMII, 0: MII */
75 #define SC_ETCS_MASK GENMASK(1, 0)
76 #define SC_ETCS_EXT_GMII 0x1
77 #define SC_ETCS_INT_GMII 0x2
78 #define SC_ETXDC_MASK GENMASK(12, 10)
79 #define SC_ETXDC_OFFSET 10
80 #define SC_ERXDC_MASK GENMASK(9, 5)
81 #define SC_ERXDC_OFFSET 5
82
83 #define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ)
84
85 #define AHB_GATE_OFFSET_EPHY 0
86
87 /* IO mux settings */
88 #define SUN8I_IOMUX_H3 2
89 #define SUN8I_IOMUX_R40 5
90 #define SUN8I_IOMUX_H6 5
91 #define SUN8I_IOMUX_H616 2
92 #define SUN8I_IOMUX 4
93
94 /* H3/A64 EMAC Register's offset */
95 #define EMAC_CTL0 0x00
96 #define EMAC_CTL0_FULL_DUPLEX BIT(0)
97 #define EMAC_CTL0_SPEED_MASK GENMASK(3, 2)
98 #define EMAC_CTL0_SPEED_10 (0x2 << 2)
99 #define EMAC_CTL0_SPEED_100 (0x3 << 2)
100 #define EMAC_CTL0_SPEED_1000 (0x0 << 2)
101 #define EMAC_CTL1 0x04
102 #define EMAC_CTL1_SOFT_RST BIT(0)
103 #define EMAC_CTL1_BURST_LEN_SHIFT 24
104 #define EMAC_INT_STA 0x08
105 #define EMAC_INT_EN 0x0c
106 #define EMAC_TX_CTL0 0x10
107 #define EMAC_TX_CTL0_TX_EN BIT(31)
108 #define EMAC_TX_CTL1 0x14
109 #define EMAC_TX_CTL1_TX_MD BIT(1)
110 #define EMAC_TX_CTL1_TX_DMA_EN BIT(30)
111 #define EMAC_TX_CTL1_TX_DMA_START BIT(31)
112 #define EMAC_TX_FLOW_CTL 0x1c
113 #define EMAC_TX_DMA_DESC 0x20
114 #define EMAC_RX_CTL0 0x24
115 #define EMAC_RX_CTL0_RX_EN BIT(31)
116 #define EMAC_RX_CTL1 0x28
117 #define EMAC_RX_CTL1_RX_MD BIT(1)
118 #define EMAC_RX_CTL1_RX_RUNT_FRM BIT(2)
119 #define EMAC_RX_CTL1_RX_ERR_FRM BIT(3)
120 #define EMAC_RX_CTL1_RX_DMA_EN BIT(30)
121 #define EMAC_RX_CTL1_RX_DMA_START BIT(31)
122 #define EMAC_RX_DMA_DESC 0x34
123 #define EMAC_MII_CMD 0x48
124 #define EMAC_MII_DATA 0x4c
125 #define EMAC_ADDR0_HIGH 0x50
126 #define EMAC_ADDR0_LOW 0x54
127 #define EMAC_TX_DMA_STA 0xb0
128 #define EMAC_TX_CUR_DESC 0xb4
129 #define EMAC_TX_CUR_BUF 0xb8
130 #define EMAC_RX_DMA_STA 0xc0
131 #define EMAC_RX_CUR_DESC 0xc4
132
133 #define EMAC_DESC_OWN_DMA BIT(31)
134 #define EMAC_DESC_LAST_DESC BIT(30)
135 #define EMAC_DESC_FIRST_DESC BIT(29)
136 #define EMAC_DESC_CHAIN_SECOND BIT(24)
137
138 #define EMAC_DESC_RX_ERROR_MASK 0x400068db
139
140 DECLARE_GLOBAL_DATA_PTR;
141
142 enum emac_variant {
143 A83T_EMAC = 1,
144 H3_EMAC,
145 A64_EMAC,
146 R40_GMAC,
147 H6_EMAC,
148 };
149
150 struct emac_dma_desc {
151 u32 status;
152 u32 ctl_size;
153 u32 buf_addr;
154 u32 next;
155 } __aligned(ARCH_DMA_MINALIGN);
156
157 struct emac_eth_dev {
158 struct emac_dma_desc rx_chain[CONFIG_TX_DESCR_NUM];
159 struct emac_dma_desc tx_chain[CONFIG_RX_DESCR_NUM];
160 char rxbuffer[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
161 char txbuffer[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
162
163 u32 interface;
164 u32 phyaddr;
165 u32 link;
166 u32 speed;
167 u32 duplex;
168 u32 phy_configured;
169 u32 tx_currdescnum;
170 u32 rx_currdescnum;
171 u32 addr;
172 u32 tx_slot;
173 bool use_internal_phy;
174
175 enum emac_variant variant;
176 void *mac_reg;
177 phys_addr_t sysctl_reg;
178 struct phy_device *phydev;
179 struct mii_dev *bus;
180 struct clk tx_clk;
181 struct clk ephy_clk;
182 struct reset_ctl tx_rst;
183 struct reset_ctl ephy_rst;
184 #if CONFIG_IS_ENABLED(DM_GPIO)
185 struct gpio_desc reset_gpio;
186 #endif
187 };
188
189
190 struct sun8i_eth_pdata {
191 struct eth_pdata eth_pdata;
192 u32 reset_delays[3];
193 int tx_delay_ps;
194 int rx_delay_ps;
195 };
196
197
sun8i_mdio_read(struct mii_dev * bus,int addr,int devad,int reg)198 static int sun8i_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
199 {
200 struct udevice *dev = bus->priv;
201 struct emac_eth_dev *priv = dev_get_priv(dev);
202 u32 mii_cmd;
203 int ret;
204
205 mii_cmd = (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) &
206 MDIO_CMD_MII_PHY_REG_ADDR_MASK;
207 mii_cmd |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) &
208 MDIO_CMD_MII_PHY_ADDR_MASK;
209
210 /*
211 * The EMAC clock is either 200 or 300 MHz, so we need a divider
212 * of 128 to get the MDIO frequency below the required 2.5 MHz.
213 */
214 if (!priv->use_internal_phy)
215 mii_cmd |= MDIO_CMD_MII_CLK_CSR_DIV_128 <<
216 MDIO_CMD_MII_CLK_CSR_SHIFT;
217
218 mii_cmd |= MDIO_CMD_MII_BUSY;
219
220 writel(mii_cmd, priv->mac_reg + EMAC_MII_CMD);
221
222 ret = wait_for_bit_le32(priv->mac_reg + EMAC_MII_CMD,
223 MDIO_CMD_MII_BUSY, false,
224 CONFIG_MDIO_TIMEOUT, true);
225 if (ret < 0)
226 return ret;
227
228 return readl(priv->mac_reg + EMAC_MII_DATA);
229 }
230
sun8i_mdio_write(struct mii_dev * bus,int addr,int devad,int reg,u16 val)231 static int sun8i_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
232 u16 val)
233 {
234 struct udevice *dev = bus->priv;
235 struct emac_eth_dev *priv = dev_get_priv(dev);
236 u32 mii_cmd;
237
238 mii_cmd = (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) &
239 MDIO_CMD_MII_PHY_REG_ADDR_MASK;
240 mii_cmd |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) &
241 MDIO_CMD_MII_PHY_ADDR_MASK;
242
243 /*
244 * The EMAC clock is either 200 or 300 MHz, so we need a divider
245 * of 128 to get the MDIO frequency below the required 2.5 MHz.
246 */
247 if (!priv->use_internal_phy)
248 mii_cmd |= MDIO_CMD_MII_CLK_CSR_DIV_128 <<
249 MDIO_CMD_MII_CLK_CSR_SHIFT;
250
251 mii_cmd |= MDIO_CMD_MII_WRITE;
252 mii_cmd |= MDIO_CMD_MII_BUSY;
253
254 writel(val, priv->mac_reg + EMAC_MII_DATA);
255 writel(mii_cmd, priv->mac_reg + EMAC_MII_CMD);
256
257 return wait_for_bit_le32(priv->mac_reg + EMAC_MII_CMD,
258 MDIO_CMD_MII_BUSY, false,
259 CONFIG_MDIO_TIMEOUT, true);
260 }
261
sun8i_eth_write_hwaddr(struct udevice * dev)262 static int sun8i_eth_write_hwaddr(struct udevice *dev)
263 {
264 struct emac_eth_dev *priv = dev_get_priv(dev);
265 struct eth_pdata *pdata = dev_get_plat(dev);
266 uchar *mac_id = pdata->enetaddr;
267 u32 macid_lo, macid_hi;
268
269 macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
270 (mac_id[3] << 24);
271 macid_hi = mac_id[4] + (mac_id[5] << 8);
272
273 writel(macid_hi, priv->mac_reg + EMAC_ADDR0_HIGH);
274 writel(macid_lo, priv->mac_reg + EMAC_ADDR0_LOW);
275
276 return 0;
277 }
278
sun8i_adjust_link(struct emac_eth_dev * priv,struct phy_device * phydev)279 static void sun8i_adjust_link(struct emac_eth_dev *priv,
280 struct phy_device *phydev)
281 {
282 u32 v;
283
284 v = readl(priv->mac_reg + EMAC_CTL0);
285
286 if (phydev->duplex)
287 v |= EMAC_CTL0_FULL_DUPLEX;
288 else
289 v &= ~EMAC_CTL0_FULL_DUPLEX;
290
291 v &= ~EMAC_CTL0_SPEED_MASK;
292
293 switch (phydev->speed) {
294 case 1000:
295 v |= EMAC_CTL0_SPEED_1000;
296 break;
297 case 100:
298 v |= EMAC_CTL0_SPEED_100;
299 break;
300 case 10:
301 v |= EMAC_CTL0_SPEED_10;
302 break;
303 }
304 writel(v, priv->mac_reg + EMAC_CTL0);
305 }
306
sun8i_emac_set_syscon_ephy(struct emac_eth_dev * priv,u32 reg)307 static u32 sun8i_emac_set_syscon_ephy(struct emac_eth_dev *priv, u32 reg)
308 {
309 if (priv->use_internal_phy) {
310 /* H3 based SoC's that has an Internal 100MBit PHY
311 * needs to be configured and powered up before use
312 */
313 reg &= ~H3_EPHY_DEFAULT_MASK;
314 reg |= H3_EPHY_DEFAULT_VALUE;
315 reg |= priv->phyaddr << H3_EPHY_ADDR_SHIFT;
316 reg &= ~H3_EPHY_SHUTDOWN;
317 return reg | H3_EPHY_SELECT;
318 }
319
320 /* This is to select External Gigabit PHY on those boards with
321 * an internal PHY. Does not hurt on other SoCs. Linux does
322 * it as well.
323 */
324 return reg & ~H3_EPHY_SELECT;
325 }
326
sun8i_emac_set_syscon(struct sun8i_eth_pdata * pdata,struct emac_eth_dev * priv)327 static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata,
328 struct emac_eth_dev *priv)
329 {
330 u32 reg;
331
332 if (priv->variant == R40_GMAC) {
333 /* Select RGMII for R40 */
334 reg = readl(priv->sysctl_reg + 0x164);
335 reg |= SC_ETCS_INT_GMII |
336 SC_EPIT |
337 (CONFIG_GMAC_TX_DELAY << SC_ETXDC_OFFSET);
338
339 writel(reg, priv->sysctl_reg + 0x164);
340 return 0;
341 }
342
343 reg = readl(priv->sysctl_reg + 0x30);
344
345 reg = sun8i_emac_set_syscon_ephy(priv, reg);
346
347 reg &= ~(SC_ETCS_MASK | SC_EPIT);
348 if (priv->variant == H3_EMAC ||
349 priv->variant == A64_EMAC ||
350 priv->variant == H6_EMAC)
351 reg &= ~SC_RMII_EN;
352
353 switch (priv->interface) {
354 case PHY_INTERFACE_MODE_MII:
355 /* default */
356 break;
357 case PHY_INTERFACE_MODE_RGMII:
358 case PHY_INTERFACE_MODE_RGMII_ID:
359 case PHY_INTERFACE_MODE_RGMII_RXID:
360 case PHY_INTERFACE_MODE_RGMII_TXID:
361 reg |= SC_EPIT | SC_ETCS_INT_GMII;
362 break;
363 case PHY_INTERFACE_MODE_RMII:
364 if (priv->variant == H3_EMAC ||
365 priv->variant == A64_EMAC ||
366 priv->variant == H6_EMAC) {
367 reg |= SC_RMII_EN | SC_ETCS_EXT_GMII;
368 break;
369 }
370 /* RMII not supported on A83T */
371 default:
372 debug("%s: Invalid PHY interface\n", __func__);
373 return -EINVAL;
374 }
375
376 if (pdata->tx_delay_ps)
377 reg |= ((pdata->tx_delay_ps / 100) << SC_ETXDC_OFFSET)
378 & SC_ETXDC_MASK;
379
380 if (pdata->rx_delay_ps)
381 reg |= ((pdata->rx_delay_ps / 100) << SC_ERXDC_OFFSET)
382 & SC_ERXDC_MASK;
383
384 writel(reg, priv->sysctl_reg + 0x30);
385
386 return 0;
387 }
388
sun8i_phy_init(struct emac_eth_dev * priv,void * dev)389 static int sun8i_phy_init(struct emac_eth_dev *priv, void *dev)
390 {
391 struct phy_device *phydev;
392
393 phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
394 if (!phydev)
395 return -ENODEV;
396
397 phy_connect_dev(phydev, dev);
398
399 priv->phydev = phydev;
400 phy_config(priv->phydev);
401
402 return 0;
403 }
404
405 #define cache_clean_descriptor(desc) \
406 flush_dcache_range((uintptr_t)(desc), \
407 (uintptr_t)(desc) + sizeof(struct emac_dma_desc))
408
409 #define cache_inv_descriptor(desc) \
410 invalidate_dcache_range((uintptr_t)(desc), \
411 (uintptr_t)(desc) + sizeof(struct emac_dma_desc))
412
rx_descs_init(struct emac_eth_dev * priv)413 static void rx_descs_init(struct emac_eth_dev *priv)
414 {
415 struct emac_dma_desc *desc_table_p = &priv->rx_chain[0];
416 char *rxbuffs = &priv->rxbuffer[0];
417 struct emac_dma_desc *desc_p;
418 int i;
419
420 /*
421 * Make sure we don't have dirty cache lines around, which could
422 * be cleaned to DRAM *after* the MAC has already written data to it.
423 */
424 invalidate_dcache_range((uintptr_t)desc_table_p,
425 (uintptr_t)desc_table_p + sizeof(priv->rx_chain));
426 invalidate_dcache_range((uintptr_t)rxbuffs,
427 (uintptr_t)rxbuffs + sizeof(priv->rxbuffer));
428
429 for (i = 0; i < CONFIG_RX_DESCR_NUM; i++) {
430 desc_p = &desc_table_p[i];
431 desc_p->buf_addr = (uintptr_t)&rxbuffs[i * CONFIG_ETH_BUFSIZE];
432 desc_p->next = (uintptr_t)&desc_table_p[i + 1];
433 desc_p->ctl_size = CONFIG_ETH_RXSIZE;
434 desc_p->status = EMAC_DESC_OWN_DMA;
435 }
436
437 /* Correcting the last pointer of the chain */
438 desc_p->next = (uintptr_t)&desc_table_p[0];
439
440 flush_dcache_range((uintptr_t)priv->rx_chain,
441 (uintptr_t)priv->rx_chain +
442 sizeof(priv->rx_chain));
443
444 writel((uintptr_t)&desc_table_p[0], (priv->mac_reg + EMAC_RX_DMA_DESC));
445 priv->rx_currdescnum = 0;
446 }
447
tx_descs_init(struct emac_eth_dev * priv)448 static void tx_descs_init(struct emac_eth_dev *priv)
449 {
450 struct emac_dma_desc *desc_table_p = &priv->tx_chain[0];
451 char *txbuffs = &priv->txbuffer[0];
452 struct emac_dma_desc *desc_p;
453 int i;
454
455 for (i = 0; i < CONFIG_TX_DESCR_NUM; i++) {
456 desc_p = &desc_table_p[i];
457 desc_p->buf_addr = (uintptr_t)&txbuffs[i * CONFIG_ETH_BUFSIZE];
458 desc_p->next = (uintptr_t)&desc_table_p[i + 1];
459 desc_p->ctl_size = 0;
460 desc_p->status = 0;
461 }
462
463 /* Correcting the last pointer of the chain */
464 desc_p->next = (uintptr_t)&desc_table_p[0];
465
466 /* Flush the first TX buffer descriptor we will tell the MAC about. */
467 cache_clean_descriptor(desc_table_p);
468
469 writel((uintptr_t)&desc_table_p[0], priv->mac_reg + EMAC_TX_DMA_DESC);
470 priv->tx_currdescnum = 0;
471 }
472
sun8i_emac_eth_start(struct udevice * dev)473 static int sun8i_emac_eth_start(struct udevice *dev)
474 {
475 struct emac_eth_dev *priv = dev_get_priv(dev);
476 int ret;
477
478 /* Soft reset MAC */
479 writel(EMAC_CTL1_SOFT_RST, priv->mac_reg + EMAC_CTL1);
480 ret = wait_for_bit_le32(priv->mac_reg + EMAC_CTL1,
481 EMAC_CTL1_SOFT_RST, false, 10, true);
482 if (ret) {
483 printf("%s: Timeout\n", __func__);
484 return ret;
485 }
486
487 /* Rewrite mac address after reset */
488 sun8i_eth_write_hwaddr(dev);
489
490 /* transmission starts after the full frame arrived in TX DMA FIFO */
491 setbits_le32(priv->mac_reg + EMAC_TX_CTL1, EMAC_TX_CTL1_TX_MD);
492
493 /*
494 * RX DMA reads data from RX DMA FIFO to host memory after a
495 * complete frame has been written to RX DMA FIFO
496 */
497 setbits_le32(priv->mac_reg + EMAC_RX_CTL1, EMAC_RX_CTL1_RX_MD);
498
499 /* DMA burst length */
500 writel(8 << EMAC_CTL1_BURST_LEN_SHIFT, priv->mac_reg + EMAC_CTL1);
501
502 /* Initialize rx/tx descriptors */
503 rx_descs_init(priv);
504 tx_descs_init(priv);
505
506 /* PHY Start Up */
507 ret = phy_startup(priv->phydev);
508 if (ret)
509 return ret;
510
511 sun8i_adjust_link(priv, priv->phydev);
512
513 /* Start RX/TX DMA */
514 setbits_le32(priv->mac_reg + EMAC_RX_CTL1, EMAC_RX_CTL1_RX_DMA_EN |
515 EMAC_RX_CTL1_RX_ERR_FRM | EMAC_RX_CTL1_RX_RUNT_FRM);
516 setbits_le32(priv->mac_reg + EMAC_TX_CTL1, EMAC_TX_CTL1_TX_DMA_EN);
517
518 /* Enable RX/TX */
519 setbits_le32(priv->mac_reg + EMAC_RX_CTL0, EMAC_RX_CTL0_RX_EN);
520 setbits_le32(priv->mac_reg + EMAC_TX_CTL0, EMAC_TX_CTL0_TX_EN);
521
522 return 0;
523 }
524
parse_phy_pins(struct udevice * dev)525 static int parse_phy_pins(struct udevice *dev)
526 {
527 int offset;
528 const char *pin_name;
529 int drive, pull = SUN4I_PINCTRL_NO_PULL, i;
530 u32 iomux;
531
532 offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev),
533 "pinctrl-0");
534 if (offset < 0) {
535 printf("WARNING: emac: cannot find pinctrl-0 node\n");
536 return offset;
537 }
538
539 drive = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0,
540 "drive-strength", ~0);
541 if (drive != ~0) {
542 if (drive <= 10)
543 drive = SUN4I_PINCTRL_10_MA;
544 else if (drive <= 20)
545 drive = SUN4I_PINCTRL_20_MA;
546 else if (drive <= 30)
547 drive = SUN4I_PINCTRL_30_MA;
548 else
549 drive = SUN4I_PINCTRL_40_MA;
550 }
551
552 if (fdt_get_property(gd->fdt_blob, offset, "bias-pull-up", NULL))
553 pull = SUN4I_PINCTRL_PULL_UP;
554 else if (fdt_get_property(gd->fdt_blob, offset, "bias-pull-down", NULL))
555 pull = SUN4I_PINCTRL_PULL_DOWN;
556
557 /*
558 * The GPIO pinmux value is an integration choice, so depends on the
559 * SoC, not the EMAC variant.
560 */
561 if (IS_ENABLED(CONFIG_MACH_SUNXI_H3_H5))
562 iomux = SUN8I_IOMUX_H3;
563 else if (IS_ENABLED(CONFIG_MACH_SUN8I_R40))
564 iomux = SUN8I_IOMUX_R40;
565 else if (IS_ENABLED(CONFIG_MACH_SUN50I_H6))
566 iomux = SUN8I_IOMUX_H6;
567 else if (IS_ENABLED(CONFIG_MACH_SUN50I_H616))
568 iomux = SUN8I_IOMUX_H616;
569 else if (IS_ENABLED(CONFIG_MACH_SUN8I_A83T))
570 iomux = SUN8I_IOMUX;
571 else if (IS_ENABLED(CONFIG_MACH_SUN50I))
572 iomux = SUN8I_IOMUX;
573 else
574 BUILD_BUG_ON_MSG(1, "missing pinmux value for Ethernet pins");
575
576 for (i = 0; ; i++) {
577 int pin;
578
579 pin_name = fdt_stringlist_get(gd->fdt_blob, offset,
580 "pins", i, NULL);
581 if (!pin_name)
582 break;
583
584 pin = sunxi_name_to_gpio(pin_name);
585 if (pin < 0)
586 continue;
587
588 sunxi_gpio_set_cfgpin(pin, iomux);
589
590 if (drive != ~0)
591 sunxi_gpio_set_drv(pin, drive);
592 if (pull != ~0)
593 sunxi_gpio_set_pull(pin, pull);
594 }
595
596 if (!i) {
597 printf("WARNING: emac: cannot find pins property\n");
598 return -2;
599 }
600
601 return 0;
602 }
603
sun8i_emac_eth_recv(struct udevice * dev,int flags,uchar ** packetp)604 static int sun8i_emac_eth_recv(struct udevice *dev, int flags, uchar **packetp)
605 {
606 struct emac_eth_dev *priv = dev_get_priv(dev);
607 u32 status, desc_num = priv->rx_currdescnum;
608 struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num];
609 uintptr_t data_start = (uintptr_t)desc_p->buf_addr;
610 int length;
611
612 /* Invalidate entire buffer descriptor */
613 cache_inv_descriptor(desc_p);
614
615 status = desc_p->status;
616
617 /* Check for DMA own bit */
618 if (status & EMAC_DESC_OWN_DMA)
619 return -EAGAIN;
620
621 length = (status >> 16) & 0x3fff;
622
623 /* make sure we read from DRAM, not our cache */
624 invalidate_dcache_range(data_start,
625 data_start + roundup(length, ARCH_DMA_MINALIGN));
626
627 if (status & EMAC_DESC_RX_ERROR_MASK) {
628 debug("RX: packet error: 0x%x\n",
629 status & EMAC_DESC_RX_ERROR_MASK);
630 return 0;
631 }
632 if (length < 0x40) {
633 debug("RX: Bad Packet (runt)\n");
634 return 0;
635 }
636
637 if (length > CONFIG_ETH_RXSIZE) {
638 debug("RX: Too large packet (%d bytes)\n", length);
639 return 0;
640 }
641
642 *packetp = (uchar *)(ulong)desc_p->buf_addr;
643
644 return length;
645 }
646
sun8i_emac_eth_send(struct udevice * dev,void * packet,int length)647 static int sun8i_emac_eth_send(struct udevice *dev, void *packet, int length)
648 {
649 struct emac_eth_dev *priv = dev_get_priv(dev);
650 u32 desc_num = priv->tx_currdescnum;
651 struct emac_dma_desc *desc_p = &priv->tx_chain[desc_num];
652 uintptr_t data_start = (uintptr_t)desc_p->buf_addr;
653 uintptr_t data_end = data_start +
654 roundup(length, ARCH_DMA_MINALIGN);
655
656 desc_p->ctl_size = length | EMAC_DESC_CHAIN_SECOND;
657
658 memcpy((void *)data_start, packet, length);
659
660 /* Flush data to be sent */
661 flush_dcache_range(data_start, data_end);
662
663 /* frame begin and end */
664 desc_p->ctl_size |= EMAC_DESC_LAST_DESC | EMAC_DESC_FIRST_DESC;
665 desc_p->status = EMAC_DESC_OWN_DMA;
666
667 /* make sure the MAC reads the actual data from DRAM */
668 cache_clean_descriptor(desc_p);
669
670 /* Move to next Descriptor and wrap around */
671 if (++desc_num >= CONFIG_TX_DESCR_NUM)
672 desc_num = 0;
673 priv->tx_currdescnum = desc_num;
674
675 /* Start the DMA */
676 setbits_le32(priv->mac_reg + EMAC_TX_CTL1, EMAC_TX_CTL1_TX_DMA_START);
677
678 /*
679 * Since we copied the data above, we return here without waiting
680 * for the packet to be actually send out.
681 */
682
683 return 0;
684 }
685
sun8i_emac_board_setup(struct udevice * dev,struct emac_eth_dev * priv)686 static int sun8i_emac_board_setup(struct udevice *dev,
687 struct emac_eth_dev *priv)
688 {
689 int ret;
690
691 ret = clk_enable(&priv->tx_clk);
692 if (ret) {
693 dev_err(dev, "failed to enable TX clock\n");
694 return ret;
695 }
696
697 if (reset_valid(&priv->tx_rst)) {
698 ret = reset_deassert(&priv->tx_rst);
699 if (ret) {
700 dev_err(dev, "failed to deassert TX reset\n");
701 goto err_tx_clk;
702 }
703 }
704
705 /* Only H3/H5 have clock controls for internal EPHY */
706 if (clk_valid(&priv->ephy_clk)) {
707 ret = clk_enable(&priv->ephy_clk);
708 if (ret) {
709 dev_err(dev, "failed to enable EPHY TX clock\n");
710 return ret;
711 }
712 }
713
714 if (reset_valid(&priv->ephy_rst)) {
715 ret = reset_deassert(&priv->ephy_rst);
716 if (ret) {
717 dev_err(dev, "failed to deassert EPHY TX clock\n");
718 return ret;
719 }
720 }
721
722 return 0;
723
724 err_tx_clk:
725 clk_disable(&priv->tx_clk);
726 return ret;
727 }
728
729 #if CONFIG_IS_ENABLED(DM_GPIO)
sun8i_mdio_reset(struct mii_dev * bus)730 static int sun8i_mdio_reset(struct mii_dev *bus)
731 {
732 struct udevice *dev = bus->priv;
733 struct emac_eth_dev *priv = dev_get_priv(dev);
734 struct sun8i_eth_pdata *pdata = dev_get_plat(dev);
735 int ret;
736
737 if (!dm_gpio_is_valid(&priv->reset_gpio))
738 return 0;
739
740 /* reset the phy */
741 ret = dm_gpio_set_value(&priv->reset_gpio, 0);
742 if (ret)
743 return ret;
744
745 udelay(pdata->reset_delays[0]);
746
747 ret = dm_gpio_set_value(&priv->reset_gpio, 1);
748 if (ret)
749 return ret;
750
751 udelay(pdata->reset_delays[1]);
752
753 ret = dm_gpio_set_value(&priv->reset_gpio, 0);
754 if (ret)
755 return ret;
756
757 udelay(pdata->reset_delays[2]);
758
759 return 0;
760 }
761 #endif
762
sun8i_mdio_init(const char * name,struct udevice * priv)763 static int sun8i_mdio_init(const char *name, struct udevice *priv)
764 {
765 struct mii_dev *bus = mdio_alloc();
766
767 if (!bus) {
768 debug("Failed to allocate MDIO bus\n");
769 return -ENOMEM;
770 }
771
772 bus->read = sun8i_mdio_read;
773 bus->write = sun8i_mdio_write;
774 snprintf(bus->name, sizeof(bus->name), name);
775 bus->priv = (void *)priv;
776 #if CONFIG_IS_ENABLED(DM_GPIO)
777 bus->reset = sun8i_mdio_reset;
778 #endif
779
780 return mdio_register(bus);
781 }
782
sun8i_eth_free_pkt(struct udevice * dev,uchar * packet,int length)783 static int sun8i_eth_free_pkt(struct udevice *dev, uchar *packet,
784 int length)
785 {
786 struct emac_eth_dev *priv = dev_get_priv(dev);
787 u32 desc_num = priv->rx_currdescnum;
788 struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num];
789
790 /* give the current descriptor back to the MAC */
791 desc_p->status |= EMAC_DESC_OWN_DMA;
792
793 /* Flush Status field of descriptor */
794 cache_clean_descriptor(desc_p);
795
796 /* Move to next desc and wrap-around condition. */
797 if (++desc_num >= CONFIG_RX_DESCR_NUM)
798 desc_num = 0;
799 priv->rx_currdescnum = desc_num;
800
801 return 0;
802 }
803
sun8i_emac_eth_stop(struct udevice * dev)804 static void sun8i_emac_eth_stop(struct udevice *dev)
805 {
806 struct emac_eth_dev *priv = dev_get_priv(dev);
807
808 /* Stop Rx/Tx transmitter */
809 clrbits_le32(priv->mac_reg + EMAC_RX_CTL0, EMAC_RX_CTL0_RX_EN);
810 clrbits_le32(priv->mac_reg + EMAC_TX_CTL0, EMAC_TX_CTL0_TX_EN);
811
812 /* Stop RX/TX DMA */
813 clrbits_le32(priv->mac_reg + EMAC_TX_CTL1, EMAC_TX_CTL1_TX_DMA_EN);
814 clrbits_le32(priv->mac_reg + EMAC_RX_CTL1, EMAC_RX_CTL1_RX_DMA_EN);
815
816 phy_shutdown(priv->phydev);
817 }
818
sun8i_emac_eth_probe(struct udevice * dev)819 static int sun8i_emac_eth_probe(struct udevice *dev)
820 {
821 struct sun8i_eth_pdata *sun8i_pdata = dev_get_plat(dev);
822 struct eth_pdata *pdata = &sun8i_pdata->eth_pdata;
823 struct emac_eth_dev *priv = dev_get_priv(dev);
824 int ret;
825
826 priv->mac_reg = (void *)pdata->iobase;
827
828 ret = sun8i_emac_board_setup(dev, priv);
829 if (ret)
830 return ret;
831
832 sun8i_emac_set_syscon(sun8i_pdata, priv);
833
834 sun8i_mdio_init(dev->name, dev);
835 priv->bus = miiphy_get_dev_by_name(dev->name);
836
837 return sun8i_phy_init(priv, dev);
838 }
839
840 static const struct eth_ops sun8i_emac_eth_ops = {
841 .start = sun8i_emac_eth_start,
842 .write_hwaddr = sun8i_eth_write_hwaddr,
843 .send = sun8i_emac_eth_send,
844 .recv = sun8i_emac_eth_recv,
845 .free_pkt = sun8i_eth_free_pkt,
846 .stop = sun8i_emac_eth_stop,
847 };
848
sun8i_handle_internal_phy(struct udevice * dev,struct emac_eth_dev * priv)849 static int sun8i_handle_internal_phy(struct udevice *dev, struct emac_eth_dev *priv)
850 {
851 struct ofnode_phandle_args phandle;
852 int ret;
853
854 ret = ofnode_parse_phandle_with_args(dev_ofnode(dev), "phy-handle",
855 NULL, 0, 0, &phandle);
856 if (ret)
857 return ret;
858
859 /* If the PHY node is not a child of the internal MDIO bus, we are
860 * using some external PHY.
861 */
862 if (!ofnode_device_is_compatible(ofnode_get_parent(phandle.node),
863 "allwinner,sun8i-h3-mdio-internal"))
864 return 0;
865
866 ret = clk_get_by_index_nodev(phandle.node, 0, &priv->ephy_clk);
867 if (ret) {
868 dev_err(dev, "failed to get EPHY TX clock\n");
869 return ret;
870 }
871
872 ret = reset_get_by_index_nodev(phandle.node, 0, &priv->ephy_rst);
873 if (ret) {
874 dev_err(dev, "failed to get EPHY TX reset\n");
875 return ret;
876 }
877
878 priv->use_internal_phy = true;
879
880 return 0;
881 }
882
sun8i_emac_eth_of_to_plat(struct udevice * dev)883 static int sun8i_emac_eth_of_to_plat(struct udevice *dev)
884 {
885 struct sun8i_eth_pdata *sun8i_pdata = dev_get_plat(dev);
886 struct eth_pdata *pdata = &sun8i_pdata->eth_pdata;
887 struct emac_eth_dev *priv = dev_get_priv(dev);
888 const char *phy_mode;
889 const fdt32_t *reg;
890 int node = dev_of_offset(dev);
891 int offset = 0;
892 #if CONFIG_IS_ENABLED(DM_GPIO)
893 int reset_flags = GPIOD_IS_OUT;
894 #endif
895 int ret;
896
897 pdata->iobase = dev_read_addr(dev);
898 if (pdata->iobase == FDT_ADDR_T_NONE) {
899 debug("%s: Cannot find MAC base address\n", __func__);
900 return -EINVAL;
901 }
902
903 priv->variant = dev_get_driver_data(dev);
904
905 if (!priv->variant) {
906 printf("%s: Missing variant\n", __func__);
907 return -EINVAL;
908 }
909
910 ret = clk_get_by_name(dev, "stmmaceth", &priv->tx_clk);
911 if (ret) {
912 dev_err(dev, "failed to get TX clock\n");
913 return ret;
914 }
915
916 ret = reset_get_by_name(dev, "stmmaceth", &priv->tx_rst);
917 if (ret && ret != -ENOENT) {
918 dev_err(dev, "failed to get TX reset\n");
919 return ret;
920 }
921
922 offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon");
923 if (offset < 0) {
924 debug("%s: cannot find syscon node\n", __func__);
925 return -EINVAL;
926 }
927
928 reg = fdt_getprop(gd->fdt_blob, offset, "reg", NULL);
929 if (!reg) {
930 debug("%s: cannot find reg property in syscon node\n",
931 __func__);
932 return -EINVAL;
933 }
934 priv->sysctl_reg = fdt_translate_address((void *)gd->fdt_blob,
935 offset, reg);
936 if (priv->sysctl_reg == FDT_ADDR_T_NONE) {
937 debug("%s: Cannot find syscon base address\n", __func__);
938 return -EINVAL;
939 }
940
941 pdata->phy_interface = -1;
942 priv->phyaddr = -1;
943 priv->use_internal_phy = false;
944
945 offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy-handle");
946 if (offset < 0) {
947 debug("%s: Cannot find PHY address\n", __func__);
948 return -EINVAL;
949 }
950 priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1);
951
952 phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL);
953
954 if (phy_mode)
955 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
956 printf("phy interface%d\n", pdata->phy_interface);
957
958 if (pdata->phy_interface == -1) {
959 debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
960 return -EINVAL;
961 }
962
963 if (priv->variant == H3_EMAC) {
964 ret = sun8i_handle_internal_phy(dev, priv);
965 if (ret)
966 return ret;
967 }
968
969 priv->interface = pdata->phy_interface;
970
971 if (!priv->use_internal_phy)
972 parse_phy_pins(dev);
973
974 sun8i_pdata->tx_delay_ps = fdtdec_get_int(gd->fdt_blob, node,
975 "allwinner,tx-delay-ps", 0);
976 if (sun8i_pdata->tx_delay_ps < 0 || sun8i_pdata->tx_delay_ps > 700)
977 printf("%s: Invalid TX delay value %d\n", __func__,
978 sun8i_pdata->tx_delay_ps);
979
980 sun8i_pdata->rx_delay_ps = fdtdec_get_int(gd->fdt_blob, node,
981 "allwinner,rx-delay-ps", 0);
982 if (sun8i_pdata->rx_delay_ps < 0 || sun8i_pdata->rx_delay_ps > 3100)
983 printf("%s: Invalid RX delay value %d\n", __func__,
984 sun8i_pdata->rx_delay_ps);
985
986 #if CONFIG_IS_ENABLED(DM_GPIO)
987 if (fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
988 "snps,reset-active-low"))
989 reset_flags |= GPIOD_ACTIVE_LOW;
990
991 ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
992 &priv->reset_gpio, reset_flags);
993
994 if (ret == 0) {
995 ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
996 "snps,reset-delays-us",
997 sun8i_pdata->reset_delays, 3);
998 } else if (ret == -ENOENT) {
999 ret = 0;
1000 }
1001 #endif
1002
1003 return 0;
1004 }
1005
1006 static const struct udevice_id sun8i_emac_eth_ids[] = {
1007 {.compatible = "allwinner,sun8i-h3-emac", .data = (uintptr_t)H3_EMAC },
1008 {.compatible = "allwinner,sun50i-a64-emac",
1009 .data = (uintptr_t)A64_EMAC },
1010 {.compatible = "allwinner,sun8i-a83t-emac",
1011 .data = (uintptr_t)A83T_EMAC },
1012 {.compatible = "allwinner,sun8i-r40-gmac",
1013 .data = (uintptr_t)R40_GMAC },
1014 {.compatible = "allwinner,sun50i-h6-emac",
1015 .data = (uintptr_t)H6_EMAC },
1016 { }
1017 };
1018
1019 U_BOOT_DRIVER(eth_sun8i_emac) = {
1020 .name = "eth_sun8i_emac",
1021 .id = UCLASS_ETH,
1022 .of_match = sun8i_emac_eth_ids,
1023 .of_to_plat = sun8i_emac_eth_of_to_plat,
1024 .probe = sun8i_emac_eth_probe,
1025 .ops = &sun8i_emac_eth_ops,
1026 .priv_auto = sizeof(struct emac_eth_dev),
1027 .plat_auto = sizeof(struct sun8i_eth_pdata),
1028 .flags = DM_FLAG_ALLOC_PRIV_DMA,
1029 };
1030