1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Freescale Three Speed Ethernet Controller driver
4 *
5 * Copyright 2004-2011, 2013 Freescale Semiconductor, Inc.
6 * (C) Copyright 2003, Motorola, Inc.
7 * author Andy Fleming
8 */
9
10 #include <config.h>
11 #include <common.h>
12 #include <dm.h>
13 #include <malloc.h>
14 #include <net.h>
15 #include <command.h>
16 #include <tsec.h>
17 #include <fsl_mdio.h>
18 #include <linux/bitops.h>
19 #include <linux/delay.h>
20 #include <linux/errno.h>
21 #include <miiphy.h>
22 #include <asm/processor.h>
23 #include <asm/io.h>
24
25 #ifndef CONFIG_DM_ETH
26 /* Default initializations for TSEC controllers. */
27
28 static struct tsec_info_struct tsec_info[] = {
29 #ifdef CONFIG_TSEC1
30 STD_TSEC_INFO(1), /* TSEC1 */
31 #endif
32 #ifdef CONFIG_TSEC2
33 STD_TSEC_INFO(2), /* TSEC2 */
34 #endif
35 #ifdef CONFIG_MPC85XX_FEC
36 {
37 .regs = TSEC_GET_REGS(2, 0x2000),
38 .devname = CONFIG_MPC85XX_FEC_NAME,
39 .phyaddr = FEC_PHY_ADDR,
40 .flags = FEC_FLAGS,
41 .mii_devname = DEFAULT_MII_NAME
42 }, /* FEC */
43 #endif
44 #ifdef CONFIG_TSEC3
45 STD_TSEC_INFO(3), /* TSEC3 */
46 #endif
47 #ifdef CONFIG_TSEC4
48 STD_TSEC_INFO(4), /* TSEC4 */
49 #endif
50 };
51 #endif /* CONFIG_DM_ETH */
52
53 #define TBIANA_SETTINGS ( \
54 TBIANA_ASYMMETRIC_PAUSE \
55 | TBIANA_SYMMETRIC_PAUSE \
56 | TBIANA_FULL_DUPLEX \
57 )
58
59 /* By default force the TBI PHY into 1000Mbps full duplex when in SGMII mode */
60 #ifndef CONFIG_TSEC_TBICR_SETTINGS
61 #define CONFIG_TSEC_TBICR_SETTINGS ( \
62 TBICR_PHY_RESET \
63 | TBICR_ANEG_ENABLE \
64 | TBICR_FULL_DUPLEX \
65 | TBICR_SPEED1_SET \
66 )
67 #endif /* CONFIG_TSEC_TBICR_SETTINGS */
68
69 /* Configure the TBI for SGMII operation */
tsec_configure_serdes(struct tsec_private * priv)70 static void tsec_configure_serdes(struct tsec_private *priv)
71 {
72 /*
73 * Access TBI PHY registers at given TSEC register offset as opposed
74 * to the register offset used for external PHY accesses
75 */
76 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
77 0, TBI_ANA, TBIANA_SETTINGS);
78 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
79 0, TBI_TBICON, TBICON_CLK_SELECT);
80 tsec_local_mdio_write(priv->phyregs_sgmii, in_be32(&priv->regs->tbipa),
81 0, TBI_CR, CONFIG_TSEC_TBICR_SETTINGS);
82 }
83
84 /* the 'way' for ethernet-CRC-32. Spliced in from Linux lib/crc32.c
85 * and this is the ethernet-crc method needed for TSEC -- and perhaps
86 * some other adapter -- hash tables
87 */
88 #define CRCPOLY_LE 0xedb88320
ether_crc(size_t len,unsigned char const * p)89 static u32 ether_crc(size_t len, unsigned char const *p)
90 {
91 int i;
92 u32 crc;
93
94 crc = ~0;
95 while (len--) {
96 crc ^= *p++;
97 for (i = 0; i < 8; i++)
98 crc = (crc >> 1) ^ ((crc & 1) ? CRCPOLY_LE : 0);
99 }
100 /* an reverse the bits, cuz of way they arrive -- last-first */
101 crc = (crc >> 16) | (crc << 16);
102 crc = (crc >> 8 & 0x00ff00ff) | (crc << 8 & 0xff00ff00);
103 crc = (crc >> 4 & 0x0f0f0f0f) | (crc << 4 & 0xf0f0f0f0);
104 crc = (crc >> 2 & 0x33333333) | (crc << 2 & 0xcccccccc);
105 crc = (crc >> 1 & 0x55555555) | (crc << 1 & 0xaaaaaaaa);
106 return crc;
107 }
108
109 /* CREDITS: linux gianfar driver, slightly adjusted... thanx. */
110
111 /* Set the appropriate hash bit for the given addr */
112
113 /*
114 * The algorithm works like so:
115 * 1) Take the Destination Address (ie the multicast address), and
116 * do a CRC on it (little endian), and reverse the bits of the
117 * result.
118 * 2) Use the 8 most significant bits as a hash into a 256-entry
119 * table. The table is controlled through 8 32-bit registers:
120 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is entry
121 * 255. This means that the 3 most significant bits in the
122 * hash index which gaddr register to use, and the 5 other bits
123 * indicate which bit (assuming an IBM numbering scheme, which
124 * for PowerPC (tm) is usually the case) in the register holds
125 * the entry.
126 */
127 #ifndef CONFIG_DM_ETH
tsec_mcast_addr(struct eth_device * dev,const u8 * mcast_mac,int join)128 static int tsec_mcast_addr(struct eth_device *dev, const u8 *mcast_mac,
129 int join)
130 #else
131 static int tsec_mcast_addr(struct udevice *dev, const u8 *mcast_mac, int join)
132 #endif
133 {
134 struct tsec_private *priv;
135 struct tsec __iomem *regs;
136 u32 result, value;
137 u8 whichbit, whichreg;
138
139 #ifndef CONFIG_DM_ETH
140 priv = (struct tsec_private *)dev->priv;
141 #else
142 priv = dev_get_priv(dev);
143 #endif
144 regs = priv->regs;
145 result = ether_crc(MAC_ADDR_LEN, mcast_mac);
146 whichbit = (result >> 24) & 0x1f; /* the 5 LSB = which bit to set */
147 whichreg = result >> 29; /* the 3 MSB = which reg to set it in */
148
149 value = BIT(31 - whichbit);
150
151 if (join)
152 setbits_be32(®s->hash.gaddr0 + whichreg, value);
153 else
154 clrbits_be32(®s->hash.gaddr0 + whichreg, value);
155
156 return 0;
157 }
158
159 /*
160 * Initialized required registers to appropriate values, zeroing
161 * those we don't care about (unless zero is bad, in which case,
162 * choose a more appropriate value)
163 */
init_registers(struct tsec __iomem * regs)164 static void init_registers(struct tsec __iomem *regs)
165 {
166 /* Clear IEVENT */
167 out_be32(®s->ievent, IEVENT_INIT_CLEAR);
168
169 out_be32(®s->imask, IMASK_INIT_CLEAR);
170
171 out_be32(®s->hash.iaddr0, 0);
172 out_be32(®s->hash.iaddr1, 0);
173 out_be32(®s->hash.iaddr2, 0);
174 out_be32(®s->hash.iaddr3, 0);
175 out_be32(®s->hash.iaddr4, 0);
176 out_be32(®s->hash.iaddr5, 0);
177 out_be32(®s->hash.iaddr6, 0);
178 out_be32(®s->hash.iaddr7, 0);
179
180 out_be32(®s->hash.gaddr0, 0);
181 out_be32(®s->hash.gaddr1, 0);
182 out_be32(®s->hash.gaddr2, 0);
183 out_be32(®s->hash.gaddr3, 0);
184 out_be32(®s->hash.gaddr4, 0);
185 out_be32(®s->hash.gaddr5, 0);
186 out_be32(®s->hash.gaddr6, 0);
187 out_be32(®s->hash.gaddr7, 0);
188
189 out_be32(®s->rctrl, 0x00000000);
190
191 /* Init RMON mib registers */
192 memset((void *)®s->rmon, 0, sizeof(regs->rmon));
193
194 out_be32(®s->rmon.cam1, 0xffffffff);
195 out_be32(®s->rmon.cam2, 0xffffffff);
196
197 out_be32(®s->mrblr, MRBLR_INIT_SETTINGS);
198
199 out_be32(®s->minflr, MINFLR_INIT_SETTINGS);
200
201 out_be32(®s->attr, ATTR_INIT_SETTINGS);
202 out_be32(®s->attreli, ATTRELI_INIT_SETTINGS);
203 }
204
205 /*
206 * Configure maccfg2 based on negotiated speed and duplex
207 * reported by PHY handling code
208 */
adjust_link(struct tsec_private * priv,struct phy_device * phydev)209 static void adjust_link(struct tsec_private *priv, struct phy_device *phydev)
210 {
211 struct tsec __iomem *regs = priv->regs;
212 u32 ecntrl, maccfg2;
213
214 if (!phydev->link) {
215 printf("%s: No link.\n", phydev->dev->name);
216 return;
217 }
218
219 /* clear all bits relative with interface mode */
220 ecntrl = in_be32(®s->ecntrl);
221 ecntrl &= ~ECNTRL_R100;
222
223 maccfg2 = in_be32(®s->maccfg2);
224 maccfg2 &= ~(MACCFG2_IF | MACCFG2_FULL_DUPLEX);
225
226 if (phydev->duplex)
227 maccfg2 |= MACCFG2_FULL_DUPLEX;
228
229 switch (phydev->speed) {
230 case 1000:
231 maccfg2 |= MACCFG2_GMII;
232 break;
233 case 100:
234 case 10:
235 maccfg2 |= MACCFG2_MII;
236
237 /*
238 * Set R100 bit in all modes although
239 * it is only used in RGMII mode
240 */
241 if (phydev->speed == 100)
242 ecntrl |= ECNTRL_R100;
243 break;
244 default:
245 printf("%s: Speed was bad\n", phydev->dev->name);
246 break;
247 }
248
249 out_be32(®s->ecntrl, ecntrl);
250 out_be32(®s->maccfg2, maccfg2);
251
252 printf("Speed: %d, %s duplex%s\n", phydev->speed,
253 (phydev->duplex) ? "full" : "half",
254 (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
255 }
256
257 /*
258 * This returns the status bits of the device. The return value
259 * is never checked, and this is what the 8260 driver did, so we
260 * do the same. Presumably, this would be zero if there were no
261 * errors
262 */
263 #ifndef CONFIG_DM_ETH
tsec_send(struct eth_device * dev,void * packet,int length)264 static int tsec_send(struct eth_device *dev, void *packet, int length)
265 #else
266 static int tsec_send(struct udevice *dev, void *packet, int length)
267 #endif
268 {
269 struct tsec_private *priv;
270 struct tsec __iomem *regs;
271 int result = 0;
272 u16 status;
273 int i;
274
275 #ifndef CONFIG_DM_ETH
276 priv = (struct tsec_private *)dev->priv;
277 #else
278 priv = dev_get_priv(dev);
279 #endif
280 regs = priv->regs;
281 /* Find an empty buffer descriptor */
282 for (i = 0;
283 in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_READY;
284 i++) {
285 if (i >= TOUT_LOOP) {
286 printf("%s: tsec: tx buffers full\n", dev->name);
287 return result;
288 }
289 }
290
291 out_be32(&priv->txbd[priv->tx_idx].bufptr, (u32)packet);
292 out_be16(&priv->txbd[priv->tx_idx].length, length);
293 status = in_be16(&priv->txbd[priv->tx_idx].status);
294 out_be16(&priv->txbd[priv->tx_idx].status, status |
295 (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT));
296
297 /* Tell the DMA to go */
298 out_be32(®s->tstat, TSTAT_CLEAR_THALT);
299
300 /* Wait for buffer to be transmitted */
301 for (i = 0;
302 in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_READY;
303 i++) {
304 if (i >= TOUT_LOOP) {
305 printf("%s: tsec: tx error\n", dev->name);
306 return result;
307 }
308 }
309
310 priv->tx_idx = (priv->tx_idx + 1) % TX_BUF_CNT;
311 result = in_be16(&priv->txbd[priv->tx_idx].status) & TXBD_STATS;
312
313 return result;
314 }
315
316 #ifndef CONFIG_DM_ETH
tsec_recv(struct eth_device * dev)317 static int tsec_recv(struct eth_device *dev)
318 {
319 struct tsec_private *priv = (struct tsec_private *)dev->priv;
320 struct tsec __iomem *regs = priv->regs;
321
322 while (!(in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY)) {
323 int length = in_be16(&priv->rxbd[priv->rx_idx].length);
324 u16 status = in_be16(&priv->rxbd[priv->rx_idx].status);
325 uchar *packet = net_rx_packets[priv->rx_idx];
326
327 /* Send the packet up if there were no errors */
328 if (!(status & RXBD_STATS))
329 net_process_received_packet(packet, length - 4);
330 else
331 printf("Got error %x\n", (status & RXBD_STATS));
332
333 out_be16(&priv->rxbd[priv->rx_idx].length, 0);
334
335 status = RXBD_EMPTY;
336 /* Set the wrap bit if this is the last element in the list */
337 if ((priv->rx_idx + 1) == PKTBUFSRX)
338 status |= RXBD_WRAP;
339 out_be16(&priv->rxbd[priv->rx_idx].status, status);
340
341 priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
342 }
343
344 if (in_be32(®s->ievent) & IEVENT_BSY) {
345 out_be32(®s->ievent, IEVENT_BSY);
346 out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
347 }
348
349 return -1;
350 }
351 #else
tsec_recv(struct udevice * dev,int flags,uchar ** packetp)352 static int tsec_recv(struct udevice *dev, int flags, uchar **packetp)
353 {
354 struct tsec_private *priv = (struct tsec_private *)dev_get_priv(dev);
355 struct tsec __iomem *regs = priv->regs;
356 int ret = -1;
357
358 if (!(in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY)) {
359 int length = in_be16(&priv->rxbd[priv->rx_idx].length);
360 u16 status = in_be16(&priv->rxbd[priv->rx_idx].status);
361 u32 buf;
362
363 /* Send the packet up if there were no errors */
364 if (!(status & RXBD_STATS)) {
365 buf = in_be32(&priv->rxbd[priv->rx_idx].bufptr);
366 *packetp = (uchar *)buf;
367 ret = length - 4;
368 } else {
369 printf("Got error %x\n", (status & RXBD_STATS));
370 }
371 }
372
373 if (in_be32(®s->ievent) & IEVENT_BSY) {
374 out_be32(®s->ievent, IEVENT_BSY);
375 out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
376 }
377
378 return ret;
379 }
380
tsec_free_pkt(struct udevice * dev,uchar * packet,int length)381 static int tsec_free_pkt(struct udevice *dev, uchar *packet, int length)
382 {
383 struct tsec_private *priv = (struct tsec_private *)dev_get_priv(dev);
384 u16 status;
385
386 out_be16(&priv->rxbd[priv->rx_idx].length, 0);
387
388 status = RXBD_EMPTY;
389 /* Set the wrap bit if this is the last element in the list */
390 if ((priv->rx_idx + 1) == PKTBUFSRX)
391 status |= RXBD_WRAP;
392 out_be16(&priv->rxbd[priv->rx_idx].status, status);
393
394 priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
395
396 return 0;
397 }
398 #endif
399
400 /* Stop the interface */
401 #ifndef CONFIG_DM_ETH
tsec_halt(struct eth_device * dev)402 static void tsec_halt(struct eth_device *dev)
403 #else
404 static void tsec_halt(struct udevice *dev)
405 #endif
406 {
407 struct tsec_private *priv;
408 struct tsec __iomem *regs;
409 #ifndef CONFIG_DM_ETH
410 priv = (struct tsec_private *)dev->priv;
411 #else
412 priv = dev_get_priv(dev);
413 #endif
414 regs = priv->regs;
415
416 clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
417 setbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
418
419 while ((in_be32(®s->ievent) & (IEVENT_GRSC | IEVENT_GTSC))
420 != (IEVENT_GRSC | IEVENT_GTSC))
421 ;
422
423 clrbits_be32(®s->maccfg1, MACCFG1_TX_EN | MACCFG1_RX_EN);
424
425 /* Shut down the PHY, as needed */
426 phy_shutdown(priv->phydev);
427 }
428
429 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
430 /*
431 * When MACCFG1[Rx_EN] is enabled during system boot as part
432 * of the eTSEC port initialization sequence,
433 * the eTSEC Rx logic may not be properly initialized.
434 */
redundant_init(struct tsec_private * priv)435 void redundant_init(struct tsec_private *priv)
436 {
437 struct tsec __iomem *regs = priv->regs;
438 uint t, count = 0;
439 int fail = 1;
440 static const u8 pkt[] = {
441 0x00, 0x1e, 0x4f, 0x12, 0xcb, 0x2c, 0x00, 0x25,
442 0x64, 0xbb, 0xd1, 0xab, 0x08, 0x00, 0x45, 0x00,
443 0x00, 0x5c, 0xdd, 0x22, 0x00, 0x00, 0x80, 0x01,
444 0x1f, 0x71, 0x0a, 0xc1, 0x14, 0x22, 0x0a, 0xc1,
445 0x14, 0x6a, 0x08, 0x00, 0xef, 0x7e, 0x02, 0x00,
446 0x94, 0x05, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66,
447 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e,
448 0x6f, 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76,
449 0x77, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67,
450 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
451 0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77,
452 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68,
453 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f, 0x70,
454 0x71, 0x72};
455
456 /* Enable promiscuous mode */
457 setbits_be32(®s->rctrl, 0x8);
458 /* Enable loopback mode */
459 setbits_be32(®s->maccfg1, MACCFG1_LOOPBACK);
460 /* Enable transmit and receive */
461 setbits_be32(®s->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
462
463 /* Tell the DMA it is clear to go */
464 setbits_be32(®s->dmactrl, DMACTRL_INIT_SETTINGS);
465 out_be32(®s->tstat, TSTAT_CLEAR_THALT);
466 out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
467 clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
468
469 do {
470 u16 status;
471
472 tsec_send(priv->dev, (void *)pkt, sizeof(pkt));
473
474 /* Wait for buffer to be received */
475 for (t = 0;
476 in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY;
477 t++) {
478 if (t >= 10 * TOUT_LOOP) {
479 printf("%s: tsec: rx error\n", priv->dev->name);
480 break;
481 }
482 }
483
484 if (!memcmp(pkt, net_rx_packets[priv->rx_idx], sizeof(pkt)))
485 fail = 0;
486
487 out_be16(&priv->rxbd[priv->rx_idx].length, 0);
488 status = RXBD_EMPTY;
489 if ((priv->rx_idx + 1) == PKTBUFSRX)
490 status |= RXBD_WRAP;
491 out_be16(&priv->rxbd[priv->rx_idx].status, status);
492 priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
493
494 if (in_be32(®s->ievent) & IEVENT_BSY) {
495 out_be32(®s->ievent, IEVENT_BSY);
496 out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
497 }
498 if (fail) {
499 printf("loopback recv packet error!\n");
500 clrbits_be32(®s->maccfg1, MACCFG1_RX_EN);
501 udelay(1000);
502 setbits_be32(®s->maccfg1, MACCFG1_RX_EN);
503 }
504 } while ((count++ < 4) && (fail == 1));
505
506 if (fail)
507 panic("eTSEC init fail!\n");
508 /* Disable promiscuous mode */
509 clrbits_be32(®s->rctrl, 0x8);
510 /* Disable loopback mode */
511 clrbits_be32(®s->maccfg1, MACCFG1_LOOPBACK);
512 }
513 #endif
514
515 /*
516 * Set up the buffers and their descriptors, and bring up the
517 * interface
518 */
startup_tsec(struct tsec_private * priv)519 static void startup_tsec(struct tsec_private *priv)
520 {
521 struct tsec __iomem *regs = priv->regs;
522 u16 status;
523 int i;
524
525 /* reset the indices to zero */
526 priv->rx_idx = 0;
527 priv->tx_idx = 0;
528 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
529 uint svr;
530 #endif
531
532 /* Point to the buffer descriptors */
533 out_be32(®s->tbase, (u32)&priv->txbd[0]);
534 out_be32(®s->rbase, (u32)&priv->rxbd[0]);
535
536 /* Initialize the Rx Buffer descriptors */
537 for (i = 0; i < PKTBUFSRX; i++) {
538 out_be16(&priv->rxbd[i].status, RXBD_EMPTY);
539 out_be16(&priv->rxbd[i].length, 0);
540 out_be32(&priv->rxbd[i].bufptr, (u32)net_rx_packets[i]);
541 }
542 status = in_be16(&priv->rxbd[PKTBUFSRX - 1].status);
543 out_be16(&priv->rxbd[PKTBUFSRX - 1].status, status | RXBD_WRAP);
544
545 /* Initialize the TX Buffer Descriptors */
546 for (i = 0; i < TX_BUF_CNT; i++) {
547 out_be16(&priv->txbd[i].status, 0);
548 out_be16(&priv->txbd[i].length, 0);
549 out_be32(&priv->txbd[i].bufptr, 0);
550 }
551 status = in_be16(&priv->txbd[TX_BUF_CNT - 1].status);
552 out_be16(&priv->txbd[TX_BUF_CNT - 1].status, status | TXBD_WRAP);
553
554 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
555 svr = get_svr();
556 if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
557 redundant_init(priv);
558 #endif
559 /* Enable Transmit and Receive */
560 setbits_be32(®s->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN);
561
562 /* Tell the DMA it is clear to go */
563 setbits_be32(®s->dmactrl, DMACTRL_INIT_SETTINGS);
564 out_be32(®s->tstat, TSTAT_CLEAR_THALT);
565 out_be32(®s->rstat, RSTAT_CLEAR_RHALT);
566 clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
567 }
568
569 /*
570 * Initializes data structures and registers for the controller,
571 * and brings the interface up. Returns the link status, meaning
572 * that it returns success if the link is up, failure otherwise.
573 * This allows U-Boot to find the first active controller.
574 */
575 #ifndef CONFIG_DM_ETH
tsec_init(struct eth_device * dev,struct bd_info * bd)576 static int tsec_init(struct eth_device *dev, struct bd_info *bd)
577 #else
578 static int tsec_init(struct udevice *dev)
579 #endif
580 {
581 struct tsec_private *priv;
582 struct tsec __iomem *regs;
583 #ifdef CONFIG_DM_ETH
584 struct eth_pdata *pdata = dev_get_plat(dev);
585 #else
586 struct eth_device *pdata = dev;
587 #endif
588 u32 tempval;
589 int ret;
590
591 #ifndef CONFIG_DM_ETH
592 priv = (struct tsec_private *)dev->priv;
593 #else
594 priv = dev_get_priv(dev);
595 #endif
596 regs = priv->regs;
597 /* Make sure the controller is stopped */
598 tsec_halt(dev);
599
600 /* Init MACCFG2. Defaults to GMII */
601 out_be32(®s->maccfg2, MACCFG2_INIT_SETTINGS);
602
603 /* Init ECNTRL */
604 out_be32(®s->ecntrl, ECNTRL_INIT_SETTINGS);
605
606 /*
607 * Copy the station address into the address registers.
608 * For a station address of 0x12345678ABCD in transmission
609 * order (BE), MACnADDR1 is set to 0xCDAB7856 and
610 * MACnADDR2 is set to 0x34120000.
611 */
612 tempval = (pdata->enetaddr[5] << 24) | (pdata->enetaddr[4] << 16) |
613 (pdata->enetaddr[3] << 8) | pdata->enetaddr[2];
614
615 out_be32(®s->macstnaddr1, tempval);
616
617 tempval = (pdata->enetaddr[1] << 24) | (pdata->enetaddr[0] << 16);
618
619 out_be32(®s->macstnaddr2, tempval);
620
621 /* Clear out (for the most part) the other registers */
622 init_registers(regs);
623
624 /* Ready the device for tx/rx */
625 startup_tsec(priv);
626
627 /* Start up the PHY */
628 ret = phy_startup(priv->phydev);
629 if (ret) {
630 printf("Could not initialize PHY %s\n",
631 priv->phydev->dev->name);
632 return ret;
633 }
634
635 adjust_link(priv, priv->phydev);
636
637 /* If there's no link, fail */
638 return priv->phydev->link ? 0 : -1;
639 }
640
tsec_get_interface(struct tsec_private * priv)641 static phy_interface_t tsec_get_interface(struct tsec_private *priv)
642 {
643 struct tsec __iomem *regs = priv->regs;
644 u32 ecntrl;
645
646 ecntrl = in_be32(®s->ecntrl);
647
648 if (ecntrl & ECNTRL_SGMII_MODE)
649 return PHY_INTERFACE_MODE_SGMII;
650
651 if (ecntrl & ECNTRL_TBI_MODE) {
652 if (ecntrl & ECNTRL_REDUCED_MODE)
653 return PHY_INTERFACE_MODE_RTBI;
654 else
655 return PHY_INTERFACE_MODE_TBI;
656 }
657
658 if (ecntrl & ECNTRL_REDUCED_MODE) {
659 phy_interface_t interface;
660
661 if (ecntrl & ECNTRL_REDUCED_MII_MODE)
662 return PHY_INTERFACE_MODE_RMII;
663
664 interface = priv->interface;
665
666 /*
667 * This isn't autodetected, so it must
668 * be set by the platform code.
669 */
670 if (interface == PHY_INTERFACE_MODE_RGMII_ID ||
671 interface == PHY_INTERFACE_MODE_RGMII_TXID ||
672 interface == PHY_INTERFACE_MODE_RGMII_RXID)
673 return interface;
674
675 return PHY_INTERFACE_MODE_RGMII;
676 }
677
678 if (priv->flags & TSEC_GIGABIT)
679 return PHY_INTERFACE_MODE_GMII;
680
681 return PHY_INTERFACE_MODE_MII;
682 }
683
684 /*
685 * Discover which PHY is attached to the device, and configure it
686 * properly. If the PHY is not recognized, then return 0
687 * (failure). Otherwise, return 1
688 */
init_phy(struct tsec_private * priv)689 static int init_phy(struct tsec_private *priv)
690 {
691 struct phy_device *phydev;
692 struct tsec __iomem *regs = priv->regs;
693 u32 supported = (SUPPORTED_10baseT_Half |
694 SUPPORTED_10baseT_Full |
695 SUPPORTED_100baseT_Half |
696 SUPPORTED_100baseT_Full);
697
698 if (priv->flags & TSEC_GIGABIT)
699 supported |= SUPPORTED_1000baseT_Full;
700
701 /* Assign a Physical address to the TBI */
702 out_be32(®s->tbipa, priv->tbiaddr);
703
704 priv->interface = tsec_get_interface(priv);
705
706 if (priv->interface == PHY_INTERFACE_MODE_SGMII)
707 tsec_configure_serdes(priv);
708
709 #if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_MDIO)
710 phydev = dm_eth_phy_connect(priv->dev);
711 #else
712 phydev = phy_connect(priv->bus, priv->phyaddr, priv->dev,
713 priv->interface);
714 #endif
715 if (!phydev)
716 return 0;
717
718 phydev->supported &= supported;
719 phydev->advertising = phydev->supported;
720
721 priv->phydev = phydev;
722
723 phy_config(phydev);
724
725 return 1;
726 }
727
728 #ifndef CONFIG_DM_ETH
729 /*
730 * Initialize device structure. Returns success if PHY
731 * initialization succeeded (i.e. if it recognizes the PHY)
732 */
tsec_initialize(struct bd_info * bis,struct tsec_info_struct * tsec_info)733 static int tsec_initialize(struct bd_info *bis,
734 struct tsec_info_struct *tsec_info)
735 {
736 struct tsec_private *priv;
737 struct eth_device *dev;
738 int i;
739
740 dev = (struct eth_device *)malloc(sizeof(*dev));
741
742 if (!dev)
743 return 0;
744
745 memset(dev, 0, sizeof(*dev));
746
747 priv = (struct tsec_private *)malloc(sizeof(*priv));
748
749 if (!priv) {
750 free(dev);
751 return 0;
752 }
753
754 priv->regs = tsec_info->regs;
755 priv->phyregs_sgmii = tsec_info->miiregs_sgmii;
756
757 priv->phyaddr = tsec_info->phyaddr;
758 priv->tbiaddr = CONFIG_SYS_TBIPA_VALUE;
759 priv->flags = tsec_info->flags;
760
761 strcpy(dev->name, tsec_info->devname);
762 priv->interface = tsec_info->interface;
763 priv->bus = miiphy_get_dev_by_name(tsec_info->mii_devname);
764 priv->dev = dev;
765 dev->iobase = 0;
766 dev->priv = priv;
767 dev->init = tsec_init;
768 dev->halt = tsec_halt;
769 dev->send = tsec_send;
770 dev->recv = tsec_recv;
771 dev->mcast = tsec_mcast_addr;
772
773 /* Tell U-Boot to get the addr from the env */
774 for (i = 0; i < 6; i++)
775 dev->enetaddr[i] = 0;
776
777 eth_register(dev);
778
779 /* Reset the MAC */
780 setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
781 udelay(2); /* Soft Reset must be asserted for 3 TX clocks */
782 clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
783
784 /* Try to initialize PHY here, and return */
785 return init_phy(priv);
786 }
787
788 /*
789 * Initialize all the TSEC devices
790 *
791 * Returns the number of TSEC devices that were initialized
792 */
tsec_eth_init(struct bd_info * bis,struct tsec_info_struct * tsecs,int num)793 int tsec_eth_init(struct bd_info *bis, struct tsec_info_struct *tsecs,
794 int num)
795 {
796 int i;
797 int count = 0;
798
799 for (i = 0; i < num; i++) {
800 int ret = tsec_initialize(bis, &tsecs[i]);
801
802 if (ret > 0)
803 count += ret;
804 }
805
806 return count;
807 }
808
tsec_standard_init(struct bd_info * bis)809 int tsec_standard_init(struct bd_info *bis)
810 {
811 struct fsl_pq_mdio_info info;
812
813 info.regs = TSEC_GET_MDIO_REGS_BASE(1);
814 info.name = DEFAULT_MII_NAME;
815
816 fsl_pq_mdio_init(bis, &info);
817
818 return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info));
819 }
820 #else /* CONFIG_DM_ETH */
tsec_probe(struct udevice * dev)821 int tsec_probe(struct udevice *dev)
822 {
823 struct eth_pdata *pdata = dev_get_plat(dev);
824 struct tsec_private *priv = dev_get_priv(dev);
825 struct ofnode_phandle_args phandle_args;
826 u32 tbiaddr = CONFIG_SYS_TBIPA_VALUE;
827 struct tsec_data *data;
828 const char *phy_mode;
829 ofnode parent, child;
830 fdt_addr_t reg;
831 u32 max_speed;
832 int ret;
833
834 data = (struct tsec_data *)dev_get_driver_data(dev);
835
836 pdata->iobase = (phys_addr_t)dev_read_addr(dev);
837 if (pdata->iobase == FDT_ADDR_T_NONE) {
838 ofnode_for_each_subnode(child, dev_ofnode(dev)) {
839 if (strncmp(ofnode_get_name(child), "queue-group",
840 strlen("queue-group")))
841 continue;
842
843 reg = ofnode_get_addr(child);
844 if (reg == FDT_ADDR_T_NONE) {
845 printf("No 'reg' property of <queue-group>\n");
846 return -ENOENT;
847 }
848 pdata->iobase = reg;
849
850 /*
851 * if there are multiple queue groups,
852 * only the first one is used.
853 */
854 break;
855 }
856
857 if (!ofnode_valid(child)) {
858 printf("No child node for <queue-group>?\n");
859 return -ENOENT;
860 }
861 }
862
863 priv->regs = map_physmem(pdata->iobase, 0, MAP_NOCACHE);
864
865 ret = dev_read_phandle_with_args(dev, "tbi-handle", NULL, 0, 0,
866 &phandle_args);
867 if (ret == 0) {
868 ofnode_read_u32(phandle_args.node, "reg", &tbiaddr);
869
870 parent = ofnode_get_parent(phandle_args.node);
871 if (!ofnode_valid(parent)) {
872 printf("No parent node for TBI PHY?\n");
873 return -ENOENT;
874 }
875
876 reg = ofnode_get_addr_index(parent, 0);
877 if (reg == FDT_ADDR_T_NONE) {
878 printf("No 'reg' property of MII for TBI PHY\n");
879 return -ENOENT;
880 }
881
882 priv->phyregs_sgmii = map_physmem(reg + data->mdio_regs_off,
883 0, MAP_NOCACHE);
884 }
885
886 priv->tbiaddr = tbiaddr;
887
888 phy_mode = dev_read_prop(dev, "phy-connection-type", NULL);
889 if (phy_mode)
890 pdata->phy_interface = phy_get_interface_by_name(phy_mode);
891 if (pdata->phy_interface == -1) {
892 printf("Invalid PHY interface '%s'\n", phy_mode);
893 return -EINVAL;
894 }
895 priv->interface = pdata->phy_interface;
896
897 /* Check for speed limit, default is 1000Mbps */
898 max_speed = dev_read_u32_default(dev, "max-speed", 1000);
899
900 /* Initialize flags */
901 if (max_speed == 1000)
902 priv->flags = TSEC_GIGABIT;
903 if (priv->interface == PHY_INTERFACE_MODE_SGMII)
904 priv->flags |= TSEC_SGMII;
905
906 /* Reset the MAC */
907 setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
908 udelay(2); /* Soft Reset must be asserted for 3 TX clocks */
909 clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
910
911 priv->dev = dev;
912 priv->bus = miiphy_get_dev_by_name(dev->name);
913
914 /* Try to initialize PHY here, and return */
915 return !init_phy(priv);
916 }
917
tsec_remove(struct udevice * dev)918 int tsec_remove(struct udevice *dev)
919 {
920 struct tsec_private *priv = dev_get_priv(dev);
921
922 free(priv->phydev);
923 mdio_unregister(priv->bus);
924 mdio_free(priv->bus);
925
926 return 0;
927 }
928
929 static const struct eth_ops tsec_ops = {
930 .start = tsec_init,
931 .send = tsec_send,
932 .recv = tsec_recv,
933 .free_pkt = tsec_free_pkt,
934 .stop = tsec_halt,
935 .mcast = tsec_mcast_addr,
936 };
937
938 static struct tsec_data etsec2_data = {
939 .mdio_regs_off = TSEC_MDIO_REGS_OFFSET,
940 };
941
942 static struct tsec_data gianfar_data = {
943 .mdio_regs_off = 0x0,
944 };
945
946 static const struct udevice_id tsec_ids[] = {
947 { .compatible = "fsl,etsec2", .data = (ulong)&etsec2_data },
948 { .compatible = "gianfar", .data = (ulong)&gianfar_data },
949 { }
950 };
951
952 U_BOOT_DRIVER(eth_tsec) = {
953 .name = "tsec",
954 .id = UCLASS_ETH,
955 .of_match = tsec_ids,
956 .probe = tsec_probe,
957 .remove = tsec_remove,
958 .ops = &tsec_ops,
959 .priv_auto = sizeof(struct tsec_private),
960 .plat_auto = sizeof(struct eth_pdata),
961 .flags = DM_FLAG_ALLOC_PRIV_DMA,
962 };
963 #endif /* CONFIG_DM_ETH */
964