1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2009-2012 Freescale Semiconductor, Inc
4 */
5
6 #include <common.h>
7 #include <asm-offsets.h>
8 #include <asm/global_data.h>
9 #include <asm/processor.h>
10 #include <asm/mmu.h>
11 #include <asm/fsl_law.h>
12 #include <asm/io.h>
13
14 DECLARE_GLOBAL_DATA_PTR;
15
16 #ifdef CONFIG_A003399_NOR_WORKAROUND
setup_ifc(void)17 void setup_ifc(void)
18 {
19 struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
20 u32 _mas0, _mas1, _mas2, _mas3, _mas7;
21 phys_addr_t flash_phys = CONFIG_SYS_FLASH_BASE_PHYS;
22
23 /*
24 * Adjust the TLB we were running out of to match the phys addr of the
25 * chip select we are adjusting and will return to.
26 */
27 flash_phys += (~CONFIG_SYS_AMASK0) + 1 - 4*1024*1024;
28
29 _mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(15);
30 _mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_IPROT |
31 MAS1_TSIZE(BOOKE_PAGESZ_4M);
32 _mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE, MAS2_I|MAS2_G);
33 _mas3 = FSL_BOOKE_MAS3(flash_phys, 0, MAS3_SW|MAS3_SR|MAS3_SX);
34 _mas7 = FSL_BOOKE_MAS7(flash_phys);
35
36 mtspr(MAS0, _mas0);
37 mtspr(MAS1, _mas1);
38 mtspr(MAS2, _mas2);
39 mtspr(MAS3, _mas3);
40 mtspr(MAS7, _mas7);
41
42 asm volatile("isync;msync;tlbwe;isync");
43
44 #if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB)
45 /*
46 * TLB entry for debuggging in AS1
47 * Create temporary TLB entry in AS0 to handle debug exception
48 * As on debug exception MSR is cleared i.e. Address space is changed
49 * to 0. A TLB entry (in AS0) is required to handle debug exception generated
50 * in AS1.
51 *
52 * TLB entry is created for IVPR + IVOR15 to map on valid OP code address
53 * bacause flash's physical address is going to change as
54 * CONFIG_SYS_FLASH_BASE_PHYS.
55 */
56 _mas0 = MAS0_TLBSEL(1) |
57 MAS0_ESEL(CONFIG_SYS_PPC_E500_DEBUG_TLB);
58 _mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_IPROT |
59 MAS1_TSIZE(BOOKE_PAGESZ_4M);
60 _mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_TEXT_BASE, MAS2_I|MAS2_G);
61 _mas3 = FSL_BOOKE_MAS3(flash_phys, 0, MAS3_SW|MAS3_SR|MAS3_SX);
62 _mas7 = FSL_BOOKE_MAS7(flash_phys);
63
64 mtspr(MAS0, _mas0);
65 mtspr(MAS1, _mas1);
66 mtspr(MAS2, _mas2);
67 mtspr(MAS3, _mas3);
68 mtspr(MAS7, _mas7);
69
70 asm volatile("isync;msync;tlbwe;isync");
71 #endif
72
73 /* Change flash's physical address */
74 ifc_out32(&(ifc_regs.gregs->cspr_cs[0].cspr), CONFIG_SYS_CSPR0);
75 ifc_out32(&(ifc_regs.gregs->csor_cs[0].csor), CONFIG_SYS_CSOR0);
76 ifc_out32(&(ifc_regs.gregs->amask_cs[0].amask), CONFIG_SYS_AMASK0);
77
78 return ;
79 }
80 #endif
81
82 /* We run cpu_init_early_f in AS = 1 */
cpu_init_early_f(void * fdt)83 void cpu_init_early_f(void *fdt)
84 {
85 u32 mas0, mas1, mas2, mas3, mas7;
86 #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
87 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
88 #endif
89 #ifdef CONFIG_A003399_NOR_WORKAROUND
90 ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
91 u32 *dst, *src;
92 void (*setup_ifc_sram)(void);
93 int i;
94 #endif
95
96 /* Pointer is writable since we allocated a register for it */
97 gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
98
99 /* gd area was zeroed during startup */
100
101 #ifdef CONFIG_ARCH_QEMU_E500
102 /*
103 * CONFIG_SYS_CCSRBAR_PHYS below may use gd->fdt_blob on ePAPR systems,
104 * so we need to populate it before it accesses it.
105 */
106 gd->fdt_blob = fdt;
107 #endif
108
109 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(13);
110 mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M);
111 mas2 = FSL_BOOKE_MAS2(CONFIG_SYS_CCSRBAR, MAS2_I|MAS2_G);
112 mas3 = FSL_BOOKE_MAS3(CONFIG_SYS_CCSRBAR_PHYS, 0, MAS3_SW|MAS3_SR);
113 mas7 = FSL_BOOKE_MAS7(CONFIG_SYS_CCSRBAR_PHYS);
114
115 write_tlb(mas0, mas1, mas2, mas3, mas7);
116
117 /*
118 * Work Around for IFC Erratum A-003549. This issue is P1010
119 * specific. LCLK(a free running clk signal) is muxed with IFC_CS3 on P1010 SOC
120 * Hence specifically selecting CS3.
121 */
122 #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
123 setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_LCLK_IFC_CS3);
124 #endif
125
126 #ifdef CONFIG_FSL_LAW
127 init_laws();
128 #endif
129
130 /*
131 * Work Around for IFC Erratum A003399, issue will hit only when execution
132 * from NOR Flash
133 */
134 #ifdef CONFIG_A003399_NOR_WORKAROUND
135 #define SRAM_BASE_ADDR (0x00000000)
136 /* TLB for SRAM */
137 mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(9);
138 mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS |
139 MAS1_TSIZE(BOOKE_PAGESZ_1M);
140 mas2 = FSL_BOOKE_MAS2(SRAM_BASE_ADDR, MAS2_I);
141 mas3 = FSL_BOOKE_MAS3(SRAM_BASE_ADDR, 0, MAS3_SX|MAS3_SW|MAS3_SR);
142 mas7 = FSL_BOOKE_MAS7(0);
143
144 write_tlb(mas0, mas1, mas2, mas3, mas7);
145
146 out_be32(&l2cache->l2srbar0, SRAM_BASE_ADDR);
147
148 out_be32(&l2cache->l2errdis,
149 (MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC));
150
151 out_be32(&l2cache->l2ctl,
152 (MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE));
153
154 /*
155 * Copy the code in setup_ifc to L2SRAM. Do a word copy
156 * because NOR Flash on P1010 does not support byte
157 * access (Erratum IFC-A002769)
158 */
159 setup_ifc_sram = (void *)SRAM_BASE_ADDR;
160 dst = (u32 *) SRAM_BASE_ADDR;
161 src = (u32 *) setup_ifc;
162 for (i = 0; i < 1024; i++) {
163 /* cppcheck-suppress nullPointer */
164 *dst++ = *src++;
165 }
166
167 /* cppcheck-suppress nullPointer */
168 setup_ifc_sram();
169
170 /* CLEANUP */
171 clrbits_be32(&l2cache->l2ctl,
172 (MPC85xx_L2CTL_L2E |
173 MPC85xx_L2CTL_L2SRAM_ENTIRE));
174 out_be32(&l2cache->l2srbar0, 0x0);
175 #endif
176
177 invalidate_tlb(1);
178
179 #if defined(CONFIG_SYS_PPC_E500_DEBUG_TLB) && \
180 !(defined(CONFIG_SPL_INIT_MINIMAL) && defined(CONFIG_SPL_BUILD)) && \
181 !defined(CONFIG_NAND_SPL)
182 disable_tlb(CONFIG_SYS_PPC_E500_DEBUG_TLB);
183 #endif
184
185 init_tlbs();
186 }
187