1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2011 Freescale Semiconductor, Inc.
4 * Jason Liu <r64343@freescale.com>
5 */
6
7 #include <common.h>
8 #include <init.h>
9 #include <log.h>
10 #include <asm/global_data.h>
11 #include <asm/io.h>
12 #include <asm/arch/imx-regs.h>
13 #include <asm/arch/sys_proto.h>
14 #include <asm/arch/crm_regs.h>
15 #include <asm/arch/clock.h>
16 #include <asm/arch/iomux-mx53.h>
17 #include <asm/arch/clock.h>
18 #include <env.h>
19 #include <linux/errno.h>
20 #include <asm/mach-imx/mx5_video.h>
21 #include <i2c.h>
22 #include <input.h>
23 #include <fsl_esdhc_imx.h>
24 #include <asm/gpio.h>
25 #include <power/pmic.h>
26 #include <dialog_pmic.h>
27 #include <fsl_pmic.h>
28 #include <linux/fb.h>
29 #include <ipu_pixfmt.h>
30
31 #define MX53LOCO_LCD_POWER IMX_GPIO_NR(3, 24)
32
33 DECLARE_GLOBAL_DATA_PTR;
34
get_board_rev(void)35 u32 get_board_rev(void)
36 {
37 struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
38 struct fuse_bank *bank = &iim->bank[0];
39 struct fuse_bank0_regs *fuse =
40 (struct fuse_bank0_regs *)bank->fuse_regs;
41
42 int rev = readl(&fuse->gp[6]);
43
44 if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR))
45 rev = 0;
46
47 return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
48 }
49
50 #define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
51 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
52
setup_iomux_uart(void)53 static void setup_iomux_uart(void)
54 {
55 static const iomux_v3_cfg_t uart_pads[] = {
56 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, UART_PAD_CTRL),
57 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, UART_PAD_CTRL),
58 };
59
60 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
61 }
62
63 #define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
64 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
65
setup_iomux_i2c(void)66 static void setup_iomux_i2c(void)
67 {
68 static const iomux_v3_cfg_t i2c1_pads[] = {
69 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__I2C1_SDA, I2C_PAD_CTRL),
70 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__I2C1_SCL, I2C_PAD_CTRL),
71 };
72
73 imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads));
74 }
75
power_init(void)76 static int power_init(void)
77 {
78 unsigned int val;
79 int ret;
80 struct pmic *p;
81
82 if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR)) {
83 ret = pmic_dialog_init(I2C_PMIC);
84 if (ret)
85 return ret;
86
87 p = pmic_get("DIALOG_PMIC");
88 if (!p)
89 return -ENODEV;
90
91 env_set("fdt_file", "imx53-qsb.dtb");
92
93 /* Set VDDA to 1.25V */
94 val = DA9052_BUCKCORE_BCOREEN | DA_BUCKCORE_VBCORE_1_250V;
95 ret = pmic_reg_write(p, DA9053_BUCKCORE_REG, val);
96 if (ret) {
97 printf("Writing to BUCKCORE_REG failed: %d\n", ret);
98 return ret;
99 }
100
101 pmic_reg_read(p, DA9053_SUPPLY_REG, &val);
102 val |= DA9052_SUPPLY_VBCOREGO;
103 ret = pmic_reg_write(p, DA9053_SUPPLY_REG, val);
104 if (ret) {
105 printf("Writing to SUPPLY_REG failed: %d\n", ret);
106 return ret;
107 }
108
109 /* Set Vcc peripheral to 1.30V */
110 ret = pmic_reg_write(p, DA9053_BUCKPRO_REG, 0x62);
111 if (ret) {
112 printf("Writing to BUCKPRO_REG failed: %d\n", ret);
113 return ret;
114 }
115
116 ret = pmic_reg_write(p, DA9053_SUPPLY_REG, 0x62);
117 if (ret) {
118 printf("Writing to SUPPLY_REG failed: %d\n", ret);
119 return ret;
120 }
121
122 return ret;
123 }
124
125 if (!i2c_probe(CONFIG_SYS_FSL_PMIC_I2C_ADDR)) {
126 ret = pmic_init(I2C_0);
127 if (ret)
128 return ret;
129
130 p = pmic_get("FSL_PMIC");
131 if (!p)
132 return -ENODEV;
133
134 env_set("fdt_file", "imx53-qsrb.dtb");
135
136 /* Set VDDGP to 1.25V for 1GHz on SW1 */
137 pmic_reg_read(p, REG_SW_0, &val);
138 val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_250V_MC34708;
139 ret = pmic_reg_write(p, REG_SW_0, val);
140 if (ret) {
141 printf("Writing to REG_SW_0 failed: %d\n", ret);
142 return ret;
143 }
144
145 /* Set VCC as 1.30V on SW2 */
146 pmic_reg_read(p, REG_SW_1, &val);
147 val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_300V_MC34708;
148 ret = pmic_reg_write(p, REG_SW_1, val);
149 if (ret) {
150 printf("Writing to REG_SW_1 failed: %d\n", ret);
151 return ret;
152 }
153
154 /* Set global reset timer to 4s */
155 pmic_reg_read(p, REG_POWER_CTL2, &val);
156 val = (val & ~TIMER_MASK_MC34708) | TIMER_4S_MC34708;
157 ret = pmic_reg_write(p, REG_POWER_CTL2, val);
158 if (ret) {
159 printf("Writing to REG_POWER_CTL2 failed: %d\n", ret);
160 return ret;
161 }
162
163 /* Set VUSBSEL and VUSBEN for USB PHY supply*/
164 pmic_reg_read(p, REG_MODE_0, &val);
165 val |= (VUSBSEL_MC34708 | VUSBEN_MC34708);
166 ret = pmic_reg_write(p, REG_MODE_0, val);
167 if (ret) {
168 printf("Writing to REG_MODE_0 failed: %d\n", ret);
169 return ret;
170 }
171
172 /* Set SWBST to 5V in auto mode */
173 val = SWBST_AUTO;
174 ret = pmic_reg_write(p, SWBST_CTRL, val);
175 if (ret) {
176 printf("Writing to SWBST_CTRL failed: %d\n", ret);
177 return ret;
178 }
179
180 return ret;
181 }
182
183 return -1;
184 }
185
clock_1GHz(void)186 static void clock_1GHz(void)
187 {
188 int ret;
189 u32 ref_clk = MXC_HCLK;
190 /*
191 * After increasing voltage to 1.25V, we can switch
192 * CPU clock to 1GHz and DDR to 400MHz safely
193 */
194 ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK);
195 if (ret)
196 printf("CPU: Switch CPU clock to 1GHZ failed\n");
197
198 ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK);
199 ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
200 if (ret)
201 printf("CPU: Switch DDR clock to 400MHz failed\n");
202 }
203
board_early_init_f(void)204 int board_early_init_f(void)
205 {
206 setup_iomux_uart();
207 setup_iomux_lcd();
208
209 return 0;
210 }
211
212 /*
213 * Do not overwrite the console
214 * Use always serial for U-Boot console
215 */
overwrite_console(void)216 int overwrite_console(void)
217 {
218 return 1;
219 }
220
board_init(void)221 int board_init(void)
222 {
223 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
224
225 mxc_set_sata_internal_clock();
226 setup_iomux_i2c();
227
228 return 0;
229 }
230
board_late_init(void)231 int board_late_init(void)
232 {
233 if (!power_init())
234 clock_1GHz();
235
236 return 0;
237 }
238
checkboard(void)239 int checkboard(void)
240 {
241 puts("Board: MX53 LOCO\n");
242
243 return 0;
244 }
245