1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * PCIe driver for Marvell MVEBU SoCs
4 *
5 * Based on Barebox drivers/pci/pci-mvebu.c
6 *
7 * Ported to U-Boot by:
8 * Anton Schubert <anton.schubert@gmx.de>
9 * Stefan Roese <sr@denx.de>
10 */
11
12 #include <common.h>
13 #include <dm.h>
14 #include <log.h>
15 #include <malloc.h>
16 #include <asm/global_data.h>
17 #include <dm/device-internal.h>
18 #include <dm/lists.h>
19 #include <dm/of_access.h>
20 #include <pci.h>
21 #include <asm/io.h>
22 #include <asm/arch/cpu.h>
23 #include <asm/arch/soc.h>
24 #include <linux/bitops.h>
25 #include <linux/errno.h>
26 #include <linux/ioport.h>
27 #include <linux/mbus.h>
28
29 DECLARE_GLOBAL_DATA_PTR;
30
31 /* PCIe unit register offsets */
32 #define SELECT(x, n) ((x >> n) & 1UL)
33
34 #define PCIE_DEV_ID_OFF 0x0000
35 #define PCIE_CMD_OFF 0x0004
36 #define PCIE_DEV_REV_OFF 0x0008
37 #define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3))
38 #define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3))
39 #define PCIE_CAPAB_OFF 0x0060
40 #define PCIE_CTRL_STAT_OFF 0x0068
41 #define PCIE_HEADER_LOG_4_OFF 0x0128
42 #define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4))
43 #define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4))
44 #define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4))
45 #define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4))
46 #define PCIE_WIN5_CTRL_OFF 0x1880
47 #define PCIE_WIN5_BASE_OFF 0x1884
48 #define PCIE_WIN5_REMAP_OFF 0x188c
49 #define PCIE_CONF_ADDR_OFF 0x18f8
50 #define PCIE_CONF_ADDR_EN BIT(31)
51 #define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc))
52 #define PCIE_CONF_BUS(b) (((b) & 0xff) << 16)
53 #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11)
54 #define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8)
55 #define PCIE_CONF_ADDR(dev, reg) \
56 (PCIE_CONF_BUS(PCI_BUS(dev)) | PCIE_CONF_DEV(PCI_DEV(dev)) | \
57 PCIE_CONF_FUNC(PCI_FUNC(dev)) | PCIE_CONF_REG(reg) | \
58 PCIE_CONF_ADDR_EN)
59 #define PCIE_CONF_DATA_OFF 0x18fc
60 #define PCIE_MASK_OFF 0x1910
61 #define PCIE_MASK_ENABLE_INTS (0xf << 24)
62 #define PCIE_CTRL_OFF 0x1a00
63 #define PCIE_CTRL_X1_MODE BIT(0)
64 #define PCIE_STAT_OFF 0x1a04
65 #define PCIE_STAT_BUS (0xff << 8)
66 #define PCIE_STAT_DEV (0x1f << 16)
67 #define PCIE_STAT_LINK_DOWN BIT(0)
68 #define PCIE_DEBUG_CTRL 0x1a60
69 #define PCIE_DEBUG_SOFT_RESET BIT(20)
70
71 struct mvebu_pcie {
72 struct pci_controller hose;
73 void __iomem *base;
74 void __iomem *membase;
75 struct resource mem;
76 void __iomem *iobase;
77 struct resource io;
78 u32 port;
79 u32 lane;
80 int devfn;
81 u32 lane_mask;
82 int first_busno;
83 int local_dev;
84 char name[16];
85 unsigned int mem_target;
86 unsigned int mem_attr;
87 unsigned int io_target;
88 unsigned int io_attr;
89 };
90
91 /*
92 * MVEBU PCIe controller needs MEMORY and I/O BARs to be mapped
93 * into SoCs address space. Each controller will map 128M of MEM
94 * and 64K of I/O space when registered.
95 */
96 static void __iomem *mvebu_pcie_membase = (void __iomem *)MBUS_PCI_MEM_BASE;
97 #define PCIE_MEM_SIZE (128 << 20)
98 static void __iomem *mvebu_pcie_iobase = (void __iomem *)MBUS_PCI_IO_BASE;
99
mvebu_pcie_link_up(struct mvebu_pcie * pcie)100 static inline bool mvebu_pcie_link_up(struct mvebu_pcie *pcie)
101 {
102 u32 val;
103 val = readl(pcie->base + PCIE_STAT_OFF);
104 return !(val & PCIE_STAT_LINK_DOWN);
105 }
106
mvebu_pcie_set_local_bus_nr(struct mvebu_pcie * pcie,int busno)107 static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie *pcie, int busno)
108 {
109 u32 stat;
110
111 stat = readl(pcie->base + PCIE_STAT_OFF);
112 stat &= ~PCIE_STAT_BUS;
113 stat |= busno << 8;
114 writel(stat, pcie->base + PCIE_STAT_OFF);
115 }
116
mvebu_pcie_set_local_dev_nr(struct mvebu_pcie * pcie,int devno)117 static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie *pcie, int devno)
118 {
119 u32 stat;
120
121 stat = readl(pcie->base + PCIE_STAT_OFF);
122 stat &= ~PCIE_STAT_DEV;
123 stat |= devno << 16;
124 writel(stat, pcie->base + PCIE_STAT_OFF);
125 }
126
mvebu_pcie_get_local_bus_nr(struct mvebu_pcie * pcie)127 static int mvebu_pcie_get_local_bus_nr(struct mvebu_pcie *pcie)
128 {
129 u32 stat;
130
131 stat = readl(pcie->base + PCIE_STAT_OFF);
132 return (stat & PCIE_STAT_BUS) >> 8;
133 }
134
mvebu_pcie_get_local_dev_nr(struct mvebu_pcie * pcie)135 static int mvebu_pcie_get_local_dev_nr(struct mvebu_pcie *pcie)
136 {
137 u32 stat;
138
139 stat = readl(pcie->base + PCIE_STAT_OFF);
140 return (stat & PCIE_STAT_DEV) >> 16;
141 }
142
hose_to_pcie(struct pci_controller * hose)143 static inline struct mvebu_pcie *hose_to_pcie(struct pci_controller *hose)
144 {
145 return container_of(hose, struct mvebu_pcie, hose);
146 }
147
mvebu_pcie_valid_addr(struct mvebu_pcie * pcie,pci_dev_t bdf)148 static int mvebu_pcie_valid_addr(struct mvebu_pcie *pcie, pci_dev_t bdf)
149 {
150 /*
151 * There are two devices visible on local bus:
152 * * on slot configured by function mvebu_pcie_set_local_dev_nr()
153 * (by default this register is set to 0) there is a
154 * "Marvell Memory controller", which isn't useful in root complex
155 * mode,
156 * * on all other slots the real PCIe card connected to the PCIe slot.
157 *
158 * We therefore allow access only to the real PCIe card.
159 */
160 if (PCI_BUS(bdf) == pcie->first_busno &&
161 PCI_DEV(bdf) != !pcie->local_dev)
162 return 0;
163
164 return 1;
165 }
166
mvebu_pcie_read_config(const struct udevice * bus,pci_dev_t bdf,uint offset,ulong * valuep,enum pci_size_t size)167 static int mvebu_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
168 uint offset, ulong *valuep,
169 enum pci_size_t size)
170 {
171 struct mvebu_pcie *pcie = dev_get_plat(bus);
172 u32 data;
173
174 debug("PCIE CFG read: (b,d,f)=(%2d,%2d,%2d) ",
175 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
176
177 if (!mvebu_pcie_valid_addr(pcie, bdf)) {
178 debug("- out of range\n");
179 *valuep = pci_get_ff(size);
180 return 0;
181 }
182
183 /* write address */
184 writel(PCIE_CONF_ADDR(bdf, offset), pcie->base + PCIE_CONF_ADDR_OFF);
185
186 /* read data */
187 data = readl(pcie->base + PCIE_CONF_DATA_OFF);
188 debug("(addr,size,val)=(0x%04x, %d, 0x%08x)\n", offset, size, data);
189 *valuep = pci_conv_32_to_size(data, offset, size);
190
191 return 0;
192 }
193
mvebu_pcie_write_config(struct udevice * bus,pci_dev_t bdf,uint offset,ulong value,enum pci_size_t size)194 static int mvebu_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
195 uint offset, ulong value,
196 enum pci_size_t size)
197 {
198 struct mvebu_pcie *pcie = dev_get_plat(bus);
199 u32 data;
200
201 debug("PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ",
202 PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
203 debug("(addr,size,val)=(0x%04x, %d, 0x%08lx)\n", offset, size, value);
204
205 if (!mvebu_pcie_valid_addr(pcie, bdf)) {
206 debug("- out of range\n");
207 return 0;
208 }
209
210 /* write address */
211 writel(PCIE_CONF_ADDR(bdf, offset), pcie->base + PCIE_CONF_ADDR_OFF);
212
213 /* write data */
214 data = pci_conv_size_to_32(0, value, offset, size);
215 writel(data, pcie->base + PCIE_CONF_DATA_OFF);
216
217 return 0;
218 }
219
220 /*
221 * Setup PCIE BARs and Address Decode Wins:
222 * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
223 * WIN[0-3] -> DRAM bank[0-3]
224 */
mvebu_pcie_setup_wins(struct mvebu_pcie * pcie)225 static void mvebu_pcie_setup_wins(struct mvebu_pcie *pcie)
226 {
227 const struct mbus_dram_target_info *dram = mvebu_mbus_dram_info();
228 u32 size;
229 int i;
230
231 /* First, disable and clear BARs and windows. */
232 for (i = 1; i < 3; i++) {
233 writel(0, pcie->base + PCIE_BAR_CTRL_OFF(i));
234 writel(0, pcie->base + PCIE_BAR_LO_OFF(i));
235 writel(0, pcie->base + PCIE_BAR_HI_OFF(i));
236 }
237
238 for (i = 0; i < 5; i++) {
239 writel(0, pcie->base + PCIE_WIN04_CTRL_OFF(i));
240 writel(0, pcie->base + PCIE_WIN04_BASE_OFF(i));
241 writel(0, pcie->base + PCIE_WIN04_REMAP_OFF(i));
242 }
243
244 writel(0, pcie->base + PCIE_WIN5_CTRL_OFF);
245 writel(0, pcie->base + PCIE_WIN5_BASE_OFF);
246 writel(0, pcie->base + PCIE_WIN5_REMAP_OFF);
247
248 /* Setup windows for DDR banks. Count total DDR size on the fly. */
249 size = 0;
250 for (i = 0; i < dram->num_cs; i++) {
251 const struct mbus_dram_window *cs = dram->cs + i;
252
253 writel(cs->base & 0xffff0000,
254 pcie->base + PCIE_WIN04_BASE_OFF(i));
255 writel(0, pcie->base + PCIE_WIN04_REMAP_OFF(i));
256 writel(((cs->size - 1) & 0xffff0000) |
257 (cs->mbus_attr << 8) |
258 (dram->mbus_dram_target_id << 4) | 1,
259 pcie->base + PCIE_WIN04_CTRL_OFF(i));
260
261 size += cs->size;
262 }
263
264 /* Round up 'size' to the nearest power of two. */
265 if ((size & (size - 1)) != 0)
266 size = 1 << fls(size);
267
268 /* Setup BAR[1] to all DRAM banks. */
269 writel(dram->cs[0].base | 0xc, pcie->base + PCIE_BAR_LO_OFF(1));
270 writel(0, pcie->base + PCIE_BAR_HI_OFF(1));
271 writel(((size - 1) & 0xffff0000) | 0x1,
272 pcie->base + PCIE_BAR_CTRL_OFF(1));
273 }
274
mvebu_pcie_probe(struct udevice * dev)275 static int mvebu_pcie_probe(struct udevice *dev)
276 {
277 struct mvebu_pcie *pcie = dev_get_plat(dev);
278 struct udevice *ctlr = pci_get_controller(dev);
279 struct pci_controller *hose = dev_get_uclass_priv(ctlr);
280 int bus = dev_seq(dev);
281 u32 reg;
282
283 debug("%s: PCIe %d.%d - up, base %08x\n", __func__,
284 pcie->port, pcie->lane, (u32)pcie->base);
285
286 /* Read Id info and local bus/dev */
287 debug("direct conf read %08x, local bus %d, local dev %d\n",
288 readl(pcie->base), mvebu_pcie_get_local_bus_nr(pcie),
289 mvebu_pcie_get_local_dev_nr(pcie));
290
291 pcie->first_busno = bus;
292 pcie->local_dev = 1;
293
294 mvebu_pcie_set_local_bus_nr(pcie, bus);
295 mvebu_pcie_set_local_dev_nr(pcie, pcie->local_dev);
296
297 pcie->mem.start = (u32)mvebu_pcie_membase;
298 pcie->mem.end = pcie->mem.start + PCIE_MEM_SIZE - 1;
299 mvebu_pcie_membase += PCIE_MEM_SIZE;
300
301 if (mvebu_mbus_add_window_by_id(pcie->mem_target, pcie->mem_attr,
302 (phys_addr_t)pcie->mem.start,
303 PCIE_MEM_SIZE)) {
304 printf("PCIe unable to add mbus window for mem at %08x+%08x\n",
305 (u32)pcie->mem.start, PCIE_MEM_SIZE);
306 }
307
308 pcie->io.start = (u32)mvebu_pcie_iobase;
309 pcie->io.end = pcie->io.start + MBUS_PCI_IO_SIZE - 1;
310 mvebu_pcie_iobase += MBUS_PCI_IO_SIZE;
311
312 if (mvebu_mbus_add_window_by_id(pcie->io_target, pcie->io_attr,
313 (phys_addr_t)pcie->io.start,
314 MBUS_PCI_IO_SIZE)) {
315 printf("PCIe unable to add mbus window for IO at %08x+%08x\n",
316 (u32)pcie->io.start, MBUS_PCI_IO_SIZE);
317 }
318
319 /* Setup windows and configure host bridge */
320 mvebu_pcie_setup_wins(pcie);
321
322 /* Master + slave enable. */
323 reg = readl(pcie->base + PCIE_CMD_OFF);
324 reg |= PCI_COMMAND_MEMORY;
325 reg |= PCI_COMMAND_IO;
326 reg |= PCI_COMMAND_MASTER;
327 reg |= BIT(10); /* disable interrupts */
328 writel(reg, pcie->base + PCIE_CMD_OFF);
329
330 /* PCI memory space */
331 pci_set_region(hose->regions + 0, pcie->mem.start,
332 pcie->mem.start, PCIE_MEM_SIZE, PCI_REGION_MEM);
333 pci_set_region(hose->regions + 1,
334 0, 0,
335 gd->ram_size,
336 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
337 pci_set_region(hose->regions + 2, pcie->io.start,
338 pcie->io.start, MBUS_PCI_IO_SIZE, PCI_REGION_IO);
339 hose->region_count = 3;
340
341 /* Set BAR0 to internal registers */
342 writel(SOC_REGS_PHY_BASE, pcie->base + PCIE_BAR_LO_OFF(0));
343 writel(0, pcie->base + PCIE_BAR_HI_OFF(0));
344
345 return 0;
346 }
347
mvebu_pcie_port_parse_dt(ofnode node,struct mvebu_pcie * pcie)348 static int mvebu_pcie_port_parse_dt(ofnode node, struct mvebu_pcie *pcie)
349 {
350 const u32 *addr;
351 int len;
352
353 addr = ofnode_get_property(node, "assigned-addresses", &len);
354 if (!addr) {
355 pr_err("property \"assigned-addresses\" not found");
356 return -FDT_ERR_NOTFOUND;
357 }
358
359 pcie->base = (void *)(fdt32_to_cpu(addr[2]) + SOC_REGS_PHY_BASE);
360
361 return 0;
362 }
363
364 #define DT_FLAGS_TO_TYPE(flags) (((flags) >> 24) & 0x03)
365 #define DT_TYPE_IO 0x1
366 #define DT_TYPE_MEM32 0x2
367 #define DT_CPUADDR_TO_TARGET(cpuaddr) (((cpuaddr) >> 56) & 0xFF)
368 #define DT_CPUADDR_TO_ATTR(cpuaddr) (((cpuaddr) >> 48) & 0xFF)
369
mvebu_get_tgt_attr(ofnode node,int devfn,unsigned long type,unsigned int * tgt,unsigned int * attr)370 static int mvebu_get_tgt_attr(ofnode node, int devfn,
371 unsigned long type,
372 unsigned int *tgt,
373 unsigned int *attr)
374 {
375 const int na = 3, ns = 2;
376 const __be32 *range;
377 int rlen, nranges, rangesz, pna, i;
378
379 *tgt = -1;
380 *attr = -1;
381
382 range = ofnode_get_property(node, "ranges", &rlen);
383 if (!range)
384 return -EINVAL;
385
386 /*
387 * Linux uses of_n_addr_cells() to get the number of address cells
388 * here. Currently this function is only available in U-Boot when
389 * CONFIG_OF_LIVE is enabled. Until this is enabled for MVEBU in
390 * general, lets't hardcode the "pna" value in the U-Boot code.
391 */
392 pna = 2; /* hardcoded for now because of lack of of_n_addr_cells() */
393 rangesz = pna + na + ns;
394 nranges = rlen / sizeof(__be32) / rangesz;
395
396 for (i = 0; i < nranges; i++, range += rangesz) {
397 u32 flags = of_read_number(range, 1);
398 u32 slot = of_read_number(range + 1, 1);
399 u64 cpuaddr = of_read_number(range + na, pna);
400 unsigned long rtype;
401
402 if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_IO)
403 rtype = IORESOURCE_IO;
404 else if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_MEM32)
405 rtype = IORESOURCE_MEM;
406 else
407 continue;
408
409 /*
410 * The Linux code used PCI_SLOT() here, which expects devfn
411 * in bits 7..0. PCI_DEV() in U-Boot is similar to PCI_SLOT(),
412 * only expects devfn in 15..8, where its saved in this driver.
413 */
414 if (slot == PCI_DEV(devfn) && type == rtype) {
415 *tgt = DT_CPUADDR_TO_TARGET(cpuaddr);
416 *attr = DT_CPUADDR_TO_ATTR(cpuaddr);
417 return 0;
418 }
419 }
420
421 return -ENOENT;
422 }
423
mvebu_pcie_of_to_plat(struct udevice * dev)424 static int mvebu_pcie_of_to_plat(struct udevice *dev)
425 {
426 struct mvebu_pcie *pcie = dev_get_plat(dev);
427 int ret = 0;
428
429 /* Get port number, lane number and memory target / attr */
430 if (ofnode_read_u32(dev_ofnode(dev), "marvell,pcie-port",
431 &pcie->port)) {
432 ret = -ENODEV;
433 goto err;
434 }
435
436 if (ofnode_read_u32(dev_ofnode(dev), "marvell,pcie-lane", &pcie->lane))
437 pcie->lane = 0;
438
439 sprintf(pcie->name, "pcie%d.%d", pcie->port, pcie->lane);
440
441 /* pci_get_devfn() returns devfn in bits 15..8, see PCI_DEV usage */
442 pcie->devfn = pci_get_devfn(dev);
443 if (pcie->devfn < 0) {
444 ret = -ENODEV;
445 goto err;
446 }
447
448 ret = mvebu_get_tgt_attr(dev_ofnode(dev->parent), pcie->devfn,
449 IORESOURCE_MEM,
450 &pcie->mem_target, &pcie->mem_attr);
451 if (ret < 0) {
452 printf("%s: cannot get tgt/attr for mem window\n", pcie->name);
453 goto err;
454 }
455
456 ret = mvebu_get_tgt_attr(dev_ofnode(dev->parent), pcie->devfn,
457 IORESOURCE_IO,
458 &pcie->io_target, &pcie->io_attr);
459 if (ret < 0) {
460 printf("%s: cannot get tgt/attr for IO window\n", pcie->name);
461 goto err;
462 }
463
464 /* Parse PCIe controller register base from DT */
465 ret = mvebu_pcie_port_parse_dt(dev_ofnode(dev), pcie);
466 if (ret < 0)
467 goto err;
468
469 /* Check link and skip ports that have no link */
470 if (!mvebu_pcie_link_up(pcie)) {
471 debug("%s: %s - down\n", __func__, pcie->name);
472 ret = -ENODEV;
473 goto err;
474 }
475
476 return 0;
477
478 err:
479 return ret;
480 }
481
482 static const struct dm_pci_ops mvebu_pcie_ops = {
483 .read_config = mvebu_pcie_read_config,
484 .write_config = mvebu_pcie_write_config,
485 };
486
487 static struct driver pcie_mvebu_drv = {
488 .name = "pcie_mvebu",
489 .id = UCLASS_PCI,
490 .ops = &mvebu_pcie_ops,
491 .probe = mvebu_pcie_probe,
492 .of_to_plat = mvebu_pcie_of_to_plat,
493 .plat_auto = sizeof(struct mvebu_pcie),
494 };
495
496 /*
497 * Use a MISC device to bind the n instances (child nodes) of the
498 * PCIe base controller in UCLASS_PCI.
499 */
mvebu_pcie_bind(struct udevice * parent)500 static int mvebu_pcie_bind(struct udevice *parent)
501 {
502 struct mvebu_pcie *pcie;
503 struct uclass_driver *drv;
504 struct udevice *dev;
505 ofnode subnode;
506
507 /* Lookup eth driver */
508 drv = lists_uclass_lookup(UCLASS_PCI);
509 if (!drv) {
510 puts("Cannot find PCI driver\n");
511 return -ENOENT;
512 }
513
514 ofnode_for_each_subnode(subnode, dev_ofnode(parent)) {
515 if (!ofnode_is_available(subnode))
516 continue;
517
518 pcie = calloc(1, sizeof(*pcie));
519 if (!pcie)
520 return -ENOMEM;
521
522 /* Create child device UCLASS_PCI and bind it */
523 device_bind(parent, &pcie_mvebu_drv, pcie->name, pcie, subnode,
524 &dev);
525 }
526
527 return 0;
528 }
529
530 static const struct udevice_id mvebu_pcie_ids[] = {
531 { .compatible = "marvell,armada-xp-pcie" },
532 { .compatible = "marvell,armada-370-pcie" },
533 { }
534 };
535
536 U_BOOT_DRIVER(pcie_mvebu_base) = {
537 .name = "pcie_mvebu_base",
538 .id = UCLASS_MISC,
539 .of_match = mvebu_pcie_ids,
540 .bind = mvebu_pcie_bind,
541 };
542