1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2011
4 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
5 *
6 * Copyright (C) 2012 Stefan Roese <sr@denx.de>
7 */
8
9 #include <common.h>
10 #include <init.h>
11 #include <spl.h>
12 #include <version.h>
13 #include <asm/io.h>
14 #include <asm/ptrace.h>
15 #include <asm/arch/hardware.h>
16 #include <asm/arch/spr_defs.h>
17 #include <asm/arch/spr_misc.h>
18 #include <asm/arch/spr_syscntl.h>
19 #include <linux/mtd/st_smi.h>
20
21 /* Reserve some space to store the BootROM's stack pointer during SPL operation.
22 * The BSS cannot be used for this purpose because it will be zeroed after
23 * having stored the pointer, so force the location to the data section.
24 */
25 u32 bootrom_stash_sp __section(".data");
26
ddr_clock_init(void)27 static void ddr_clock_init(void)
28 {
29 struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
30 u32 clkenb, ddrpll;
31
32 clkenb = readl(&misc_p->periph1_clken);
33 clkenb &= ~PERIPH_MPMCMSK;
34 clkenb |= PERIPH_MPMC_WE;
35
36 /* Intentionally done twice */
37 writel(clkenb, &misc_p->periph1_clken);
38 writel(clkenb, &misc_p->periph1_clken);
39
40 ddrpll = readl(&misc_p->pll_ctr_reg);
41 ddrpll &= ~MEM_CLK_SEL_MSK;
42 #if (CONFIG_DDR_HCLK)
43 ddrpll |= MEM_CLK_HCLK;
44 #elif (CONFIG_DDR_2HCLK)
45 ddrpll |= MEM_CLK_2HCLK;
46 #elif (CONFIG_DDR_PLL2)
47 ddrpll |= MEM_CLK_PLL2;
48 #else
49 #error "please define one of CONFIG_DDR_(HCLK|2HCLK|PLL2)"
50 #endif
51 writel(ddrpll, &misc_p->pll_ctr_reg);
52
53 writel(readl(&misc_p->periph1_clken) | PERIPH_MPMC_EN,
54 &misc_p->periph1_clken);
55 }
56
mpmc_init_values(void)57 static void mpmc_init_values(void)
58 {
59 u32 i;
60 u32 *mpmc_reg_p = (u32 *)CONFIG_SPEAR_MPMCBASE;
61 u32 *mpmc_val_p = &mpmc_conf_vals[0];
62
63 for (i = 0; i < CONFIG_SPEAR_MPMCREGS; i++, mpmc_reg_p++, mpmc_val_p++)
64 writel(*mpmc_val_p, mpmc_reg_p);
65
66 mpmc_reg_p = (u32 *)CONFIG_SPEAR_MPMCBASE;
67
68 /*
69 * MPMC controller start
70 * MPMC waiting for DLLLOCKREG high
71 */
72 writel(0x01000100, &mpmc_reg_p[7]);
73
74 while (!(readl(&mpmc_reg_p[3]) & 0x10000))
75 ;
76 }
77
mpmc_init(void)78 static void mpmc_init(void)
79 {
80 /* Clock related settings for DDR */
81 ddr_clock_init();
82
83 /*
84 * DDR pad register bits are different for different SoCs
85 * Compensation values are also handled separately
86 */
87 plat_ddr_init();
88
89 /* Initialize mpmc register values */
90 mpmc_init_values();
91 }
92
pll_init(void)93 static void pll_init(void)
94 {
95 struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
96
97 /* Initialize PLLs */
98 writel(FREQ_332, &misc_p->pll1_frq);
99 writel(0x1C0A, &misc_p->pll1_cntl);
100 writel(0x1C0E, &misc_p->pll1_cntl);
101 writel(0x1C06, &misc_p->pll1_cntl);
102 writel(0x1C0E, &misc_p->pll1_cntl);
103
104 writel(FREQ_332, &misc_p->pll2_frq);
105 writel(0x1C0A, &misc_p->pll2_cntl);
106 writel(0x1C0E, &misc_p->pll2_cntl);
107 writel(0x1C06, &misc_p->pll2_cntl);
108 writel(0x1C0E, &misc_p->pll2_cntl);
109
110 /* wait for pll locks */
111 while (!(readl(&misc_p->pll1_cntl) & 0x1))
112 ;
113 while (!(readl(&misc_p->pll2_cntl) & 0x1))
114 ;
115 }
116
mac_init(void)117 static void mac_init(void)
118 {
119 struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
120
121 writel(readl(&misc_p->periph1_clken) & (~PERIPH_GMAC),
122 &misc_p->periph1_clken);
123
124 writel(SYNTH23, &misc_p->gmac_synth_clk);
125
126 switch (get_socrev()) {
127 case SOC_SPEAR600_AA:
128 case SOC_SPEAR600_AB:
129 case SOC_SPEAR600_BA:
130 case SOC_SPEAR600_BB:
131 case SOC_SPEAR600_BC:
132 case SOC_SPEAR600_BD:
133 writel(0x0, &misc_p->gmac_ctr_reg);
134 break;
135
136 case SOC_SPEAR300:
137 case SOC_SPEAR310:
138 case SOC_SPEAR320:
139 writel(0x4, &misc_p->gmac_ctr_reg);
140 break;
141 }
142
143 writel(readl(&misc_p->periph1_clken) | PERIPH_GMAC,
144 &misc_p->periph1_clken);
145
146 writel(readl(&misc_p->periph1_rst) | PERIPH_GMAC,
147 &misc_p->periph1_rst);
148 writel(readl(&misc_p->periph1_rst) & (~PERIPH_GMAC),
149 &misc_p->periph1_rst);
150 }
151
sys_init(void)152 static void sys_init(void)
153 {
154 struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
155 struct syscntl_regs *syscntl_p =
156 (struct syscntl_regs *)CONFIG_SPEAR_SYSCNTLBASE;
157
158 /* Set system state to SLOW */
159 writel(SLOW, &syscntl_p->scctrl);
160 writel(PLL_TIM << 3, &syscntl_p->scpllctrl);
161
162 /* Initialize PLLs */
163 pll_init();
164
165 /*
166 * Ethernet configuration
167 * To be done only if the tftp boot is not selected already
168 * Boot code ensures the correct configuration in tftp booting
169 */
170 if (!tftp_boot_selected())
171 mac_init();
172
173 writel(RTC_DISABLE | PLLTIMEEN, &misc_p->periph_clk_cfg);
174 writel(0x555, &misc_p->amba_clk_cfg);
175
176 writel(NORMAL, &syscntl_p->scctrl);
177
178 /* Wait for system to switch to normal mode */
179 while (((readl(&syscntl_p->scctrl) >> MODE_SHIFT) & MODE_MASK)
180 != NORMAL)
181 ;
182 }
183
184 /*
185 * get_socrev
186 *
187 * Get SoC Revision.
188 * @return SOC_SPEARXXX
189 */
get_socrev(void)190 int get_socrev(void)
191 {
192 #if defined(CONFIG_SPEAR600)
193 struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
194 u32 soc_id = readl(&misc_p->soc_core_id);
195 u32 pri_socid = (soc_id >> SOC_PRI_SHFT) & 0xFF;
196 u32 sec_socid = (soc_id >> SOC_SEC_SHFT) & 0xFF;
197
198 if ((pri_socid == 'B') && (sec_socid == 'B'))
199 return SOC_SPEAR600_BB;
200 else if ((pri_socid == 'B') && (sec_socid == 'C'))
201 return SOC_SPEAR600_BC;
202 else if ((pri_socid == 'B') && (sec_socid == 'D'))
203 return SOC_SPEAR600_BD;
204 else if (soc_id == 0)
205 return SOC_SPEAR600_BA;
206 else
207 return SOC_SPEAR_NA;
208 #elif defined(CONFIG_SPEAR300)
209 return SOC_SPEAR300;
210 #elif defined(CONFIG_SPEAR310)
211 return SOC_SPEAR310;
212 #elif defined(CONFIG_SPEAR320)
213 return SOC_SPEAR320;
214 #endif
215 }
216
217 /*
218 * SNOR (Serial NOR flash) related functions
219 */
snor_init(void)220 static void snor_init(void)
221 {
222 struct smi_regs *const smicntl =
223 (struct smi_regs * const)CONFIG_SYS_SMI_BASE;
224
225 /* Setting the fast mode values. SMI working at 166/4 = 41.5 MHz */
226 writel(HOLD1 | FAST_MODE | BANK_EN | DSEL_TIME | PRESCAL4,
227 &smicntl->smi_cr1);
228 }
229
spl_boot_device(void)230 u32 spl_boot_device(void)
231 {
232 u32 mode = 0;
233
234 if (usb_boot_selected()) {
235 mode = BOOT_DEVICE_BOOTROM;
236 } else if (snor_boot_selected()) {
237 /* SNOR-SMI initialization */
238 snor_init();
239
240 mode = BOOT_DEVICE_NOR;
241 }
242
243 return mode;
244 }
245
board_boot_order(u32 * spl_boot_list)246 void board_boot_order(u32 *spl_boot_list)
247 {
248 spl_boot_list[0] = spl_boot_device();
249
250 /*
251 * If the main boot device (eg. NOR) is empty, try to jump back into the
252 * BootROM for USB boot process.
253 */
254 if (USB_BOOT_SUPPORTED)
255 spl_boot_list[1] = BOOT_DEVICE_BOOTROM;
256 }
257
board_init_f(ulong dummy)258 void board_init_f(ulong dummy)
259 {
260 struct misc_regs *misc_p = (struct misc_regs *)CONFIG_SPEAR_MISCBASE;
261
262 /* Initialize PLLs */
263 sys_init();
264
265 preloader_console_init();
266 arch_cpu_init();
267
268 /* Enable IPs (release reset) */
269 writel(PERIPH_RST_ALL, &misc_p->periph1_rst);
270
271 /* Initialize MPMC */
272 puts("Configure DDR\n");
273 mpmc_init();
274 spear_late_init();
275 }
276
277 /*
278 * In a few cases (Ethernet, UART or USB boot, we might want to go back into the
279 * BootROM code right after having initialized a few components like the DRAM).
280 * The following function is called from SPL common code (board_init_r).
281 */
board_return_to_bootrom(struct spl_image_info * spl_image,struct spl_boot_device * bootdev)282 int board_return_to_bootrom(struct spl_image_info *spl_image,
283 struct spl_boot_device *bootdev)
284 {
285 /*
286 * Retrieve the BootROM's stack pointer and jump back to the start of
287 * the SPL, where we can easily branch back into the BootROM. Don't do
288 * it right here because SPL might be compiled in Thumb mode while the
289 * BootROM expects ARM mode.
290 */
291 asm volatile ("ldr r0, =bootrom_stash_sp;"
292 "ldr r0, [r0];"
293 "mov sp, r0;"
294 #if defined(CONFIG_SPL_SYS_THUMB_BUILD)
295 "blx back_to_bootrom;"
296 #else
297 "bl back_to_bootrom;"
298 #endif
299 );
300
301 return 0;
302 }
303