1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2009 4 * Marvell Semiconductor <www.marvell.com> 5 * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 6 * 7 * Derived from drivers/spi/mpc8xxx_spi.c 8 */ 9 10 #ifndef __KW_SPI_H__ 11 #define __KW_SPI_H__ 12 13 /* SPI Registers on kirkwood SOC */ 14 struct kwspi_registers { 15 u32 ctrl; /* 0x10600 */ 16 u32 cfg; /* 0x10604 */ 17 u32 dout; /* 0x10608 */ 18 u32 din; /* 0x1060c */ 19 u32 irq_cause; /* 0x10610 */ 20 u32 irq_mask; /* 0x10614 */ 21 u32 timing1; /* 0x10618 */ 22 u32 timing2; /* 0x1061c */ 23 u32 dw_cfg; /* 0x10620 - Direct Write Configuration */ 24 }; 25 26 /* Control Register */ 27 #define KWSPI_CSN_ACT (1 << 0) /* Activates serial memory interface */ 28 #define KWSPI_SMEMRDY (1 << 1) /* SerMem Data xfer ready */ 29 #define KWSPI_CS_SHIFT 2 /* chip select shift */ 30 #define KWSPI_CS_MASK 0x7 /* chip select mask */ 31 32 /* Configuration Register */ 33 #define KWSPI_CLKPRESCL_MASK 0x1f 34 #define KWSPI_CLKPRESCL_MIN 0x12 35 #define KWSPI_XFERLEN_1BYTE 0 36 #define KWSPI_XFERLEN_2BYTE (1 << 5) 37 #define KWSPI_XFERLEN_MASK (1 << 5) 38 #define KWSPI_ADRLEN_1BYTE 0 39 #define KWSPI_ADRLEN_2BYTE (1 << 8) 40 #define KWSPI_ADRLEN_3BYTE (2 << 8) 41 #define KWSPI_ADRLEN_4BYTE (3 << 8) 42 #define KWSPI_ADRLEN_MASK (3 << 8) 43 #define KWSPI_CPOL (1 << 11) 44 #define KWSPI_CPHA (1 << 12) 45 #define KWSPI_TXLSBF (1 << 13) 46 #define KWSPI_RXLSBF (1 << 14) 47 48 /* Timing Parameters 1 Register */ 49 #define KW_SPI_TMISO_SAMPLE_OFFSET 6 50 #define KW_SPI_TMISO_SAMPLE_MASK (0x3 << KW_SPI_TMISO_SAMPLE_OFFSET) 51 #define KW_SPI_TMISO_SAMPLE_1 (1 << KW_SPI_TMISO_SAMPLE_OFFSET) 52 #define KW_SPI_TMISO_SAMPLE_2 (2 << KW_SPI_TMISO_SAMPLE_OFFSET) 53 54 #define KWSPI_IRQUNMASK 1 /* unmask SPI interrupt */ 55 #define KWSPI_IRQMASK 0 /* mask SPI interrupt */ 56 #define KWSPI_SMEMRDIRQ 1 /* SerMem data xfer ready irq */ 57 58 #define KWSPI_TIMEOUT 10000 59 60 #endif /* __KW_SPI_H__ */ 61