1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * J721E: SoC specific initialization
4 *
5 * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/
6 * Lokesh Vutla <lokeshvutla@ti.com>
7 */
8
9 #include <common.h>
10 #include <init.h>
11 #include <spl.h>
12 #include <asm/io.h>
13 #include <asm/armv7_mpu.h>
14 #include <asm/arch/hardware.h>
15 #include <asm/arch/sysfw-loader.h>
16 #include "common.h"
17 #include <asm/arch/sys_proto.h>
18 #include <linux/soc/ti/ti_sci_protocol.h>
19 #include <dm.h>
20 #include <dm/uclass-internal.h>
21 #include <dm/pinctrl.h>
22 #include <mmc.h>
23 #include <remoteproc.h>
24
25 #ifdef CONFIG_SPL_BUILD
26 #ifdef CONFIG_K3_LOAD_SYSFW
27 #ifdef CONFIG_TI_SECURE_DEVICE
28 struct fwl_data cbass_hc_cfg0_fwls[] = {
29 { "PCIE0_CFG", 2560, 8 },
30 { "PCIE1_CFG", 2561, 8 },
31 { "USB3SS0_CORE", 2568, 4 },
32 { "USB3SS1_CORE", 2570, 4 },
33 { "EMMC8SS0_CFG", 2576, 4 },
34 { "UFS_HCI0_CFG", 2580, 4 },
35 { "SERDES0", 2584, 1 },
36 { "SERDES1", 2585, 1 },
37 }, cbass_hc0_fwls[] = {
38 { "PCIE0_HP", 2528, 24 },
39 { "PCIE0_LP", 2529, 24 },
40 { "PCIE1_HP", 2530, 24 },
41 { "PCIE1_LP", 2531, 24 },
42 }, cbass_rc_cfg0_fwls[] = {
43 { "EMMCSD4SS0_CFG", 2380, 4 },
44 }, cbass_rc0_fwls[] = {
45 { "GPMC0", 2310, 8 },
46 }, infra_cbass0_fwls[] = {
47 { "PLL_MMR0", 8, 26 },
48 { "CTRL_MMR0", 9, 16 },
49 }, mcu_cbass0_fwls[] = {
50 { "MCU_R5FSS0_CORE0", 1024, 4 },
51 { "MCU_R5FSS0_CORE0_CFG", 1025, 2 },
52 { "MCU_R5FSS0_CORE1", 1028, 4 },
53 { "MCU_FSS0_CFG", 1032, 12 },
54 { "MCU_FSS0_S1", 1033, 8 },
55 { "MCU_FSS0_S0", 1036, 8 },
56 { "MCU_PSROM49152X32", 1048, 1 },
57 { "MCU_MSRAM128KX64", 1050, 8 },
58 { "MCU_CTRL_MMR0", 1200, 8 },
59 { "MCU_PLL_MMR0", 1201, 3 },
60 { "MCU_CPSW0", 1220, 2 },
61 }, wkup_cbass0_fwls[] = {
62 { "WKUP_CTRL_MMR0", 131, 16 },
63 };
64 #endif
65 #endif
66
ctrl_mmr_unlock(void)67 static void ctrl_mmr_unlock(void)
68 {
69 /* Unlock all WKUP_CTRL_MMR0 module registers */
70 mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
71 mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
72 mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
73 mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
74 mmr_unlock(WKUP_CTRL_MMR0_BASE, 4);
75 mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
76 mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
77
78 /* Unlock all MCU_CTRL_MMR0 module registers */
79 mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
80 mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
81 mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
82 mmr_unlock(MCU_CTRL_MMR0_BASE, 3);
83 mmr_unlock(MCU_CTRL_MMR0_BASE, 4);
84
85 /* Unlock all CTRL_MMR0 module registers */
86 mmr_unlock(CTRL_MMR0_BASE, 0);
87 mmr_unlock(CTRL_MMR0_BASE, 1);
88 mmr_unlock(CTRL_MMR0_BASE, 2);
89 mmr_unlock(CTRL_MMR0_BASE, 3);
90 mmr_unlock(CTRL_MMR0_BASE, 5);
91 if (soc_is_j721e())
92 mmr_unlock(CTRL_MMR0_BASE, 6);
93 mmr_unlock(CTRL_MMR0_BASE, 7);
94 }
95
96 #if defined(CONFIG_K3_LOAD_SYSFW)
k3_mmc_stop_clock(void)97 void k3_mmc_stop_clock(void)
98 {
99 if (spl_boot_device() == BOOT_DEVICE_MMC1) {
100 struct mmc *mmc = find_mmc_device(0);
101
102 if (!mmc)
103 return;
104
105 mmc->saved_clock = mmc->clock;
106 mmc_set_clock(mmc, 0, true);
107 }
108 }
109
k3_mmc_restart_clock(void)110 void k3_mmc_restart_clock(void)
111 {
112 if (spl_boot_device() == BOOT_DEVICE_MMC1) {
113 struct mmc *mmc = find_mmc_device(0);
114
115 if (!mmc)
116 return;
117
118 mmc_set_clock(mmc, mmc->saved_clock, false);
119 }
120 }
121 #endif
122
123 /*
124 * This uninitialized global variable would normal end up in the .bss section,
125 * but the .bss is cleared between writing and reading this variable, so move
126 * it to the .data section.
127 */
128 u32 bootindex __section(".data");
129 static struct rom_extended_boot_data bootdata __section(".data");
130
store_boot_info_from_rom(void)131 static void store_boot_info_from_rom(void)
132 {
133 bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
134 memcpy(&bootdata, (uintptr_t *)ROM_ENTENDED_BOOT_DATA_INFO,
135 sizeof(struct rom_extended_boot_data));
136 }
137
board_init_f(ulong dummy)138 void board_init_f(ulong dummy)
139 {
140 #if defined(CONFIG_K3_J721E_DDRSS) || defined(CONFIG_K3_LOAD_SYSFW)
141 struct udevice *dev;
142 int ret;
143 #endif
144 /*
145 * Cannot delay this further as there is a chance that
146 * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
147 */
148 store_boot_info_from_rom();
149
150 /* Make all control module registers accessible */
151 ctrl_mmr_unlock();
152
153 #ifdef CONFIG_CPU_V7R
154 disable_linefill_optimization();
155 setup_k3_mpu_regions();
156 #endif
157
158 /* Init DM early */
159 spl_early_init();
160
161 #ifdef CONFIG_K3_LOAD_SYSFW
162 /*
163 * Process pinctrl for the serial0 a.k.a. MCU_UART0 module and continue
164 * regardless of the result of pinctrl. Do this without probing the
165 * device, but instead by searching the device that would request the
166 * given sequence number if probed. The UART will be used by the system
167 * firmware (SYSFW) image for various purposes and SYSFW depends on us
168 * to initialize its pin settings.
169 */
170 ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, &dev);
171 if (!ret)
172 pinctrl_select_state(dev, "default");
173
174 /*
175 * Load, start up, and configure system controller firmware. Provide
176 * the U-Boot console init function to the SYSFW post-PM configuration
177 * callback hook, effectively switching on (or over) the console
178 * output.
179 */
180 k3_sysfw_loader(is_rom_loaded_sysfw(&bootdata),
181 k3_mmc_stop_clock, k3_mmc_restart_clock);
182
183 /* Prepare console output */
184 preloader_console_init();
185
186 /* Disable ROM configured firewalls right after loading sysfw */
187 #ifdef CONFIG_TI_SECURE_DEVICE
188 remove_fwl_configs(cbass_hc_cfg0_fwls, ARRAY_SIZE(cbass_hc_cfg0_fwls));
189 remove_fwl_configs(cbass_hc0_fwls, ARRAY_SIZE(cbass_hc0_fwls));
190 remove_fwl_configs(cbass_rc_cfg0_fwls, ARRAY_SIZE(cbass_rc_cfg0_fwls));
191 remove_fwl_configs(cbass_rc0_fwls, ARRAY_SIZE(cbass_rc0_fwls));
192 remove_fwl_configs(infra_cbass0_fwls, ARRAY_SIZE(infra_cbass0_fwls));
193 remove_fwl_configs(mcu_cbass0_fwls, ARRAY_SIZE(mcu_cbass0_fwls));
194 remove_fwl_configs(wkup_cbass0_fwls, ARRAY_SIZE(wkup_cbass0_fwls));
195 #endif
196 #else
197 /* Prepare console output */
198 preloader_console_init();
199 #endif
200
201 /* Output System Firmware version info */
202 k3_sysfw_print_ver();
203
204 /* Perform EEPROM-based board detection */
205 if (IS_ENABLED(CONFIG_TI_I2C_BOARD_DETECT))
206 do_board_detect();
207
208 #if defined(CONFIG_CPU_V7R) && defined(CONFIG_K3_AVS0)
209 ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(k3_avs),
210 &dev);
211 if (ret)
212 printf("AVS init failed: %d\n", ret);
213 #endif
214
215 #if defined(CONFIG_K3_J721E_DDRSS)
216 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
217 if (ret)
218 panic("DRAM init failed: %d\n", ret);
219 #endif
220 spl_enable_dcache();
221 }
222
spl_mmc_boot_mode(const u32 boot_device)223 u32 spl_mmc_boot_mode(const u32 boot_device)
224 {
225 switch (boot_device) {
226 case BOOT_DEVICE_MMC1:
227 return MMCSD_MODE_EMMCBOOT;
228 case BOOT_DEVICE_MMC2:
229 return MMCSD_MODE_FS;
230 default:
231 return MMCSD_MODE_RAW;
232 }
233 }
234
__get_backup_bootmedia(u32 main_devstat)235 static u32 __get_backup_bootmedia(u32 main_devstat)
236 {
237 u32 bkup_boot = (main_devstat & MAIN_DEVSTAT_BKUP_BOOTMODE_MASK) >>
238 MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT;
239
240 switch (bkup_boot) {
241 case BACKUP_BOOT_DEVICE_USB:
242 return BOOT_DEVICE_DFU;
243 case BACKUP_BOOT_DEVICE_UART:
244 return BOOT_DEVICE_UART;
245 case BACKUP_BOOT_DEVICE_ETHERNET:
246 return BOOT_DEVICE_ETHERNET;
247 case BACKUP_BOOT_DEVICE_MMC2:
248 {
249 u32 port = (main_devstat & MAIN_DEVSTAT_BKUP_MMC_PORT_MASK) >>
250 MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT;
251 if (port == 0x0)
252 return BOOT_DEVICE_MMC1;
253 return BOOT_DEVICE_MMC2;
254 }
255 case BACKUP_BOOT_DEVICE_SPI:
256 return BOOT_DEVICE_SPI;
257 case BACKUP_BOOT_DEVICE_I2C:
258 return BOOT_DEVICE_I2C;
259 }
260
261 return BOOT_DEVICE_RAM;
262 }
263
__get_primary_bootmedia(u32 main_devstat,u32 wkup_devstat)264 static u32 __get_primary_bootmedia(u32 main_devstat, u32 wkup_devstat)
265 {
266
267 u32 bootmode = (wkup_devstat & WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
268 WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT;
269
270 bootmode |= (main_devstat & MAIN_DEVSTAT_BOOT_MODE_B_MASK) <<
271 BOOT_MODE_B_SHIFT;
272
273 if (bootmode == BOOT_DEVICE_OSPI || bootmode == BOOT_DEVICE_QSPI)
274 bootmode = BOOT_DEVICE_SPI;
275
276 if (bootmode == BOOT_DEVICE_MMC2) {
277 u32 port = (main_devstat &
278 MAIN_DEVSTAT_PRIM_BOOTMODE_MMC_PORT_MASK) >>
279 MAIN_DEVSTAT_PRIM_BOOTMODE_PORT_SHIFT;
280 if (port == 0x0)
281 bootmode = BOOT_DEVICE_MMC1;
282 }
283
284 return bootmode;
285 }
286
spl_boot_device(void)287 u32 spl_boot_device(void)
288 {
289 u32 wkup_devstat = readl(CTRLMMR_WKUP_DEVSTAT);
290 u32 main_devstat;
291
292 if (wkup_devstat & WKUP_DEVSTAT_MCU_OMLY_MASK) {
293 printf("ERROR: MCU only boot is not yet supported\n");
294 return BOOT_DEVICE_RAM;
295 }
296
297 /* MAIN CTRL MMR can only be read if MCU ONLY is 0 */
298 main_devstat = readl(CTRLMMR_MAIN_DEVSTAT);
299
300 if (bootindex == K3_PRIMARY_BOOTMODE)
301 return __get_primary_bootmedia(main_devstat, wkup_devstat);
302 else
303 return __get_backup_bootmedia(main_devstat);
304 }
305 #endif
306
307 #ifdef CONFIG_SYS_K3_SPL_ATF
308
309 #define J721E_DEV_MCU_RTI0 262
310 #define J721E_DEV_MCU_RTI1 263
311 #define J721E_DEV_MCU_ARMSS0_CPU0 250
312 #define J721E_DEV_MCU_ARMSS0_CPU1 251
313
release_resources_for_core_shutdown(void)314 void release_resources_for_core_shutdown(void)
315 {
316 struct ti_sci_handle *ti_sci;
317 struct ti_sci_dev_ops *dev_ops;
318 struct ti_sci_proc_ops *proc_ops;
319 int ret;
320 u32 i;
321
322 const u32 put_device_ids[] = {
323 J721E_DEV_MCU_RTI0,
324 J721E_DEV_MCU_RTI1,
325 };
326
327 ti_sci = get_ti_sci_handle();
328 dev_ops = &ti_sci->ops.dev_ops;
329 proc_ops = &ti_sci->ops.proc_ops;
330
331 /* Iterate through list of devices to put (shutdown) */
332 for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) {
333 u32 id = put_device_ids[i];
334
335 ret = dev_ops->put_device(ti_sci, id);
336 if (ret)
337 panic("Failed to put device %u (%d)\n", id, ret);
338 }
339
340 const u32 put_core_ids[] = {
341 J721E_DEV_MCU_ARMSS0_CPU1,
342 J721E_DEV_MCU_ARMSS0_CPU0, /* Handle CPU0 after CPU1 */
343 };
344
345 /* Iterate through list of cores to put (shutdown) */
346 for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) {
347 u32 id = put_core_ids[i];
348
349 /*
350 * Queue up the core shutdown request. Note that this call
351 * needs to be followed up by an actual invocation of an WFE
352 * or WFI CPU instruction.
353 */
354 ret = proc_ops->proc_shutdown_no_wait(ti_sci, id);
355 if (ret)
356 panic("Failed sending core %u shutdown message (%d)\n",
357 id, ret);
358 }
359 }
360 #endif
361
362 #ifdef CONFIG_SYS_K3_SPL_ATF
start_non_linux_remote_cores(void)363 void start_non_linux_remote_cores(void)
364 {
365 int size = 0, ret;
366 u32 loadaddr = 0;
367
368 if (!soc_is_j721e())
369 return;
370
371 size = load_firmware("name_mainr5f0_0fw", "addr_mainr5f0_0load",
372 &loadaddr);
373 if (size <= 0)
374 goto err_load;
375
376 /* assuming remoteproc 2 is aliased for the needed remotecore */
377 ret = rproc_load(2, loadaddr, size);
378 if (ret) {
379 printf("Firmware failed to start on rproc (%d)\n", ret);
380 goto err_load;
381 }
382
383 ret = rproc_start(2);
384 if (ret) {
385 printf("Firmware init failed on rproc (%d)\n", ret);
386 goto err_load;
387 }
388
389 printf("Remoteproc 2 started successfully\n");
390
391 return;
392
393 err_load:
394 rproc_reset(2);
395 }
396 #endif
397