1// SPDX-License-Identifier: GPL-2.0+ OR X11 2/* 3 * NXP lx2160a SOC common device tree source 4 * 5 * Copyright 2018-2020 NXP 6 * 7 */ 8 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10 11/ { 12 compatible = "fsl,lx2160a"; 13 interrupt-parent = <&gic>; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 memory@80000000 { 18 device_type = "memory"; 19 reg = <0x00000000 0x80000000 0 0x80000000>; 20 /* DRAM space - 1, size : 2 GB DRAM */ 21 }; 22 23 sysclk: sysclk { 24 compatible = "fixed-clock"; 25 #clock-cells = <0>; 26 clock-frequency = <100000000>; 27 clock-output-names = "sysclk"; 28 }; 29 30 clockgen: clocking@1300000 { 31 compatible = "fsl,ls2080a-clockgen"; 32 reg = <0 0x1300000 0 0xa0000>; 33 #clock-cells = <2>; 34 clocks = <&sysclk>; 35 }; 36 37 gic: interrupt-controller@6000000 { 38 compatible = "arm,gic-v3"; 39 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ 40 <0x0 0x06200000 0 0x100000>; /* GICR */ 41 #interrupt-cells = <3>; 42 interrupt-controller; 43 interrupts = <1 9 0x4>; 44 }; 45 46 gic_lpi_base: syscon@0x80000000 { 47 compatible = "gic-lpi-base"; 48 reg = <0x0 0x80000000 0x0 0x200000>; 49 max-gic-redistributors = <16>; 50 }; 51 52 timer { 53 compatible = "arm,armv8-timer"; 54 interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */ 55 <1 14 0x8>, /* Physical NS PPI, active-low */ 56 <1 11 0x8>, /* Virtual PPI, active-low */ 57 <1 10 0x8>; /* Hypervisor PPI, active-low */ 58 }; 59 60 fspi: flexspi@20c0000 { 61 compatible = "nxp,lx2160a-fspi"; 62 #address-cells = <1>; 63 #size-cells = <0>; 64 reg = <0x0 0x20c0000 0x0 0x10000>, 65 <0x0 0x20000000 0x0 0x10000000>; 66 reg-names = "fspi_base", "fspi_mmap"; 67 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 68 clock-names = "fspi_en", "fspi"; 69 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 70 status = "disabled"; 71 }; 72 73 i2c0: i2c@2000000 { 74 compatible = "fsl,vf610-i2c"; 75 #address-cells = <1>; 76 #size-cells = <0>; 77 reg = <0x0 0x2000000 0x0 0x10000>; 78 interrupts = <0 34 4>; 79 scl-gpio = <&gpio2 15 0>; 80 status = "disabled"; 81 }; 82 83 i2c1: i2c@2010000 { 84 compatible = "fsl,vf610-i2c"; 85 #address-cells = <1>; 86 #size-cells = <0>; 87 reg = <0x0 0x2010000 0x0 0x10000>; 88 interrupts = <0 34 4>; 89 status = "disabled"; 90 }; 91 92 i2c2: i2c@2020000 { 93 compatible = "fsl,vf610-i2c"; 94 #address-cells = <1>; 95 #size-cells = <0>; 96 reg = <0x0 0x2020000 0x0 0x10000>; 97 interrupts = <0 35 4>; 98 status = "disabled"; 99 }; 100 101 i2c3: i2c@2030000 { 102 compatible = "fsl,vf610-i2c"; 103 #address-cells = <1>; 104 #size-cells = <0>; 105 reg = <0x0 0x2030000 0x0 0x10000>; 106 interrupts = <0 35 4>; 107 status = "disabled"; 108 }; 109 110 i2c4: i2c@2040000 { 111 compatible = "fsl,vf610-i2c"; 112 #address-cells = <1>; 113 #size-cells = <0>; 114 reg = <0x0 0x2040000 0x0 0x10000>; 115 interrupts = <0 74 4>; 116 scl-gpio = <&gpio2 16 0>; 117 status = "disabled"; 118 }; 119 120 i2c5: i2c@2050000 { 121 compatible = "fsl,vf610-i2c"; 122 #address-cells = <1>; 123 #size-cells = <0>; 124 reg = <0x0 0x2050000 0x0 0x10000>; 125 interrupts = <0 74 4>; 126 status = "disabled"; 127 }; 128 129 i2c6: i2c@2060000 { 130 compatible = "fsl,vf610-i2c"; 131 #address-cells = <1>; 132 #size-cells = <0>; 133 reg = <0x0 0x2060000 0x0 0x10000>; 134 interrupts = <0 75 4>; 135 status = "disabled"; 136 }; 137 138 i2c7: i2c@2070000 { 139 compatible = "fsl,vf610-i2c"; 140 #address-cells = <1>; 141 #size-cells = <0>; 142 reg = <0x0 0x2070000 0x0 0x10000>; 143 interrupts = <0 75 4>; 144 status = "disabled"; 145 }; 146 147 uart0: serial@21c0000 { 148 compatible = "arm,pl011"; 149 reg = <0x0 0x21c0000 0x0 0x1000>; 150 clocks = <&clockgen 4 0>; 151 status = "disabled"; 152 }; 153 154 uart1: serial@21d0000 { 155 compatible = "arm,pl011"; 156 reg = <0x0 0x21d0000 0x0 0x1000>; 157 clocks = <&clockgen 4 0>; 158 status = "disabled"; 159 }; 160 161 uart2: serial@21e0000 { 162 compatible = "arm,pl011"; 163 reg = <0x0 0x21e0000 0x0 0x1000>; 164 clocks = <&clockgen 4 0>; 165 status = "disabled"; 166 }; 167 168 uart3: serial@21f0000 { 169 compatible = "arm,pl011"; 170 reg = <0x0 0x21f0000 0x0 0x1000>; 171 clocks = <&clockgen 4 0>; 172 status = "disabled"; 173 }; 174 175 dspi0: dspi@2100000 { 176 compatible = "fsl,vf610-dspi"; 177 #address-cells = <1>; 178 #size-cells = <0>; 179 reg = <0x0 0x2100000 0x0 0x10000>; 180 interrupts = <0 26 0x4>; /* Level high type */ 181 num-cs = <6>; 182 }; 183 184 dspi1: dspi@2110000 { 185 compatible = "fsl,vf610-dspi"; 186 #address-cells = <1>; 187 #size-cells = <0>; 188 reg = <0x0 0x2110000 0x0 0x10000>; 189 interrupts = <0 26 0x4>; /* Level high type */ 190 num-cs = <6>; 191 }; 192 193 dspi2: dspi@2120000 { 194 compatible = "fsl,vf610-dspi"; 195 #address-cells = <1>; 196 #size-cells = <0>; 197 reg = <0x0 0x2120000 0x0 0x10000>; 198 interrupts = <0 241 0x4>; /* Level high type */ 199 num-cs = <6>; 200 }; 201 202 gpio0: gpio@2300000 { 203 compatible = "fsl,qoriq-gpio"; 204 reg = <0x0 0x2300000 0x0 0x10000>; 205 interrupts = <0 36 4>; 206 gpio-controller; 207 little-endian; 208 #gpio-cells = <2>; 209 interrupt-controller; 210 #interrupt-cells = <2>; 211 }; 212 213 gpio1: gpio@2310000 { 214 compatible = "fsl,qoriq-gpio"; 215 reg = <0x0 0x2310000 0x0 0x10000>; 216 interrupts = <0 36 4>; 217 gpio-controller; 218 little-endian; 219 #gpio-cells = <2>; 220 interrupt-controller; 221 #interrupt-cells = <2>; 222 }; 223 224 gpio2: gpio@2320000 { 225 compatible = "fsl,qoriq-gpio"; 226 reg = <0x0 0x2320000 0x0 0x10000>; 227 interrupts = <0 37 4>; 228 gpio-controller; 229 little-endian; 230 #gpio-cells = <2>; 231 interrupt-controller; 232 #interrupt-cells = <2>; 233 }; 234 235 gpio3: gpio@2330000 { 236 compatible = "fsl,qoriq-gpio"; 237 reg = <0x0 0x2330000 0x0 0x10000>; 238 interrupts = <0 37 4>; 239 gpio-controller; 240 little-endian; 241 #gpio-cells = <2>; 242 interrupt-controller; 243 #interrupt-cells = <2>; 244 }; 245 246 watchdog@23a0000 { 247 compatible = "arm,sbsa-gwdt"; 248 reg = <0x0 0x23a0000 0 0x1000>, 249 <0x0 0x2390000 0 0x1000>; 250 timeout-sec = <30>; 251 }; 252 253 usb0: usb3@3100000 { 254 compatible = "fsl,layerscape-dwc3"; 255 reg = <0x0 0x3100000 0x0 0x10000>; 256 interrupts = <0 80 0x4>; /* Level high type */ 257 dr_mode = "host"; 258 }; 259 260 usb1: usb3@3110000 { 261 compatible = "fsl,layerscape-dwc3"; 262 reg = <0x0 0x3110000 0x0 0x10000>; 263 interrupts = <0 81 0x4>; /* Level high type */ 264 dr_mode = "host"; 265 }; 266 267 esdhc0: esdhc@2140000 { 268 compatible = "fsl,esdhc"; 269 reg = <0x0 0x2140000 0x0 0x10000>; 270 interrupts = <0 28 0x4>; /* Level high type */ 271 clocks = <&clockgen 4 1>; 272 voltage-ranges = <1800 1800 3300 3300>; 273 sdhci,auto-cmd12; 274 little-endian; 275 bus-width = <4>; 276 status = "disabled"; 277 }; 278 279 esdhc1: esdhc@2150000 { 280 compatible = "fsl,esdhc"; 281 reg = <0x0 0x2150000 0x0 0x10000>; 282 interrupts = <0 63 0x4>; /* Level high type */ 283 clocks = <&clockgen 4 1>; 284 voltage-ranges = <1800 1800 3300 3300>; 285 sdhci,auto-cmd12; 286 non-removable; 287 little-endian; 288 bus-width = <4>; 289 status = "disabled"; 290 }; 291 292 sata0: sata@3200000 { 293 compatible = "fsl,ls2080a-ahci"; 294 reg = <0x0 0x3200000 0x0 0x10000>; 295 interrupts = <0 133 4>; 296 clocks = <&clockgen 4 3>; 297 status = "disabled"; 298 299 }; 300 301 sata1: sata@3210000 { 302 compatible = "fsl,ls2080a-ahci"; 303 reg = <0x0 0x3210000 0x0 0x10000>; 304 interrupts = <0 136 4>; 305 clocks = <&clockgen 4 3>; 306 status = "disabled"; 307 308 }; 309 310 sata2: sata@3220000 { 311 compatible = "fsl,ls2080a-ahci"; 312 reg = <0x0 0x3220000 0x0 0x10000>; 313 interrupts = <0 97 4>; 314 clocks = <&clockgen 4 3>; 315 status = "disabled"; 316 317 }; 318 319 sata3: sata@3230000 { 320 compatible = "fsl,ls2080a-ahci"; 321 reg = <0x0 0x3230000 0x0 0x10000>; 322 interrupts = <0 100 4>; 323 clocks = <&clockgen 4 3>; 324 status = "disabled"; 325 326 }; 327 328 pcie1: pcie@3400000 { 329 compatible = "fsl,lx2160a-pcie"; 330 reg = <0x00 0x03400000 0x0 0x80000 /* PAB registers */ 331 0x00 0x03480000 0x0 0x40000 /* LUT registers */ 332 0x00 0x034c0000 0x0 0x40000 /* PF control registers */ 333 0x80 0x00000000 0x0 0x2000>; /* configuration space */ 334 reg-names = "ccsr", "lut", "pf_ctrl", "config"; 335 #address-cells = <3>; 336 #size-cells = <2>; 337 device_type = "pci"; 338 bus-range = <0x0 0xff>; 339 ranges = <0x81000000 0x0 0x00000000 0x80 0x00020000 0x0 0x00010000 /* downstream I/O */ 340 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 341 }; 342 343 pcie2: pcie@3500000 { 344 compatible = "fsl,lx2160a-pcie"; 345 reg = <0x00 0x03500000 0x0 0x80000 /* PAB registers */ 346 0x00 0x03580000 0x0 0x40000 /* LUT registers */ 347 0x00 0x035c0000 0x0 0x40000 /* PF control registers */ 348 0x88 0x00000000 0x0 0x2000>; /* configuration space */ 349 reg-names = "ccsr", "lut", "pf_ctrl", "config"; 350 #address-cells = <3>; 351 #size-cells = <2>; 352 device_type = "pci"; 353 num-lanes = <2>; 354 bus-range = <0x0 0xff>; 355 ranges = <0x81000000 0x0 0x00000000 0x88 0x00020000 0x0 0x00010000 /* downstream I/O */ 356 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 357 }; 358 359 pcie3: pcie@3600000 { 360 compatible = "fsl,lx2160a-pcie"; 361 reg = <0x00 0x03600000 0x0 0x80000 /* PAB registers */ 362 0x00 0x03680000 0x0 0x40000 /* LUT registers */ 363 0x00 0x036c0000 0x0 0x40000 /* PF control registers */ 364 0x90 0x00000000 0x0 0x2000>; /* configuration space */ 365 reg-names = "ccsr", "lut", "pf_ctrl", "config"; 366 #address-cells = <3>; 367 #size-cells = <2>; 368 device_type = "pci"; 369 bus-range = <0x0 0xff>; 370 ranges = <0x81000000 0x0 0x00000000 0x90 0x00020000 0x0 0x00010000 /* downstream I/O */ 371 0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 372 }; 373 374 pcie4: pcie@3700000 { 375 compatible = "fsl,lx2160a-pcie"; 376 reg = <0x00 0x03700000 0x0 0x80000 /* PAB registers */ 377 0x00 0x03780000 0x0 0x40000 /* LUT registers */ 378 0x00 0x037c0000 0x0 0x40000 /* PF control registers */ 379 0x98 0x00000000 0x0 0x2000>; /* configuration space */ 380 reg-names = "ccsr", "lut", "pf_ctrl", "config"; 381 #address-cells = <3>; 382 #size-cells = <2>; 383 device_type = "pci"; 384 bus-range = <0x0 0xff>; 385 ranges = <0x81000000 0x0 0x00000000 0x98 0x00020000 0x0 0x00010000 /* downstream I/O */ 386 0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 387 }; 388 389 pcie5: pcie@3800000 { 390 compatible = "fsl,lx2160a-pcie"; 391 reg = <0x00 0x03800000 0x0 0x80000 /* PAB registers */ 392 0x00 0x03880000 0x0 0x40000 /* LUT registers */ 393 0x00 0x038c0000 0x0 0x40000 /* PF control registers */ 394 0xa0 0x00000000 0x0 0x2000>; /* configuration space */ 395 reg-names = "ccsr", "lut", "pf_ctrl", "config"; 396 #address-cells = <3>; 397 #size-cells = <2>; 398 device_type = "pci"; 399 bus-range = <0x0 0xff>; 400 ranges = <0x81000000 0x0 0x00000000 0xa0 0x00020000 0x0 0x00010000 /* downstream I/O */ 401 0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 402 }; 403 404 pcie6: pcie@3900000 { 405 compatible = "fsl,lx2160a-pcie"; 406 reg = <0x00 0x03900000 0x0 0x80000 /* PAB registers */ 407 0x00 0x03980000 0x0 0x40000 /* LUT registers */ 408 0x00 0x039c0000 0x0 0x40000 /* PF control registers */ 409 0xa8 0x00000000 0x0 0x2000>; /* configuration space */ 410 reg-names = "ccsr", "lut", "pf_ctrl", "config"; 411 #address-cells = <3>; 412 #size-cells = <2>; 413 device_type = "pci"; 414 bus-range = <0x0 0xff>; 415 ranges = <0x81000000 0x0 0x00000000 0xa8 0x00020000 0x0 0x00010000 /* downstream I/O */ 416 0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 417 }; 418 419 fsl_mc: fsl-mc@80c000000 { 420 compatible = "fsl,qoriq-mc", "simple-mfd"; 421 reg = <0x00000008 0x0c000000 0 0x40>, 422 <0x00000000 0x08340000 0 0x40000>; 423 #address-cells = <3>; 424 #size-cells = <1>; 425 426 /* 427 * Region type 0x0 - MC portals 428 * Region type 0x1 - QBMAN portals 429 */ 430 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 431 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; 432 433 dpmacs { 434 compatible = "simple-mfd"; 435 #address-cells = <1>; 436 #size-cells = <0>; 437 438 dpmac1: dpmac@1 { 439 compatible = "fsl,qoriq-mc-dpmac"; 440 reg = <0x1>; 441 status = "disabled"; 442 }; 443 444 dpmac2: dpmac@2 { 445 compatible = "fsl,qoriq-mc-dpmac"; 446 reg = <0x2>; 447 status = "disabled"; 448 }; 449 450 dpmac3: dpmac@3 { 451 compatible = "fsl,qoriq-mc-dpmac"; 452 reg = <0x3>; 453 status = "disabled"; 454 }; 455 456 dpmac4: dpmac@4 { 457 compatible = "fsl,qoriq-mc-dpmac"; 458 reg = <0x4>; 459 status = "disabled"; 460 }; 461 462 dpmac5: dpmac@5 { 463 compatible = "fsl,qoriq-mc-dpmac"; 464 reg = <0x5>; 465 status = "disabled"; 466 }; 467 468 dpmac6: dpmac@6 { 469 compatible = "fsl,qoriq-mc-dpmac"; 470 reg = <0x6>; 471 status = "disabled"; 472 }; 473 474 dpmac7: dpmac@7 { 475 compatible = "fsl,qoriq-mc-dpmac"; 476 reg = <0x7>; 477 status = "disabled"; 478 }; 479 480 dpmac8: dpmac@8 { 481 compatible = "fsl,qoriq-mc-dpmac"; 482 reg = <0x8>; 483 status = "disabled"; 484 }; 485 486 dpmac9: dpmac@9 { 487 compatible = "fsl,qoriq-mc-dpmac"; 488 reg = <0x9>; 489 status = "disabled"; 490 }; 491 492 dpmac10: dpmac@a { 493 compatible = "fsl,qoriq-mc-dpmac"; 494 reg = <0xa>; 495 status = "disabled"; 496 }; 497 498 dpmac11: dpmac@b { 499 compatible = "fsl,qoriq-mc-dpmac"; 500 reg = <0xb>; 501 status = "disabled"; 502 }; 503 504 dpmac12: dpmac@c { 505 compatible = "fsl,qoriq-mc-dpmac"; 506 reg = <0xc>; 507 status = "disabled"; 508 }; 509 510 dpmac13: dpmac@d { 511 compatible = "fsl,qoriq-mc-dpmac"; 512 reg = <0xd>; 513 status = "disabled"; 514 }; 515 516 dpmac14: dpmac@e { 517 compatible = "fsl,qoriq-mc-dpmac"; 518 reg = <0xe>; 519 status = "disabled"; 520 }; 521 522 dpmac15: dpmac@f { 523 compatible = "fsl,qoriq-mc-dpmac"; 524 reg = <0xf>; 525 status = "disabled"; 526 }; 527 528 dpmac16: dpmac@10 { 529 compatible = "fsl,qoriq-mc-dpmac"; 530 reg = <0x10>; 531 status = "disabled"; 532 }; 533 534 dpmac17: dpmac@11 { 535 compatible = "fsl,qoriq-mc-dpmac"; 536 reg = <0x11>; 537 status = "disabled"; 538 }; 539 540 dpmac18: dpmac@12 { 541 compatible = "fsl,qoriq-mc-dpmac"; 542 reg = <0x12>; 543 status = "disabled"; 544 }; 545 }; 546 }; 547 548 /* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */ 549 emdio1: mdio@8b96000 { 550 compatible = "fsl,ls-mdio"; 551 reg = <0x0 0x8b96000 0x0 0x1000>; 552 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 553 #address-cells = <1>; 554 #size-cells = <0>; 555 status = "disabled"; 556 }; 557 558 /* WRIOP0: 0x8b8_0000, E-MDIO2: 0x1_7000 */ 559 emdio2: mdio@8b97000 { 560 compatible = "fsl,ls-mdio"; 561 reg = <0x0 0x8b97000 0x0 0x1000>; 562 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 563 #address-cells = <1>; 564 #size-cells = <0>; 565 status = "disabled"; 566 }; 567 firmware { 568 optee { 569 compatible = "linaro,optee-tz"; 570 method = "smc"; 571 }; 572 }; 573}; 574