1// SPDX-License-Identifier: GPL-2.0+
2//
3// Copyright 2013-2019 Boundary Devices, Inc.
4// Copyright 2012 Freescale Semiconductor, Inc.
5// Copyright 2011 Linaro Ltd.
6
7#include <dt-bindings/clock/imx6qdl-clock.h>
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/input/input.h>
10
11&iomuxc {
12	pinctrl-names = "default";
13	pinctrl-0 = <&pinctrl_hog>;
14
15	pinctrl_ecspi1: ecspi1grp {
16		fsl,pins = <
17			MX6QDL_PAD_EIM_D17__ECSPI1_MISO		0x100b1
18			MX6QDL_PAD_EIM_D18__ECSPI1_MOSI		0x100b1
19			MX6QDL_PAD_EIM_D16__ECSPI1_SCLK		0x000b1
20#define GP_ECSPI1_NOR_CS	<&gpio3 19 GPIO_ACTIVE_LOW>
21			MX6QDL_PAD_EIM_D19__GPIO3_IO19		0x0b0b1
22		>;
23	};
24
25	pinctrl_enet: enetgrp {
26		fsl,pins = <
27			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
28			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
29			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x100b0
30			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x100b0
31			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x100b0
32			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x100b0
33			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x100b0
34			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x100b0
35			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x100b0
36			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0
37			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b0b0
38			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b0b0
39			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0
40			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0
41			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b0b0
42#undef GP_ENET_PHY_RESET
43#define GP_ENET_PHY_RESET	<&gpio3 23 GPIO_ACTIVE_LOW>
44			MX6QDL_PAD_EIM_D23__GPIO3_IO23		0x030b0
45#define GPIRQ_ENET_PHY		<&gpio1 28 IRQ_TYPE_LEVEL_LOW>
46			MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28	0x1b0b0
47		>;
48	};
49
50	pinctrl_hog: hoggrp {
51		fsl,pins = <
52			/* Spare */
53			MX6QDL_PAD_NANDF_D7__GPIO2_IO07		0x1b0b0
54		>;
55	};
56
57	pinctrl_i2c1: i2c1grp {
58		fsl,pins = <
59			MX6QDL_PAD_EIM_D21__I2C1_SCL		0x4001b8b1
60			MX6QDL_PAD_EIM_D28__I2C1_SDA		0x4001b8b1
61		>;
62	};
63
64	pinctrl_i2c1_1: i2c1-1grp {
65		fsl,pins = <
66#define GP_I2C1_SCL	<&gpio3 21 GPIO_ACTIVE_HIGH>
67			MX6QDL_PAD_EIM_D21__GPIO3_IO21		0x4001b8b1
68#define GP_I2C1_SDA	<&gpio3 28 GPIO_ACTIVE_HIGH>
69			MX6QDL_PAD_EIM_D28__GPIO3_IO28		0x4001b8b1
70		>;
71	};
72
73	pinctrl_i2c2: i2c2grp {
74		fsl,pins = <
75			MX6QDL_PAD_KEY_COL3__I2C2_SCL		0x4001b8b1
76			MX6QDL_PAD_KEY_ROW3__I2C2_SDA		0x4001b8b1
77		>;
78	};
79
80	pinctrl_i2c2_1: i2c2-1grp {
81		fsl,pins = <
82#define GP_I2C2_SCL	<&gpio4 12 GPIO_ACTIVE_HIGH>
83			MX6QDL_PAD_KEY_COL3__GPIO4_IO12		0x4001b8b1
84#define GP_I2C2_SDA	<&gpio4 13 GPIO_ACTIVE_HIGH>
85			MX6QDL_PAD_KEY_ROW3__GPIO4_IO13		0x4001b8b1
86		>;
87	};
88
89	pinctrl_i2c3: i2c3grp {
90		fsl,pins = <
91			MX6QDL_PAD_GPIO_5__I2C3_SCL		0x4001b8b1
92			MX6QDL_PAD_GPIO_16__I2C3_SDA		0x4001b8b1
93#define GPIRQ_I2C3_J7	<&gpio1 9 IRQ_TYPE_EDGE_FALLING>
94#define GP_I2C3_J7	<&gpio1 9 GPIO_ACTIVE_LOW>
95			MX6QDL_PAD_GPIO_9__GPIO1_IO09		0x1b0b0
96		>;
97	};
98
99	pinctrl_i2c3_1: i2c3-1grp {
100		fsl,pins = <
101#define GP_I2C3_SCL	<&gpio1 5 GPIO_ACTIVE_HIGH>
102			MX6QDL_PAD_GPIO_5__GPIO1_IO05		0x4001b8b1
103#define GP_I2C3_SDA	<&gpio7 11 GPIO_ACTIVE_HIGH>
104			MX6QDL_PAD_GPIO_16__GPIO7_IO11		0x4001b8b1
105		>;
106	};
107
108	pinctrl_pwm1: pwm1grp {
109		fsl,pins = <
110			MX6QDL_PAD_SD1_DAT3__PWM1_OUT		0x1b0b1
111		>;
112	};
113
114	pinctrl_pwm3: pwm3grp {
115		fsl,pins = <
116			MX6QDL_PAD_SD1_DAT1__PWM3_OUT		0x1b0b1
117		>;
118	};
119
120	pinctrl_pwm4: pwm4grp {
121		fsl,pins = <
122			MX6QDL_PAD_SD1_CMD__PWM4_OUT		0x1b0b1
123		>;
124	};
125
126	pinctrl_reg_usbotg_vbus: reg-usbotg-vbusgrp {
127		fsl,pins = <
128#define GP_REG_USBOTG	<&gpio3 22 GPIO_ACTIVE_HIGH>
129			MX6QDL_PAD_EIM_D22__GPIO3_IO22		0x030b0
130		>;
131	};
132
133	pinctrl_uart1: uart1grp {
134		fsl,pins = <
135			MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA	0x1b0b1
136			MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA	0x1b0b1
137		>;
138	};
139
140	pinctrl_uart2: uart2grp {
141		fsl,pins = <
142			MX6QDL_PAD_EIM_D26__UART2_TX_DATA	0x1b0b1
143			MX6QDL_PAD_EIM_D27__UART2_RX_DATA	0x1b0b1
144		>;
145	};
146
147	pinctrl_usbh1: usbh1grp {
148		fsl,pins = <
149#define GP_USBH1_HUB_RESET	<&gpio7 12 GPIO_ACTIVE_LOW>
150			MX6QDL_PAD_GPIO_17__GPIO7_IO12		0x0b0b0
151		>;
152	};
153
154	pinctrl_usbotg: usbotggrp {
155		fsl,pins = <
156			MX6QDL_PAD_GPIO_1__USB_OTG_ID		0x17059
157			MX6QDL_PAD_KEY_COL4__USB_OTG_OC		0x1b0b0
158		>;
159	};
160
161	pinctrl_usdhc3: usdhc3grp {
162		fsl,pins = <
163			MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
164			MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059
165			MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
166			MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
167			MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
168			MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
169#define GP_USDHC3_CD	<&gpio7 0 GPIO_ACTIVE_LOW>
170			MX6QDL_PAD_SD3_DAT5__GPIO7_IO00		0x1b0b0
171#define GP_USDHC3_WP	<&gpio7 1 GPIO_ACTIVE_HIGH>
172			MX6QDL_PAD_SD3_DAT4__GPIO7_IO01         0x1b0b0
173		>;
174	};
175
176	pinctrl_usdhc4: usdhc4grp {
177		fsl,pins = <
178			MX6QDL_PAD_SD4_CMD__SD4_CMD		0x17059
179			MX6QDL_PAD_SD4_CLK__SD4_CLK		0x10059
180			MX6QDL_PAD_SD4_DAT0__SD4_DATA0		0x17059
181			MX6QDL_PAD_SD4_DAT1__SD4_DATA1		0x17059
182			MX6QDL_PAD_SD4_DAT2__SD4_DATA2		0x17059
183			MX6QDL_PAD_SD4_DAT3__SD4_DATA3		0x17059
184#define GP_USDHC4_CD	<&gpio2 6 GPIO_ACTIVE_LOW>
185			MX6QDL_PAD_NANDF_D6__GPIO2_IO06		0x1b0b0
186		>;
187	};
188};
189
190/ {
191	aliases {
192		mmc0 = &usdhc3;
193		mmc1 = &usdhc4;
194		pwm_lcd = &pwm1;
195		pwm_lvds = &pwm4;
196	};
197
198	chosen {
199		stdout-path = &uart2;
200	};
201
202	memory {
203		reg = <0x10000000 0x40000000>;
204	};
205
206	reg_3p3v: regulator-3v3 {
207		compatible = "regulator-fixed";
208		regulator-name = "3P3V";
209		regulator-min-microvolt = <3300000>;
210		regulator-max-microvolt = <3300000>;
211		regulator-always-on;
212	};
213
214	reg_usb_otg_vbus: regulator-usb-otg-vbus {
215		compatible = "regulator-fixed";
216		regulator-name = "usb_otg_vbus";
217		regulator-min-microvolt = <5000000>;
218		regulator-max-microvolt = <5000000>;
219		gpio = GP_REG_USBOTG;
220		enable-active-high;
221	};
222};
223
224&ecspi1 {
225	cs-gpios = GP_ECSPI1_NOR_CS;
226	pinctrl-names = "default";
227	pinctrl-0 = <&pinctrl_ecspi1>;
228	status = "okay";
229
230	flash: m25p80@0 {
231		compatible = "sst,sst25vf016b", "jedec,spi-nor";
232		spi-max-frequency = <20000000>;
233		reg = <0>;
234		#address-cells = <1>;
235		#size-cells = <1>;
236		mtd@00000000 {
237			label = "U-Boot";
238			reg = <0x0 0xC0000>;
239		};
240
241		mtd@000C0000 {
242			label = "env";
243			reg = <0xC0000 0x2000>;
244		};
245		mtd@000C2000 {
246			label = "splash";
247			reg = <0xC2000 0x13e000>;
248		};
249	};
250};
251
252&fec {
253	phy-handle = <&ethphy>;
254	phy-mode = "rgmii";
255#if 0
256	phy-reset-gpios = GP_ENET_PHY_RESET;
257#endif
258	pinctrl-names = "default";
259	pinctrl-0 = <&pinctrl_enet>;
260	rxc-skew-ps = <3000>;
261	rxd0-skew-ps = <0>;
262	rxd1-skew-ps = <0>;
263	rxd2-skew-ps = <0>;
264	rxd3-skew-ps = <0>;
265	rxdv-skew-ps = <0>;
266	status = "okay";
267	txc-skew-ps = <3000>;
268	txd0-skew-ps = <0>;
269	txd1-skew-ps = <0>;
270	txd2-skew-ps = <0>;
271	txd3-skew-ps = <0>;
272	txen-skew-ps = <0>;
273
274	mdio {
275		#address-cells = <0>;
276		#size-cells = <1>;
277
278		ethphy: ethernet-phy {
279			interrupts-extended = GPIRQ_ENET_PHY;
280		};
281	};
282};
283
284&i2c1 {
285	clock-frequency = <100000>;
286	pinctrl-names = "default", "gpio";
287	pinctrl-0 = <&pinctrl_i2c1>;
288	pinctrl-1 = <&pinctrl_i2c1_1>;
289	scl-gpios = GP_I2C1_SCL;
290	sda-gpios = GP_I2C1_SDA;
291	status = "okay";
292};
293
294&i2c2 {
295	clock-frequency = <100000>;
296	pinctrl-names = "default", "gpio";
297	pinctrl-0 = <&pinctrl_i2c2>;
298	pinctrl-1 = <&pinctrl_i2c2_1>;
299	scl-gpios = GP_I2C2_SCL;
300	sda-gpios = GP_I2C2_SDA;
301	status = "okay";
302
303	hdmi_edid: edid@50 {
304		compatible = "fsl,imx6-hdmi-i2c";
305		reg = <0x50>;
306	};
307};
308
309&i2c3 {
310	clock-frequency = <100000>;
311	pinctrl-names = "default", "gpio";
312	pinctrl-0 = <&pinctrl_i2c3>;
313	pinctrl-1 = <&pinctrl_i2c3_1>;
314	scl-gpios = GP_I2C3_SCL;
315	sda-gpios = GP_I2C3_SDA;
316	status = "okay";
317};
318
319&pcie {
320	status = "okay";
321};
322
323&pwm1 {
324	pinctrl-names = "default";
325	pinctrl-0 = <&pinctrl_pwm1>;
326	status = "okay";
327};
328
329&pwm3 {
330	pinctrl-names = "default";
331	pinctrl-0 = <&pinctrl_pwm3>;
332	status = "okay";
333};
334
335&pwm4 {
336	pinctrl-names = "default";
337	pinctrl-0 = <&pinctrl_pwm4>;
338	status = "okay";
339};
340
341&uart1 {
342	pinctrl-names = "default";
343	pinctrl-0 = <&pinctrl_uart1>;
344	status = "okay";
345};
346
347&uart2 {
348	pinctrl-names = "default";
349	pinctrl-0 = <&pinctrl_uart2>;
350	status = "okay";
351};
352
353&usbh1 {
354	pinctrl-names = "default";
355	pinctrl-0 = <&pinctrl_usbh1>;
356	disable-over-current;
357	reset-gpios = GP_USBH1_HUB_RESET;
358	status = "okay";
359};
360
361&usbotg {
362	vbus-supply = <&reg_usb_otg_vbus>;
363	pinctrl-names = "default";
364	pinctrl-0 = <&pinctrl_usbotg>;
365	disable-over-current;
366	status = "okay";
367};
368
369&usdhc3 {
370	pinctrl-names = "default";
371	pinctrl-0 = <&pinctrl_usdhc3>;
372	cd-gpios = GP_USDHC3_CD;
373	wp-gpios = GP_USDHC3_WP;
374	vmmc-supply = <&reg_3p3v>;
375	status = "okay";
376};
377
378&usdhc4 {
379	pinctrl-names = "default";
380	pinctrl-0 = <&pinctrl_usdhc4>;
381	cd-gpios = GP_USDHC4_CD;
382	vmmc-supply = <&reg_3p3v>;
383	status = "okay";
384};
385