1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Google Veyron (and derivatives) board device tree source 4 * 5 * Copyright 2014 Google, Inc 6 */ 7 8#include <dt-bindings/clock/rockchip,rk808.h> 9#include <dt-bindings/input/input.h> 10#include "rk3288.dtsi" 11 12/ { 13 memory { 14 reg = <0x0 0x80000000>; 15 }; 16 17 chosen { 18 stdout-path = &uart2; 19 u-boot,spl-boot-order = &spi_flash; 20 }; 21 22 firmware { 23 chromeos { 24 pinctrl-names = "default"; 25 pinctrl-0 = <&fw_wp_ap>; 26 write-protect-gpio = <&gpio7 6 GPIO_ACTIVE_LOW>; 27 }; 28 }; 29 30 backlight: backlight { 31 compatible = "pwm-backlight"; 32 brightness-levels = < 33 0 1 2 3 4 5 6 7 34 8 9 10 11 12 13 14 15 35 16 17 18 19 20 21 22 23 36 24 25 26 27 28 29 30 31 37 32 33 34 35 36 37 38 39 38 40 41 42 43 44 45 46 47 39 48 49 50 51 52 53 54 55 40 56 57 58 59 60 61 62 63 41 64 65 66 67 68 69 70 71 42 72 73 74 75 76 77 78 79 43 80 81 82 83 84 85 86 87 44 88 89 90 91 92 93 94 95 45 96 97 98 99 100 101 102 103 46 104 105 106 107 108 109 110 111 47 112 113 114 115 116 117 118 119 48 120 121 122 123 124 125 126 127 49 128 129 130 131 132 133 134 135 50 136 137 138 139 140 141 142 143 51 144 145 146 147 148 149 150 151 52 152 153 154 155 156 157 158 159 53 160 161 162 163 164 165 166 167 54 168 169 170 171 172 173 174 175 55 176 177 178 179 180 181 182 183 56 184 185 186 187 188 189 190 191 57 192 193 194 195 196 197 198 199 58 200 201 202 203 204 205 206 207 59 208 209 210 211 212 213 214 215 60 216 217 218 219 220 221 222 223 61 224 225 226 227 228 229 230 231 62 232 233 234 235 236 237 238 239 63 240 241 242 243 244 245 246 247 64 248 249 250 251 252 253 254 255>; 65 default-brightness-level = <128>; 66 enable-gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>; 67 backlight-boot-off; 68 pinctrl-names = "default"; 69 pinctrl-0 = <&bl_en>; 70 pwms = <&pwm0 0 1000000 0>; 71 }; 72 73 panel: panel { 74 compatible ="cnm,n116bgeea2","simple-panel"; 75 status = "okay"; 76 power-supply = <&vcc33_lcd>; 77 backlight = <&backlight>; 78 }; 79 80 gpio_keys: gpio-keys { 81 compatible = "gpio-keys"; 82 83 pinctrl-names = "default"; 84 pinctrl-0 = <&pwr_key_h>; 85 power { 86 label = "Power"; 87 gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>; 88 linux,code = <KEY_POWER>; 89 debounce-interval = <100>; 90 gpio-key,wakeup; 91 }; 92 }; 93 94 gpio-restart { 95 compatible = "gpio-restart"; 96 gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; 97 pinctrl-names = "default"; 98 pinctrl-0 = <&ap_warm_reset_h>; 99 priority = /bits/ 8 <200>; 100 }; 101 102 emmc_pwrseq: emmc-pwrseq { 103 compatible = "mmc-pwrseq-emmc"; 104 pinctrl-0 = <&emmc_reset>; 105 pinctrl-names = "default"; 106 reset-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>; 107 }; 108 109 sound { 110 compatible = "rockchip,rockchip-audio-max98090"; 111 rockchip,model = "ROCKCHIP-I2S"; 112 rockchip,i2s-controller = <&i2s>; 113 rockchip,audio-codec = <&max98090>; 114 rockchip,hp-det-gpios = <&gpio6 5 GPIO_ACTIVE_HIGH>; 115 rockchip,mic-det-gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; 116 rockchip,headset-codec = <&headsetcodec>; 117 pinctrl-names = "default"; 118 pinctrl-0 = <&mic_det>, <&hp_det>; 119 }; 120 121 vdd_logic: pwm-regulator { 122 compatible = "pwm-regulator"; 123 pwms = <&pwm1 0 2000 0>; 124 125 voltage-table = <1350000 0>, 126 <1300000 10>, 127 <1250000 20>, 128 <1200000 31>, 129 <1150000 41>, 130 <1100000 52>, 131 <1050000 62>, 132 <1000000 72>, 133 < 950000 83>; 134 135 regulator-min-microvolt = <950000>; 136 regulator-max-microvolt = <1350000>; 137 regulator-name = "vdd_logic"; 138 regulator-ramp-delay = <4000>; 139 }; 140 141 vcc33_sys: vcc33-sys { 142 compatible = "regulator-fixed"; 143 regulator-name = "vcc33_sys"; 144 regulator-always-on; 145 regulator-boot-on; 146 regulator-min-microvolt = <3300000>; 147 regulator-max-microvolt = <3300000>; 148 vin-supply = <&vccsys>; 149 }; 150 151 vcc_5v: vcc-5v { 152 compatible = "regulator-fixed"; 153 regulator-name = "vcc_5v"; 154 regulator-always-on; 155 regulator-boot-on; 156 regulator-min-microvolt = <5000000>; 157 regulator-max-microvolt = <5000000>; 158 }; 159 160 vcc50_hdmi: vcc50-hdmi { 161 compatible = "regulator-fixed"; 162 regulator-name = "vcc50_hdmi"; 163 regulator-always-on; 164 regulator-boot-on; 165 vin-supply = <&vcc_5v>; 166 }; 167 168 bt_regulator: bt-regulator { 169 /* 170 * On the module itself this is one of these (depending 171 * on the actual card pouplated): 172 * - BT_I2S_WS_BT_RFDISABLE_L 173 * - No connect 174 */ 175 176 compatible = "regulator-fixed"; 177 enable-active-high; 178 gpio = <&gpio4 29 GPIO_ACTIVE_HIGH>; 179 pinctrl-names = "default"; 180 pinctrl-0 = <&bt_enable_l>; 181 regulator-name = "bt_regulator"; 182 }; 183 184 wifi_regulator: wifi-regulator { 185 /* 186 * On the module itself this is one of these (depending 187 * on the actual card populated): 188 * - SDIO_RESET_L_WL_REG_ON 189 * - PDN (power down when low) 190 */ 191 192 compatible = "regulator-fixed"; 193 enable-active-high; 194 gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>; 195 pinctrl-names = "default"; 196 pinctrl-0 = <&wifi_enable_h>; 197 regulator-name = "wifi_regulator"; 198 199 /* Faux input supply. See bt_regulator description. */ 200 vin-supply = <&bt_regulator>; 201 }; 202 203 io-domains { 204 compatible = "rockchip,rk3288-io-voltage-domain"; 205 rockchip,grf = <&grf>; 206 207 audio-supply = <&vcc18_codec>; 208 bb-supply = <&vcc33_io>; 209 dvp-supply = <&vcc_18>; 210 flash0-supply = <&vcc18_flashio>; 211 gpio1830-supply = <&vcc33_io>; 212 gpio30-supply = <&vcc33_io>; 213 lcdc-supply = <&vcc33_lcd>; 214 sdcard-supply = <&vccio_sd>; 215 wifi-supply = <&vcc18_wl>; 216 }; 217}; 218 219&cpu0 { 220 cpu0-supply = <&vdd_cpu>; 221}; 222 223&dmc { 224 logic-supply = <&vdd_logic>; 225 rockchip,odt-disable-freq = <333000000>; 226 rockchip,dll-disable-freq = <333000000>; 227 rockchip,sr-enable-freq = <333000000>; 228 rockchip,pd-enable-freq = <666000000>; 229 rockchip,auto-self-refresh-cnt = <0>; 230 rockchip,auto-power-down-cnt = <64>; 231 rockchip,ddr-speed-bin = <21>; 232 rockchip,trcd = <10>; 233 rockchip,trp = <10>; 234 operating-points = < 235 /* KHz uV */ 236 200000 1050000 237 333000 1100000 238 533000 1150000 239 666000 1200000 240 >; 241}; 242 243&efuse { 244 status = "okay"; 245}; 246 247&emmc { 248 broken-cd; 249 bus-width = <8>; 250 cap-mmc-highspeed; 251 mmc-hs200-1_8v; 252 mmc-pwrseq = <&emmc_pwrseq>; 253 disable-wp; 254 non-removable; 255 num-slots = <1>; 256 pinctrl-names = "default"; 257 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8 &emmc_pwr>; 258 status = "okay"; 259}; 260 261&sdio0 { 262 broken-cd; 263 bus-width = <4>; 264 cap-sd-highspeed; 265 sd-uhs-sdr12; 266 sd-uhs-sdr25; 267 sd-uhs-sdr50; 268 sd-uhs-sdr104; 269 cap-sdio-irq; 270 card-external-vcc-supply = <&wifi_regulator>; 271 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, <&cru SCLK_SDIO0_DRV>, 272 <&cru SCLK_SDIO0_SAMPLE>, <&rk808 RK808_CLKOUT1>; 273 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample", "card_ext_clock"; 274 keep-power-in-suspend; 275 non-removable; 276 num-slots = <1>; 277 pinctrl-names = "default"; 278 pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_bus4>; 279 status = "okay"; 280 vmmc-supply = <&vcc33_sys>; 281 vqmmc-supply = <&vcc18_wl>; 282}; 283 284&sdmmc { 285 bus-width = <4>; 286 cap-mmc-highspeed; 287 cap-sd-highspeed; 288 sd-uhs-sdr12; 289 sd-uhs-sdr25; 290 sd-uhs-sdr50; 291 sd-uhs-sdr104; 292 card-detect-delay = <200>; 293 cd-gpios = <&gpio7 5 GPIO_ACTIVE_LOW>; 294 num-slots = <1>; 295 status = "okay"; 296 vmmc-supply = <&vcc33_sd>; 297 vqmmc-supply = <&vccio_sd>; 298}; 299 300&spi2 { 301 status = "okay"; 302 u-boot,dm-pre-reloc; 303 304 spi_flash: spiflash@0 { 305 u-boot,dm-pre-reloc; 306 compatible = "spidev", "jedec,spi-nor"; 307 spi-max-frequency = <20000000>; /* Reduce for Dediprog em100 pro */ 308 reg = <0>; 309 }; 310}; 311 312&i2c0 { 313 status = "okay"; 314 315 clock-frequency = <400000>; 316 i2c-scl-falling-time-ns = <50>; /* 2.5ns measured */ 317 i2c-scl-rising-time-ns = <100>; /* 45ns measured */ 318 u-boot,dm-pre-reloc; 319 320 rk808: pmic@1b { 321 compatible = "rockchip,rk808"; 322 clock-output-names = "xin32k", "wifibt_32kin"; 323 interrupt-parent = <&gpio0>; 324 interrupts = <4 IRQ_TYPE_LEVEL_LOW>; 325 pinctrl-names = "default"; 326 pinctrl-0 = <&pmic_int_l>; 327 reg = <0x1b>; 328 rockchip,system-power-controller; 329 wakeup-source; 330 #clock-cells = <1>; 331 u-boot,dm-pre-reloc; 332 333 vcc1-supply = <&vcc33_sys>; 334 vcc2-supply = <&vcc33_sys>; 335 vcc3-supply = <&vcc33_sys>; 336 vcc4-supply = <&vcc33_sys>; 337 vcc6-supply = <&vcc_5v>; 338 vcc7-supply = <&vcc33_sys>; 339 vcc8-supply = <&vcc33_sys>; 340 vcc9-supply = <&vcc_5v>; 341 vcc10-supply = <&vcc33_sys>; 342 vcc11-supply = <&vcc_5v>; 343 vcc12-supply = <&vcc_18>; 344 345 vddio-supply = <&vcc33_io>; 346 347 regulators { 348 vdd_cpu: DCDC_REG1 { 349 regulator-always-on; 350 regulator-boot-on; 351 regulator-min-microvolt = <750000>; 352 regulator-max-microvolt = <1450000>; 353 regulator-name = "vdd_arm"; 354 regulator-ramp-delay = <6001>; 355 regulator-suspend-mem-disabled; 356 }; 357 358 vdd_gpu: DCDC_REG2 { 359 regulator-always-on; 360 regulator-boot-on; 361 regulator-min-microvolt = <800000>; 362 regulator-max-microvolt = <1250000>; 363 regulator-name = "vdd_gpu"; 364 regulator-ramp-delay = <6001>; 365 regulator-suspend-mem-disabled; 366 }; 367 368 vcc135_ddr: DCDC_REG3 { 369 regulator-always-on; 370 regulator-boot-on; 371 regulator-name = "vcc135_ddr"; 372 regulator-suspend-mem-enabled; 373 }; 374 375 /* 376 * vcc_18 has several aliases. (vcc18_flashio and 377 * vcc18_wl). We'll add those aliases here just to 378 * make it easier to follow the schematic. The signals 379 * are actually hooked together and only separated for 380 * power measurement purposes). 381 */ 382 vcc18_wl: vcc18_flashio: vcc_18: DCDC_REG4 { 383 regulator-always-on; 384 regulator-boot-on; 385 regulator-min-microvolt = <1800000>; 386 regulator-max-microvolt = <1800000>; 387 regulator-name = "vcc_18"; 388 regulator-suspend-mem-microvolt = <1800000>; 389 }; 390 391 /* 392 * Note that both vcc33_io and vcc33_pmuio are always 393 * powered together. To simplify the logic in the dts 394 * we just refer to vcc33_io every time something is 395 * powered from vcc33_pmuio. In fact, on later boards 396 * (such as danger) they're the same net. 397 */ 398 vcc33_io: LDO_REG1 { 399 regulator-always-on; 400 regulator-boot-on; 401 regulator-min-microvolt = <3300000>; 402 regulator-max-microvolt = <3300000>; 403 regulator-name = "vcc33_io"; 404 regulator-suspend-mem-microvolt = <3300000>; 405 }; 406 407 vdd_10: LDO_REG3 { 408 regulator-always-on; 409 regulator-boot-on; 410 regulator-min-microvolt = <1000000>; 411 regulator-max-microvolt = <1000000>; 412 regulator-name = "vdd_10"; 413 regulator-suspend-mem-microvolt = <1000000>; 414 }; 415 416 vccio_sd: LDO_REG4 { 417 regulator-min-microvolt = <1800000>; 418 regulator-max-microvolt = <3300000>; 419 regulator-name = "vccio_sd"; 420 regulator-suspend-mem-disabled; 421 }; 422 423 vcc33_sd: LDO_REG5 { 424 regulator-min-microvolt = <3300000>; 425 regulator-max-microvolt = <3300000>; 426 regulator-name = "vcc33_sd"; 427 regulator-suspend-mem-disabled; 428 }; 429 430 vcc18_codec: LDO_REG6 { 431 regulator-always-on; 432 regulator-boot-on; 433 regulator-min-microvolt = <1800000>; 434 regulator-max-microvolt = <1800000>; 435 regulator-name = "vcc18_codec"; 436 regulator-suspend-mem-disabled; 437 }; 438 439 vdd10_lcd_pwren_h: LDO_REG7 { 440 regulator-always-on; 441 regulator-boot-on; 442 regulator-min-microvolt = <2500000>; 443 regulator-max-microvolt = <2500000>; 444 regulator-name = "vdd10_lcd_pwren_h"; 445 regulator-suspend-mem-disabled; 446 }; 447 448 vcc33_lcd: SWITCH_REG1 { 449 regulator-always-on; 450 regulator-boot-on; 451 regulator-name = "vcc33_lcd"; 452 regulator-suspend-mem-disabled; 453 }; 454 }; 455 }; 456}; 457 458&i2c1 { 459 status = "okay"; 460 461 clock-frequency = <400000>; 462 i2c-scl-falling-time-ns = <50>; /* 2.5ns measured */ 463 i2c-scl-rising-time-ns = <100>; /* 40ns measured */ 464 465 tpm: tpm@20 { 466 compatible = "infineon,slb9645tt"; 467 reg = <0x20>; 468 powered-while-suspended; 469 }; 470}; 471 472&i2c2 { 473 status = "okay"; 474 475 /* 100kHz since 4.7k resistors don't rise fast enough */ 476 clock-frequency = <100000>; 477 i2c-scl-falling-time-ns = <50>; /* 10ns measured */ 478 i2c-scl-rising-time-ns = <800>; /* 600ns measured */ 479 480 max98090: max98090@10 { 481 compatible = "maxim,max98090"; 482 reg = <0x10>; 483 #sound-dai-cells = <0>; 484 interrupt-parent = <&gpio6>; 485 interrupts = <7 IRQ_TYPE_EDGE_FALLING>; 486 pinctrl-names = "default"; 487 pinctrl-0 = <&int_codec>; 488 }; 489}; 490 491&i2c3 { 492 status = "okay"; 493 494 clock-frequency = <400000>; 495 i2c-scl-falling-time-ns = <50>; 496 i2c-scl-rising-time-ns = <300>; 497}; 498 499&i2c4 { 500 status = "okay"; 501 502 clock-frequency = <400000>; 503 i2c-scl-falling-time-ns = <50>; /* 11ns measured */ 504 i2c-scl-rising-time-ns = <300>; /* 225ns measured */ 505 506 headsetcodec: ts3a227e@3b { 507 compatible = "ti,ts3a227e"; 508 reg = <0x3b>; 509 interrupt-parent = <&gpio0>; 510 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 511 pinctrl-names = "default"; 512 pinctrl-0 = <&ts3a227e_int_l>; 513 ti,micbias = <7>; /* MICBIAS = 2.8V */ 514 }; 515}; 516 517&i2c5 { 518 status = "okay"; 519 520 clock-frequency = <100000>; 521 i2c-scl-falling-time-ns = <300>; 522 i2c-scl-rising-time-ns = <1000>; 523}; 524 525&i2s { 526 status = "okay"; 527 clock-names = "i2s_hclk", "i2s_clk", "i2s_clk_out"; 528 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>, <&cru SCLK_I2S0_OUT>; 529}; 530 531&wdt { 532 status = "okay"; 533}; 534 535&pwm0 { 536 status = "okay"; 537}; 538 539&pwm1 { 540 status = "okay"; 541}; 542 543&uart0 { 544 status = "okay"; 545 546 /* Pins don't include flow control by default; add that in */ 547 pinctrl-names = "default"; 548 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 549 /* We need to go faster than 24MHz, so adjust clock parents / rates */ 550 assigned-clocks = <&cru SCLK_UART0>; 551 assigned-clock-rates = <48000000>; 552}; 553 554&uart1 { 555 status = "okay"; 556}; 557 558&uart2 { 559 status = "okay"; 560 u-boot,dm-pre-reloc; 561 reg-shift = <2>; 562}; 563 564&vopb { 565 status = "okay"; 566}; 567 568&vopb_mmu { 569 status = "okay"; 570}; 571 572&vopl { 573 status = "okay"; 574}; 575 576&vopl_mmu { 577 status = "okay"; 578}; 579 580&edp { 581 status = "okay"; 582 rockchip,panel = <&panel>; 583}; 584 585&hdmi { 586 status = "okay"; 587}; 588 589&hdmi_audio { 590 status = "okay"; 591}; 592 593&gpu { 594 status = "okay"; 595}; 596 597&tsadc { 598 tsadc-tshut-mode = <1>; /* tshut mode 0:CRU 1:GPIO */ 599 tsadc-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */ 600 status = "okay"; 601}; 602 603&pinctrl { 604 u-boot,dm-pre-reloc; 605 pinctrl-names = "default", "sleep"; 606 pinctrl-0 = < 607 /* Common for sleep and wake, but no owners */ 608 &ddr0_retention 609 &ddrio_pwroff 610 &global_pwroff 611 612 /* Wake only */ 613 &bt_dev_wake_awake 614 >; 615 pinctrl-1 = < 616 /* Common for sleep and wake, but no owners */ 617 &ddr0_retention 618 &ddrio_pwroff 619 &global_pwroff 620 621 /* Sleep only */ 622 &bt_dev_wake_sleep 623 >; 624 625 /* Add this for sdmmc pins to SD card */ 626 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma { 627 drive-strength = <8>; 628 }; 629 630 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma { 631 bias-pull-up; 632 drive-strength = <8>; 633 }; 634 635 pcfg_output_high: pcfg-output-high { 636 output-high; 637 }; 638 639 pcfg_output_low: pcfg-output-low { 640 output-low; 641 }; 642 643 backlight { 644 bl_en: bl-en { 645 rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>; 646 }; 647 }; 648 649 buttons { 650 pwr_key_h: pwr-key-h { 651 rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_none>; 652 }; 653 }; 654 655 codec { 656 hp_det: hp-det { 657 rockchip,pins = <6 5 RK_FUNC_GPIO &pcfg_pull_up>; 658 }; 659 int_codec: int-codec { 660 rockchip,pins = <6 7 RK_FUNC_GPIO &pcfg_pull_up>; 661 }; 662 mic_det: mic-det { 663 rockchip,pins = <6 11 RK_FUNC_GPIO &pcfg_pull_up>; 664 }; 665 }; 666 667 emmc { 668 emmc_reset: emmc-reset { 669 rockchip,pins = <2 9 RK_FUNC_GPIO &pcfg_pull_none>; 670 }; 671 672 /* 673 * We run eMMC at max speed; bump up drive strength. 674 * We also have external pulls, so disable the internal ones. 675 */ 676 emmc_clk: emmc-clk { 677 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none_drv_8ma>; 678 }; 679 680 emmc_cmd: emmc-cmd { 681 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none_drv_8ma>; 682 }; 683 684 emmc_bus8: emmc-bus8 { 685 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, 686 <3 1 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, 687 <3 2 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, 688 <3 3 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, 689 <3 4 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, 690 <3 5 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, 691 <3 6 RK_FUNC_2 &pcfg_pull_none_drv_8ma>, 692 <3 7 RK_FUNC_2 &pcfg_pull_none_drv_8ma>; 693 }; 694 }; 695 696 headset { 697 ts3a227e_int_l: ts3a227e-int-l { 698 rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_up>; 699 }; 700 }; 701 702 pmic { 703 pmic_int_l: pmic-int-l { 704 /* 705 * Causes jerry to hang when probing bus 0 706 * rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>; 707 */ 708 }; 709 }; 710 711 reboot { 712 ap_warm_reset_h: ap-warm-reset-h { 713 rockchip,pins = <RK_GPIO0 13 RK_FUNC_GPIO &pcfg_pull_none>; 714 }; 715 }; 716 717 sdio0 { 718 wifi_enable_h: wifienable-h { 719 rockchip,pins = <4 28 RK_FUNC_GPIO &pcfg_pull_none>; 720 }; 721 722 /* NOTE: mislabelled on schematic; should be bt_enable_h */ 723 bt_enable_l: bt-enable-l { 724 rockchip,pins = <4 29 RK_FUNC_GPIO &pcfg_pull_none>; 725 }; 726 727 /* 728 * We run sdio0 at max speed; bump up drive strength. 729 * We also have external pulls, so disable the internal ones. 730 */ 731 sdio0_bus4: sdio0-bus4 { 732 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, 733 <4 21 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, 734 <4 22 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, 735 <4 23 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; 736 }; 737 738 sdio0_cmd: sdio0-cmd { 739 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; 740 }; 741 742 sdio0_clk: sdio0-clk { 743 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; 744 }; 745 746 /* 747 * These pins are only present on very new veyron boards; on 748 * older boards bt_dev_wake is simply always high. Note that 749 * gpio4_26 is a NC on old veyron boards, so it doesn't hurt 750 * to map this pin everywhere 751 */ 752 bt_dev_wake_sleep: bt-dev-wake-sleep { 753 rockchip,pins = <4 26 RK_FUNC_GPIO &pcfg_output_low>; 754 }; 755 756 bt_dev_wake_awake: bt-dev-wake-awake { 757 rockchip,pins = <4 26 RK_FUNC_GPIO &pcfg_output_high>; 758 }; 759 }; 760 761 sdmmc { 762 /* 763 * We run sdmmc at max speed; bump up drive strength. 764 * We also have external pulls, so disable the internal ones. 765 */ 766 sdmmc_bus4: sdmmc-bus4 { 767 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, 768 <6 17 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, 769 <6 18 RK_FUNC_1 &pcfg_pull_none_drv_8ma>, 770 <6 19 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; 771 }; 772 773 sdmmc_clk: sdmmc-clk { 774 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; 775 }; 776 777 sdmmc_cmd: sdmmc-cmd { 778 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_none_drv_8ma>; 779 }; 780 781 /* 782 * Builtin CD line is hooked to ground to prevent JTAG at boot 783 * (and also to get the voltage rail correct). Make we 784 * configure gpio6_C6 as GPIO so dw_mmc builtin CD doesn't 785 * think there's a card inserted 786 */ 787 sdmmc_cd_disabled: sdmmc-cd-disabled { 788 rockchip,pins = <6 22 RK_FUNC_GPIO &pcfg_pull_none>; 789 }; 790 791 /* This is where we actually hook up CD */ 792 sdmmc_cd_gpio: sdmmc-cd-gpio { 793 rockchip,pins = <7 5 RK_FUNC_GPIO &pcfg_pull_none>; 794 }; 795 }; 796 797 tpm { 798 tpm_int_h: tpm-int-h { 799 rockchip,pins = <7 4 RK_FUNC_GPIO &pcfg_pull_none>; 800 }; 801 }; 802 803 write-protect { 804 fw_wp_ap: fw-wp-ap { 805 rockchip,pins = <7 6 RK_FUNC_GPIO &pcfg_pull_none>; 806 }; 807 }; 808}; 809 810&usbphy { 811 status = "okay"; 812}; 813 814&usb_host0_ehci { 815 status = "okay"; 816 needs-reset-on-resume; 817}; 818 819&usb_host1 { 820 status = "okay"; 821}; 822 823&usb_otg { 824 dr_mode = "host"; 825 status = "okay"; 826 assigned-clocks = <&cru SCLK_USBPHY480M_SRC>; 827 assigned-clock-parents = <&cru SCLK_OTGPHY0>; 828}; 829 830&sdmmc { 831 u-boot,dm-pre-reloc; 832}; 833 834&gpio3 { 835 u-boot,dm-pre-reloc; 836}; 837 838&gpio8 { 839 u-boot,dm-pre-reloc; 840}; 841