1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * sama7g5.dtsi - Device Tree Include file for SAMA7G5 SoC.
4 *
5 * Copyright (C) 2020 Microchip Technology Inc. and its subsidiaries
6 *
7 * Author: Eugen Hristev <eugen.hristev@microchip.com>
8 * Author: Claudiu Beznea <claudiu.beznea@microchip.com>
9 *
10 */
11
12#include "skeleton.dtsi"
13#include <dt-bindings/clk/at91.h>
14
15/ {
16	model = "Microchip SAMA7G5 family SoC";
17	compatible = "microchip,sama7g5";
18
19	clocks {
20		slow_rc_osc: slow_rc_osc {
21			compatible = "fixed-clock";
22			#clock-cells = <0>;
23			clock-frequency = <32000>;
24		};
25
26		main_rc: main_rc {
27			compatible = "fixed-clock";
28			#clock-cells = <0>;
29			clock-frequency = <12000000>;
30		};
31
32		slow_xtal: slow_xtal {
33			compatible = "fixed-clock";
34			#clock-cells = <0>;
35		};
36
37		main_xtal: main_xtal {
38			compatible = "fixed-clock";
39			#clock-cells = <0>;
40		};
41	};
42
43	cpus {
44		#address-cells = <1>;
45		#size-cells = <0>;
46
47		A7_0: cpu@0 {
48			device_type = "cpu";
49			compatible = "arm,cortex-a7";
50			clocks = <&pmc PMC_TYPE_CORE 8>, <&pmc PMC_TYPE_CORE 22>, <&main_xtal>;
51			clock-names = "cpu", "master", "xtal";
52		};
53	};
54
55	ahb {
56		compatible = "simple-bus";
57		#address-cells = <1>;
58		#size-cells = <1>;
59
60		apb {
61			compatible = "simple-bus";
62			#address-cells = <1>;
63			#size-cells = <1>;
64
65			pioA: pinctrl@e0014000 {
66				compatible = "microchip,sama7g5-gpio";
67				reg = <0xe0014000 0x800>;
68				gpio-controller;
69				#gpio-cells = <2>;
70				clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
71				status = "okay";
72
73				pinctrl: pinctrl_default {
74					compatible = "microchip,sama7g5-pinctrl";
75				};
76			};
77
78			pmc: pmc@e0018000 {
79				compatible = "microchip,sama7g5-pmc";
80				reg = <0xe0018000 0x200>;
81				#clock-cells = <2>;
82				clocks = <&clk32 1>, <&clk32 0>, <&main_xtal>, <&main_rc>;
83				clock-names = "td_slck", "md_slck", "main_xtal", "main_rc";
84				status = "okay";
85			};
86
87			clk32: sckc@e001d050 {
88				compatible = "microchip,sam9x60-sckc";
89				reg = <0xe001d050 0x4>;
90				clocks = <&slow_rc_osc>, <&slow_xtal>;
91				#clock-cells = <1>;
92			};
93
94			sdmmc0: sdio-host@e1204000 {
95				compatible = "microchip,sama7g5-sdhci";
96				reg = <0xe1204000 0x300>;
97				clocks = <&pmc PMC_TYPE_PERIPHERAL 80>, <&pmc PMC_TYPE_GCK 80>;
98				clock-names = "hclock", "multclk";
99				assigned-clocks = <&pmc PMC_TYPE_GCK 80>;
100				assigned-clock-rates = <200000000>;
101				assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* sys pll div. */
102				status = "disabled";
103			};
104
105			sdmmc1: sdio-host@e1208000 {
106				compatible = "microchip,sama7g5-sdhci";
107				reg = <0xe1208000 0x300>;
108				clocks = <&pmc PMC_TYPE_PERIPHERAL 81>, <&pmc PMC_TYPE_GCK 81>;
109				clock-names = "hclock", "multclk";
110				assigned-clocks = <&pmc PMC_TYPE_GCK 81>;
111				assigned-clock-rates = <200000000>;
112				assigned-clock-parents = <&pmc PMC_TYPE_CORE 10>; /* sys pll div. */
113				status = "disabled";
114			};
115
116			pit64b0: timer@e1800000 {
117				compatible = "microchip,sama7g5-pit64b";
118				reg = <0xe1800000 0x4000>;
119				clocks = <&pmc PMC_TYPE_PERIPHERAL 70>, <&pmc PMC_TYPE_GCK 70>;
120				clock-names = "pclk", "gclk";
121				status = "okay";
122			};
123
124			flx1: flexcom@e181c000 {
125				compatible = "atmel,sama5d2-flexcom";
126				reg = <0xe181c000 0x200>;
127				clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
128				#address-cells = <1>;
129				#size-cells = <1>;
130				ranges = <0x0 0xe181c000 0x800>;
131				status = "disabled";
132
133				i2c1: i2c@600 {
134					compatible = "atmel,sama5d2-i2c";
135					reg = <0x600 0x200>;
136					#address-cells = <1>;
137					#size-cells = <0>;
138					clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
139				};
140			};
141
142			uart0: serial@e1824200 {
143				compatible = "atmel,at91sam9260-usart";
144				reg = <0xe1824200 0x200>;
145				clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
146				clock-names = "usart";
147				status = "disabled";
148			};
149
150			gmac0: ethernet@e2800000 {
151				compatible = "cdns,sama7g5-gem";
152				reg = <0xe2800000 0x4000>;
153				clocks = <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_GCK 51>;
154				clock-names = "hclk", "pclk", "tx_clk";
155				assigned-clocks = <&pmc PMC_TYPE_GCK 51>;
156				assigned-clock-parents = <&pmc PMC_TYPE_CORE 21>; /* eth pll div. */
157				assigned-clock-rates = <125000000>;
158				status = "disabled";
159			};
160
161			gmac1: ethernet@e2804000 {
162				compatible = "cdns,sama7g5-emac";
163				reg = <0xe2804000 0x1000>;
164				clocks = <&pmc PMC_TYPE_PERIPHERAL 52>, <&pmc PMC_TYPE_PERIPHERAL 52>;
165				clock-names = "pclk", "hclk";
166				status = "disabled";
167			};
168		};
169	};
170};
171