1/* 2 * Copyright 2014 Chen-Yu Tsai 3 * 4 * Chen-Yu Tsai <wens@csie.org> 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This file is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * Or, alternatively, 22 * 23 * b) Permission is hereby granted, free of charge, to any person 24 * obtaining a copy of this software and associated documentation 25 * files (the "Software"), to deal in the Software without 26 * restriction, including without limitation the rights to use, 27 * copy, modify, merge, publish, distribute, sublicense, and/or 28 * sell copies of the Software, and to permit persons to whom the 29 * Software is furnished to do so, subject to the following 30 * conditions: 31 * 32 * The above copyright notice and this permission notice shall be 33 * included in all copies or substantial portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42 * OTHER DEALINGS IN THE SOFTWARE. 43 */ 44 45#include <dt-bindings/interrupt-controller/arm-gic.h> 46 47#include <dt-bindings/clock/sun9i-a80-ccu.h> 48#include <dt-bindings/clock/sun9i-a80-de.h> 49#include <dt-bindings/clock/sun9i-a80-usb.h> 50#include <dt-bindings/reset/sun9i-a80-ccu.h> 51#include <dt-bindings/reset/sun9i-a80-de.h> 52#include <dt-bindings/reset/sun9i-a80-usb.h> 53 54/ { 55 #address-cells = <2>; 56 #size-cells = <2>; 57 interrupt-parent = <&gic>; 58 59 cpus { 60 #address-cells = <1>; 61 #size-cells = <0>; 62 63 cpu0: cpu@0 { 64 compatible = "arm,cortex-a7"; 65 device_type = "cpu"; 66 cci-control-port = <&cci_control0>; 67 clock-frequency = <12000000>; 68 enable-method = "allwinner,sun9i-a80-smp"; 69 reg = <0x0>; 70 }; 71 72 cpu1: cpu@1 { 73 compatible = "arm,cortex-a7"; 74 device_type = "cpu"; 75 cci-control-port = <&cci_control0>; 76 clock-frequency = <12000000>; 77 enable-method = "allwinner,sun9i-a80-smp"; 78 reg = <0x1>; 79 }; 80 81 cpu2: cpu@2 { 82 compatible = "arm,cortex-a7"; 83 device_type = "cpu"; 84 cci-control-port = <&cci_control0>; 85 clock-frequency = <12000000>; 86 enable-method = "allwinner,sun9i-a80-smp"; 87 reg = <0x2>; 88 }; 89 90 cpu3: cpu@3 { 91 compatible = "arm,cortex-a7"; 92 device_type = "cpu"; 93 cci-control-port = <&cci_control0>; 94 clock-frequency = <12000000>; 95 enable-method = "allwinner,sun9i-a80-smp"; 96 reg = <0x3>; 97 }; 98 99 cpu4: cpu@100 { 100 compatible = "arm,cortex-a15"; 101 device_type = "cpu"; 102 cci-control-port = <&cci_control1>; 103 clock-frequency = <18000000>; 104 enable-method = "allwinner,sun9i-a80-smp"; 105 reg = <0x100>; 106 }; 107 108 cpu5: cpu@101 { 109 compatible = "arm,cortex-a15"; 110 device_type = "cpu"; 111 cci-control-port = <&cci_control1>; 112 clock-frequency = <18000000>; 113 enable-method = "allwinner,sun9i-a80-smp"; 114 reg = <0x101>; 115 }; 116 117 cpu6: cpu@102 { 118 compatible = "arm,cortex-a15"; 119 device_type = "cpu"; 120 cci-control-port = <&cci_control1>; 121 clock-frequency = <18000000>; 122 enable-method = "allwinner,sun9i-a80-smp"; 123 reg = <0x102>; 124 }; 125 126 cpu7: cpu@103 { 127 compatible = "arm,cortex-a15"; 128 device_type = "cpu"; 129 cci-control-port = <&cci_control1>; 130 clock-frequency = <18000000>; 131 enable-method = "allwinner,sun9i-a80-smp"; 132 reg = <0x103>; 133 }; 134 }; 135 136 timer { 137 compatible = "arm,armv7-timer"; 138 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 139 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 140 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 141 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 142 clock-frequency = <24000000>; 143 arm,cpu-registers-not-fw-configured; 144 }; 145 146 clocks { 147 #address-cells = <1>; 148 #size-cells = <1>; 149 /* 150 * map 64 bit address range down to 32 bits, 151 * as the peripherals are all under 512MB. 152 */ 153 ranges = <0 0 0 0x20000000>; 154 155 /* 156 * This clock is actually configurable from the PRCM address 157 * space. The external 24M oscillator can be turned off, and 158 * the clock switched to an internal 16M RC oscillator. Under 159 * normal operation there's no reason to do this, and the 160 * default is to use the external good one, so just model this 161 * as a fixed clock. Also it is not entirely clear if the 162 * osc24M mux in the PRCM affects the entire clock tree, which 163 * would also throw all the PLL clock rates off, or just the 164 * downstream clocks in the PRCM. 165 */ 166 osc24M: clk-24M { 167 #clock-cells = <0>; 168 compatible = "fixed-clock"; 169 clock-frequency = <24000000>; 170 clock-output-names = "osc24M"; 171 }; 172 173 /* 174 * The 32k clock is from an external source, normally the 175 * AC100 codec/RTC chip. This serves as a placeholder for 176 * board dts files to specify the source. 177 */ 178 osc32k: clk-32k { 179 #clock-cells = <0>; 180 compatible = "fixed-factor-clock"; 181 clock-div = <1>; 182 clock-mult = <1>; 183 clock-output-names = "osc32k"; 184 }; 185 186 cpus_clk: clk@8001410 { 187 compatible = "allwinner,sun9i-a80-cpus-clk"; 188 reg = <0x08001410 0x4>; 189 #clock-cells = <0>; 190 clocks = <&osc32k>, <&osc24M>, 191 <&ccu CLK_PLL_PERIPH0>, 192 <&ccu CLK_PLL_AUDIO>; 193 clock-output-names = "cpus"; 194 }; 195 196 ahbs: clk-ahbs { 197 compatible = "fixed-factor-clock"; 198 #clock-cells = <0>; 199 clock-div = <1>; 200 clock-mult = <1>; 201 clocks = <&cpus_clk>; 202 clock-output-names = "ahbs"; 203 }; 204 205 apbs: clk@800141c { 206 compatible = "allwinner,sun8i-a23-apb0-clk"; 207 reg = <0x0800141c 0x4>; 208 #clock-cells = <0>; 209 clocks = <&ahbs>; 210 clock-output-names = "apbs"; 211 }; 212 213 apbs_gates: clk@8001428 { 214 compatible = "allwinner,sun9i-a80-apbs-gates-clk"; 215 reg = <0x08001428 0x4>; 216 #clock-cells = <1>; 217 clocks = <&apbs>; 218 clock-indices = <0>, <1>, 219 <2>, <3>, 220 <4>, <5>, 221 <6>, <7>, 222 <12>, <13>, 223 <16>, <17>, 224 <18>, <20>; 225 clock-output-names = "apbs_pio", "apbs_ir", 226 "apbs_timer", "apbs_rsb", 227 "apbs_uart", "apbs_1wire", 228 "apbs_i2c0", "apbs_i2c1", 229 "apbs_ps2_0", "apbs_ps2_1", 230 "apbs_dma", "apbs_i2s0", 231 "apbs_i2s1", "apbs_twd"; 232 }; 233 234 r_1wire_clk: clk@8001450 { 235 reg = <0x08001450 0x4>; 236 #clock-cells = <0>; 237 compatible = "allwinner,sun4i-a10-mod0-clk"; 238 clocks = <&osc32k>, <&osc24M>; 239 clock-output-names = "r_1wire"; 240 }; 241 242 r_ir_clk: clk@8001454 { 243 reg = <0x08001454 0x4>; 244 #clock-cells = <0>; 245 compatible = "allwinner,sun4i-a10-mod0-clk"; 246 clocks = <&osc32k>, <&osc24M>; 247 clock-output-names = "r_ir"; 248 }; 249 }; 250 251 de: display-engine { 252 compatible = "allwinner,sun9i-a80-display-engine"; 253 allwinner,pipelines = <&fe0>, <&fe1>; 254 status = "disabled"; 255 }; 256 257 soc { 258 compatible = "simple-bus"; 259 #address-cells = <1>; 260 #size-cells = <1>; 261 /* 262 * map 64 bit address range down to 32 bits, 263 * as the peripherals are all under 512MB. 264 */ 265 ranges = <0 0 0 0x20000000>; 266 267 sram_b: sram@20000 { 268 /* 256 KiB secure SRAM at 0x20000 */ 269 compatible = "mmio-sram"; 270 reg = <0x00020000 0x40000>; 271 272 #address-cells = <1>; 273 #size-cells = <1>; 274 ranges = <0 0x00020000 0x40000>; 275 276 smp-sram@1000 { 277 /* 278 * This is checked by BROM to determine if 279 * cpu0 should jump to SMP entry vector 280 */ 281 compatible = "allwinner,sun9i-a80-smp-sram"; 282 reg = <0x1000 0x8>; 283 }; 284 }; 285 286 ehci0: usb@a00000 { 287 compatible = "allwinner,sun9i-a80-ehci", "generic-ehci"; 288 reg = <0x00a00000 0x100>; 289 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 290 clocks = <&usb_clocks CLK_BUS_HCI0>; 291 resets = <&usb_clocks RST_USB0_HCI>; 292 phys = <&usbphy1>; 293 phy-names = "usb"; 294 status = "disabled"; 295 }; 296 297 ohci0: usb@a00400 { 298 compatible = "allwinner,sun9i-a80-ohci", "generic-ohci"; 299 reg = <0x00a00400 0x100>; 300 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 301 clocks = <&usb_clocks CLK_BUS_HCI0>, 302 <&usb_clocks CLK_USB_OHCI0>; 303 resets = <&usb_clocks RST_USB0_HCI>; 304 phys = <&usbphy1>; 305 phy-names = "usb"; 306 status = "disabled"; 307 }; 308 309 usbphy1: phy@a00800 { 310 compatible = "allwinner,sun9i-a80-usb-phy"; 311 reg = <0x00a00800 0x4>; 312 clocks = <&usb_clocks CLK_USB0_PHY>; 313 clock-names = "phy"; 314 resets = <&usb_clocks RST_USB0_PHY>; 315 reset-names = "phy"; 316 status = "disabled"; 317 #phy-cells = <0>; 318 }; 319 320 ehci1: usb@a01000 { 321 compatible = "allwinner,sun9i-a80-ehci", "generic-ehci"; 322 reg = <0x00a01000 0x100>; 323 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 324 clocks = <&usb_clocks CLK_BUS_HCI1>; 325 resets = <&usb_clocks RST_USB1_HCI>; 326 phys = <&usbphy2>; 327 phy-names = "usb"; 328 status = "disabled"; 329 }; 330 331 usbphy2: phy@a01800 { 332 compatible = "allwinner,sun9i-a80-usb-phy"; 333 reg = <0x00a01800 0x4>; 334 clocks = <&usb_clocks CLK_USB1_HSIC>, 335 <&usb_clocks CLK_USB_HSIC>, 336 <&usb_clocks CLK_USB1_PHY>; 337 clock-names = "hsic_480M", 338 "hsic_12M", 339 "phy"; 340 resets = <&usb_clocks RST_USB1_HSIC>, 341 <&usb_clocks RST_USB1_PHY>; 342 reset-names = "hsic", 343 "phy"; 344 status = "disabled"; 345 #phy-cells = <0>; 346 /* usb1 is always used with HSIC */ 347 phy_type = "hsic"; 348 }; 349 350 ehci2: usb@a02000 { 351 compatible = "allwinner,sun9i-a80-ehci", "generic-ehci"; 352 reg = <0x00a02000 0x100>; 353 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 354 clocks = <&usb_clocks CLK_BUS_HCI2>; 355 resets = <&usb_clocks RST_USB2_HCI>; 356 phys = <&usbphy3>; 357 phy-names = "usb"; 358 status = "disabled"; 359 }; 360 361 ohci2: usb@a02400 { 362 compatible = "allwinner,sun9i-a80-ohci", "generic-ohci"; 363 reg = <0x00a02400 0x100>; 364 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 365 clocks = <&usb_clocks CLK_BUS_HCI2>, 366 <&usb_clocks CLK_USB_OHCI2>; 367 resets = <&usb_clocks RST_USB2_HCI>; 368 phys = <&usbphy3>; 369 phy-names = "usb"; 370 status = "disabled"; 371 }; 372 373 usbphy3: phy@a02800 { 374 compatible = "allwinner,sun9i-a80-usb-phy"; 375 reg = <0x00a02800 0x4>; 376 clocks = <&usb_clocks CLK_USB2_HSIC>, 377 <&usb_clocks CLK_USB_HSIC>, 378 <&usb_clocks CLK_USB2_PHY>; 379 clock-names = "hsic_480M", 380 "hsic_12M", 381 "phy"; 382 resets = <&usb_clocks RST_USB2_HSIC>, 383 <&usb_clocks RST_USB2_PHY>; 384 reset-names = "hsic", 385 "phy"; 386 status = "disabled"; 387 #phy-cells = <0>; 388 }; 389 390 usb_clocks: clock@a08000 { 391 compatible = "allwinner,sun9i-a80-usb-clks"; 392 reg = <0x00a08000 0x8>; 393 clocks = <&ccu CLK_BUS_USB>, <&osc24M>; 394 clock-names = "bus", "hosc"; 395 #clock-cells = <1>; 396 #reset-cells = <1>; 397 }; 398 399 cpucfg@1700000 { 400 compatible = "allwinner,sun9i-a80-cpucfg"; 401 reg = <0x01700000 0x100>; 402 }; 403 404 mmc0: mmc@1c0f000 { 405 compatible = "allwinner,sun9i-a80-mmc"; 406 reg = <0x01c0f000 0x1000>; 407 clocks = <&mmc_config_clk 0>, <&ccu CLK_MMC0>, 408 <&ccu CLK_MMC0_OUTPUT>, 409 <&ccu CLK_MMC0_SAMPLE>; 410 clock-names = "ahb", "mmc", "output", "sample"; 411 resets = <&mmc_config_clk 0>; 412 reset-names = "ahb"; 413 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 414 status = "disabled"; 415 #address-cells = <1>; 416 #size-cells = <0>; 417 }; 418 419 mmc1: mmc@1c10000 { 420 compatible = "allwinner,sun9i-a80-mmc"; 421 reg = <0x01c10000 0x1000>; 422 clocks = <&mmc_config_clk 1>, <&ccu CLK_MMC1>, 423 <&ccu CLK_MMC1_OUTPUT>, 424 <&ccu CLK_MMC1_SAMPLE>; 425 clock-names = "ahb", "mmc", "output", "sample"; 426 resets = <&mmc_config_clk 1>; 427 reset-names = "ahb"; 428 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 429 status = "disabled"; 430 #address-cells = <1>; 431 #size-cells = <0>; 432 }; 433 434 mmc2: mmc@1c11000 { 435 compatible = "allwinner,sun9i-a80-mmc"; 436 reg = <0x01c11000 0x1000>; 437 clocks = <&mmc_config_clk 2>, <&ccu CLK_MMC2>, 438 <&ccu CLK_MMC2_OUTPUT>, 439 <&ccu CLK_MMC2_SAMPLE>; 440 clock-names = "ahb", "mmc", "output", "sample"; 441 resets = <&mmc_config_clk 2>; 442 reset-names = "ahb"; 443 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 444 status = "disabled"; 445 #address-cells = <1>; 446 #size-cells = <0>; 447 }; 448 449 mmc3: mmc@1c12000 { 450 compatible = "allwinner,sun9i-a80-mmc"; 451 reg = <0x01c12000 0x1000>; 452 clocks = <&mmc_config_clk 3>, <&ccu CLK_MMC3>, 453 <&ccu CLK_MMC3_OUTPUT>, 454 <&ccu CLK_MMC3_SAMPLE>; 455 clock-names = "ahb", "mmc", "output", "sample"; 456 resets = <&mmc_config_clk 3>; 457 reset-names = "ahb"; 458 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 459 status = "disabled"; 460 #address-cells = <1>; 461 #size-cells = <0>; 462 }; 463 464 mmc_config_clk: clk@1c13000 { 465 compatible = "allwinner,sun9i-a80-mmc-config-clk"; 466 reg = <0x01c13000 0x10>; 467 clocks = <&ccu CLK_BUS_MMC>; 468 clock-names = "ahb"; 469 resets = <&ccu RST_BUS_MMC>; 470 reset-names = "ahb"; 471 #clock-cells = <1>; 472 #reset-cells = <1>; 473 clock-output-names = "mmc0_config", "mmc1_config", 474 "mmc2_config", "mmc3_config"; 475 }; 476 477 gic: interrupt-controller@1c41000 { 478 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; 479 reg = <0x01c41000 0x1000>, 480 <0x01c42000 0x2000>, 481 <0x01c44000 0x2000>, 482 <0x01c46000 0x2000>; 483 interrupt-controller; 484 #interrupt-cells = <3>; 485 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 486 }; 487 488 cci: cci@1c90000 { 489 compatible = "arm,cci-400"; 490 #address-cells = <1>; 491 #size-cells = <1>; 492 reg = <0x01c90000 0x1000>; 493 ranges = <0x0 0x01c90000 0x10000>; 494 495 cci_control0: slave-if@4000 { 496 compatible = "arm,cci-400-ctrl-if"; 497 interface-type = "ace"; 498 reg = <0x4000 0x1000>; 499 }; 500 501 cci_control1: slave-if@5000 { 502 compatible = "arm,cci-400-ctrl-if"; 503 interface-type = "ace"; 504 reg = <0x5000 0x1000>; 505 }; 506 507 pmu@9000 { 508 compatible = "arm,cci-400-pmu,r1"; 509 reg = <0x9000 0x5000>; 510 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 511 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 512 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 513 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 515 }; 516 }; 517 518 de_clocks: clock@3000000 { 519 compatible = "allwinner,sun9i-a80-de-clks"; 520 reg = <0x03000000 0x30>; 521 clocks = <&ccu CLK_DE>, 522 <&ccu CLK_SDRAM>, 523 <&ccu CLK_BUS_DE>; 524 clock-names = "mod", 525 "dram", 526 "bus"; 527 resets = <&ccu RST_BUS_DE>; 528 #clock-cells = <1>; 529 #reset-cells = <1>; 530 }; 531 532 fe0: display-frontend@3100000 { 533 compatible = "allwinner,sun9i-a80-display-frontend"; 534 reg = <0x03100000 0x40000>; 535 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 536 clocks = <&de_clocks CLK_BUS_FE0>, <&de_clocks CLK_FE0>, 537 <&de_clocks CLK_DRAM_FE0>; 538 clock-names = "ahb", "mod", 539 "ram"; 540 resets = <&de_clocks RST_FE0>; 541 542 ports { 543 #address-cells = <1>; 544 #size-cells = <0>; 545 546 fe0_out: port@1 { 547 #address-cells = <1>; 548 #size-cells = <0>; 549 reg = <1>; 550 551 fe0_out_deu0: endpoint@0 { 552 reg = <0>; 553 remote-endpoint = <&deu0_in_fe0>; 554 }; 555 }; 556 }; 557 }; 558 559 fe1: display-frontend@3140000 { 560 compatible = "allwinner,sun9i-a80-display-frontend"; 561 reg = <0x03140000 0x40000>; 562 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 563 clocks = <&de_clocks CLK_BUS_FE1>, <&de_clocks CLK_FE1>, 564 <&de_clocks CLK_DRAM_FE1>; 565 clock-names = "ahb", "mod", 566 "ram"; 567 resets = <&de_clocks RST_FE0>; 568 569 ports { 570 #address-cells = <1>; 571 #size-cells = <0>; 572 573 fe1_out: port@1 { 574 #address-cells = <1>; 575 #size-cells = <0>; 576 reg = <1>; 577 578 fe1_out_deu1: endpoint@0 { 579 reg = <0>; 580 remote-endpoint = <&deu1_in_fe1>; 581 }; 582 }; 583 }; 584 }; 585 586 be0: display-backend@3200000 { 587 compatible = "allwinner,sun9i-a80-display-backend"; 588 reg = <0x03200000 0x40000>; 589 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 590 clocks = <&de_clocks CLK_BUS_BE0>, <&de_clocks CLK_BE0>, 591 <&de_clocks CLK_DRAM_BE0>; 592 clock-names = "ahb", "mod", 593 "ram"; 594 resets = <&de_clocks RST_BE0>; 595 596 ports { 597 #address-cells = <1>; 598 #size-cells = <0>; 599 600 be0_in: port@0 { 601 #address-cells = <1>; 602 #size-cells = <0>; 603 reg = <0>; 604 605 be0_in_deu0: endpoint@0 { 606 reg = <0>; 607 remote-endpoint = <&deu0_out_be0>; 608 }; 609 610 be0_in_deu1: endpoint@1 { 611 reg = <1>; 612 remote-endpoint = <&deu1_out_be0>; 613 }; 614 }; 615 616 be0_out: port@1 { 617 #address-cells = <1>; 618 #size-cells = <0>; 619 reg = <1>; 620 621 be0_out_drc0: endpoint@0 { 622 reg = <0>; 623 remote-endpoint = <&drc0_in_be0>; 624 }; 625 }; 626 }; 627 }; 628 629 be1: display-backend@3240000 { 630 compatible = "allwinner,sun9i-a80-display-backend"; 631 reg = <0x03240000 0x40000>; 632 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 633 clocks = <&de_clocks CLK_BUS_BE1>, <&de_clocks CLK_BE1>, 634 <&de_clocks CLK_DRAM_BE1>; 635 clock-names = "ahb", "mod", 636 "ram"; 637 resets = <&de_clocks RST_BE1>; 638 639 ports { 640 #address-cells = <1>; 641 #size-cells = <0>; 642 643 be1_in: port@0 { 644 #address-cells = <1>; 645 #size-cells = <0>; 646 reg = <0>; 647 648 be1_in_deu0: endpoint@0 { 649 reg = <0>; 650 remote-endpoint = <&deu0_out_be1>; 651 }; 652 653 be1_in_deu1: endpoint@1 { 654 reg = <1>; 655 remote-endpoint = <&deu1_out_be1>; 656 }; 657 }; 658 659 be1_out: port@1 { 660 #address-cells = <1>; 661 #size-cells = <0>; 662 reg = <1>; 663 664 be1_out_drc1: endpoint@0 { 665 reg = <0>; 666 remote-endpoint = <&drc1_in_be1>; 667 }; 668 }; 669 }; 670 }; 671 672 deu0: deu@3300000 { 673 compatible = "allwinner,sun9i-a80-deu"; 674 reg = <0x03300000 0x40000>; 675 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 676 clocks = <&de_clocks CLK_BUS_DEU0>, 677 <&de_clocks CLK_IEP_DEU0>, 678 <&de_clocks CLK_DRAM_DEU0>; 679 clock-names = "ahb", 680 "mod", 681 "ram"; 682 resets = <&de_clocks RST_DEU0>; 683 684 ports { 685 #address-cells = <1>; 686 #size-cells = <0>; 687 688 deu0_in: port@0 { 689 #address-cells = <1>; 690 #size-cells = <0>; 691 reg = <0>; 692 693 deu0_in_fe0: endpoint@0 { 694 reg = <0>; 695 remote-endpoint = <&fe0_out_deu0>; 696 }; 697 }; 698 699 deu0_out: port@1 { 700 #address-cells = <1>; 701 #size-cells = <0>; 702 reg = <1>; 703 704 deu0_out_be0: endpoint@0 { 705 reg = <0>; 706 remote-endpoint = <&be0_in_deu0>; 707 }; 708 709 deu0_out_be1: endpoint@1 { 710 reg = <1>; 711 remote-endpoint = <&be1_in_deu0>; 712 }; 713 }; 714 }; 715 }; 716 717 deu1: deu@3340000 { 718 compatible = "allwinner,sun9i-a80-deu"; 719 reg = <0x03340000 0x40000>; 720 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 721 clocks = <&de_clocks CLK_BUS_DEU1>, 722 <&de_clocks CLK_IEP_DEU1>, 723 <&de_clocks CLK_DRAM_DEU1>; 724 clock-names = "ahb", 725 "mod", 726 "ram"; 727 resets = <&de_clocks RST_DEU1>; 728 729 ports { 730 #address-cells = <1>; 731 #size-cells = <0>; 732 733 deu1_in: port@0 { 734 #address-cells = <1>; 735 #size-cells = <0>; 736 reg = <0>; 737 738 deu1_in_fe1: endpoint@0 { 739 reg = <0>; 740 remote-endpoint = <&fe1_out_deu1>; 741 }; 742 }; 743 744 deu1_out: port@1 { 745 #address-cells = <1>; 746 #size-cells = <0>; 747 reg = <1>; 748 749 deu1_out_be0: endpoint@0 { 750 reg = <0>; 751 remote-endpoint = <&be0_in_deu1>; 752 }; 753 754 deu1_out_be1: endpoint@1 { 755 reg = <1>; 756 remote-endpoint = <&be1_in_deu1>; 757 }; 758 }; 759 }; 760 }; 761 762 drc0: drc@3400000 { 763 compatible = "allwinner,sun9i-a80-drc"; 764 reg = <0x03400000 0x40000>; 765 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 766 clocks = <&de_clocks CLK_BUS_DRC0>, 767 <&de_clocks CLK_IEP_DRC0>, 768 <&de_clocks CLK_DRAM_DRC0>; 769 clock-names = "ahb", 770 "mod", 771 "ram"; 772 resets = <&de_clocks RST_DRC0>; 773 774 ports { 775 #address-cells = <1>; 776 #size-cells = <0>; 777 778 drc0_in: port@0 { 779 #address-cells = <1>; 780 #size-cells = <0>; 781 reg = <0>; 782 783 drc0_in_be0: endpoint@0 { 784 reg = <0>; 785 remote-endpoint = <&be0_out_drc0>; 786 }; 787 }; 788 789 drc0_out: port@1 { 790 #address-cells = <1>; 791 #size-cells = <0>; 792 reg = <1>; 793 794 drc0_out_tcon0: endpoint@0 { 795 reg = <0>; 796 remote-endpoint = <&tcon0_in_drc0>; 797 }; 798 }; 799 }; 800 }; 801 802 drc1: drc@3440000 { 803 compatible = "allwinner,sun9i-a80-drc"; 804 reg = <0x03440000 0x40000>; 805 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 806 clocks = <&de_clocks CLK_BUS_DRC1>, 807 <&de_clocks CLK_IEP_DRC1>, 808 <&de_clocks CLK_DRAM_DRC1>; 809 clock-names = "ahb", 810 "mod", 811 "ram"; 812 resets = <&de_clocks RST_DRC1>; 813 814 ports { 815 #address-cells = <1>; 816 #size-cells = <0>; 817 818 drc1_in: port@0 { 819 #address-cells = <1>; 820 #size-cells = <0>; 821 reg = <0>; 822 823 drc1_in_be1: endpoint@0 { 824 reg = <0>; 825 remote-endpoint = <&be1_out_drc1>; 826 }; 827 }; 828 829 drc1_out: port@1 { 830 #address-cells = <1>; 831 #size-cells = <0>; 832 reg = <1>; 833 834 drc1_out_tcon1: endpoint@0 { 835 reg = <0>; 836 remote-endpoint = <&tcon1_in_drc1>; 837 }; 838 }; 839 }; 840 }; 841 842 tcon0: lcd-controller@3c00000 { 843 compatible = "allwinner,sun9i-a80-tcon-lcd"; 844 reg = <0x03c00000 0x10000>; 845 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 846 clocks = <&ccu CLK_BUS_LCD0>, <&ccu CLK_LCD0>; 847 clock-names = "ahb", "tcon-ch0"; 848 resets = <&ccu RST_BUS_LCD0>, <&ccu RST_BUS_EDP>; 849 reset-names = "lcd", "edp"; 850 clock-output-names = "tcon0-pixel-clock"; 851 852 ports { 853 #address-cells = <1>; 854 #size-cells = <0>; 855 856 tcon0_in: port@0 { 857 #address-cells = <1>; 858 #size-cells = <0>; 859 reg = <0>; 860 861 tcon0_in_drc0: endpoint@0 { 862 reg = <0>; 863 remote-endpoint = <&drc0_out_tcon0>; 864 }; 865 }; 866 867 tcon0_out: port@1 { 868 #address-cells = <1>; 869 #size-cells = <0>; 870 reg = <1>; 871 }; 872 }; 873 }; 874 875 tcon1: lcd-controller@3c10000 { 876 compatible = "allwinner,sun9i-a80-tcon-tv"; 877 reg = <0x03c10000 0x10000>; 878 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 879 clocks = <&ccu CLK_BUS_LCD1>, <&ccu CLK_LCD1>; 880 clock-names = "ahb", "tcon-ch1"; 881 resets = <&ccu RST_BUS_LCD1>, <&ccu RST_BUS_EDP>; 882 reset-names = "lcd", "edp"; 883 884 ports { 885 #address-cells = <1>; 886 #size-cells = <0>; 887 888 tcon1_in: port@0 { 889 #address-cells = <1>; 890 #size-cells = <0>; 891 reg = <0>; 892 893 tcon1_in_drc1: endpoint@0 { 894 reg = <0>; 895 remote-endpoint = <&drc1_out_tcon1>; 896 }; 897 }; 898 899 tcon1_out: port@1 { 900 #address-cells = <1>; 901 #size-cells = <0>; 902 reg = <1>; 903 }; 904 }; 905 }; 906 907 ccu: clock@6000000 { 908 compatible = "allwinner,sun9i-a80-ccu"; 909 reg = <0x06000000 0x800>; 910 clocks = <&osc24M>, <&osc32k>; 911 clock-names = "hosc", "losc"; 912 #clock-cells = <1>; 913 #reset-cells = <1>; 914 }; 915 916 timer@6000c00 { 917 compatible = "allwinner,sun4i-a10-timer"; 918 reg = <0x06000c00 0xa0>; 919 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 920 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 921 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 922 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 923 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 924 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 925 926 clocks = <&osc24M>; 927 }; 928 929 wdt: watchdog@6000ca0 { 930 compatible = "allwinner,sun6i-a31-wdt"; 931 reg = <0x06000ca0 0x20>; 932 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 933 }; 934 935 pio: pinctrl@6000800 { 936 compatible = "allwinner,sun9i-a80-pinctrl"; 937 reg = <0x06000800 0x400>; 938 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 939 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 940 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 941 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 942 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 943 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>; 944 clock-names = "apb", "hosc", "losc"; 945 gpio-controller; 946 interrupt-controller; 947 #interrupt-cells = <3>; 948 #size-cells = <0>; 949 #gpio-cells = <3>; 950 951 i2c3_pins: i2c3-pins { 952 pins = "PG10", "PG11"; 953 function = "i2c3"; 954 }; 955 956 lcd0_rgb888_pins: lcd0-rgb888-pins { 957 pins = "PD0", "PD1", "PD2", "PD3", 958 "PD4", "PD5", "PD6", "PD7", 959 "PD8", "PD9", "PD10", "PD11", 960 "PD12", "PD13", "PD14", "PD15", 961 "PD16", "PD17", "PD18", "PD19", 962 "PD20", "PD21", "PD22", "PD23", 963 "PD24", "PD25", "PD26", "PD27"; 964 function = "lcd0"; 965 }; 966 967 mmc0_pins: mmc0-pins { 968 pins = "PF0", "PF1" ,"PF2", "PF3", 969 "PF4", "PF5"; 970 function = "mmc0"; 971 drive-strength = <30>; 972 bias-pull-up; 973 }; 974 975 mmc1_pins: mmc1-pins { 976 pins = "PG0", "PG1" ,"PG2", "PG3", 977 "PG4", "PG5"; 978 function = "mmc1"; 979 drive-strength = <30>; 980 bias-pull-up; 981 }; 982 983 mmc2_8bit_pins: mmc2-8bit-pins { 984 pins = "PC6", "PC7", "PC8", "PC9", 985 "PC10", "PC11", "PC12", 986 "PC13", "PC14", "PC15", 987 "PC16"; 988 function = "mmc2"; 989 drive-strength = <30>; 990 bias-pull-up; 991 }; 992 993 uart0_ph_pins: uart0-ph-pins { 994 pins = "PH12", "PH13"; 995 function = "uart0"; 996 }; 997 998 uart4_pins: uart4-pins { 999 pins = "PG12", "PG13", "PG14", "PG15"; 1000 function = "uart4"; 1001 }; 1002 }; 1003 1004 uart0: serial@7000000 { 1005 compatible = "snps,dw-apb-uart"; 1006 reg = <0x07000000 0x400>; 1007 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 1008 reg-shift = <2>; 1009 reg-io-width = <4>; 1010 clocks = <&ccu CLK_BUS_UART0>; 1011 resets = <&ccu RST_BUS_UART0>; 1012 status = "disabled"; 1013 }; 1014 1015 uart1: serial@7000400 { 1016 compatible = "snps,dw-apb-uart"; 1017 reg = <0x07000400 0x400>; 1018 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 1019 reg-shift = <2>; 1020 reg-io-width = <4>; 1021 clocks = <&ccu CLK_BUS_UART1>; 1022 resets = <&ccu RST_BUS_UART1>; 1023 status = "disabled"; 1024 }; 1025 1026 uart2: serial@7000800 { 1027 compatible = "snps,dw-apb-uart"; 1028 reg = <0x07000800 0x400>; 1029 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 1030 reg-shift = <2>; 1031 reg-io-width = <4>; 1032 clocks = <&ccu CLK_BUS_UART2>; 1033 resets = <&ccu RST_BUS_UART2>; 1034 status = "disabled"; 1035 }; 1036 1037 uart3: serial@7000c00 { 1038 compatible = "snps,dw-apb-uart"; 1039 reg = <0x07000c00 0x400>; 1040 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1041 reg-shift = <2>; 1042 reg-io-width = <4>; 1043 clocks = <&ccu CLK_BUS_UART3>; 1044 resets = <&ccu RST_BUS_UART3>; 1045 status = "disabled"; 1046 }; 1047 1048 uart4: serial@7001000 { 1049 compatible = "snps,dw-apb-uart"; 1050 reg = <0x07001000 0x400>; 1051 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1052 reg-shift = <2>; 1053 reg-io-width = <4>; 1054 clocks = <&ccu CLK_BUS_UART4>; 1055 resets = <&ccu RST_BUS_UART4>; 1056 status = "disabled"; 1057 }; 1058 1059 uart5: serial@7001400 { 1060 compatible = "snps,dw-apb-uart"; 1061 reg = <0x07001400 0x400>; 1062 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1063 reg-shift = <2>; 1064 reg-io-width = <4>; 1065 clocks = <&ccu CLK_BUS_UART5>; 1066 resets = <&ccu RST_BUS_UART5>; 1067 status = "disabled"; 1068 }; 1069 1070 i2c0: i2c@7002800 { 1071 compatible = "allwinner,sun6i-a31-i2c"; 1072 reg = <0x07002800 0x400>; 1073 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1074 clocks = <&ccu CLK_BUS_I2C0>; 1075 resets = <&ccu RST_BUS_I2C0>; 1076 status = "disabled"; 1077 #address-cells = <1>; 1078 #size-cells = <0>; 1079 }; 1080 1081 i2c1: i2c@7002c00 { 1082 compatible = "allwinner,sun6i-a31-i2c"; 1083 reg = <0x07002c00 0x400>; 1084 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1085 clocks = <&ccu CLK_BUS_I2C1>; 1086 resets = <&ccu RST_BUS_I2C1>; 1087 status = "disabled"; 1088 #address-cells = <1>; 1089 #size-cells = <0>; 1090 }; 1091 1092 i2c2: i2c@7003000 { 1093 compatible = "allwinner,sun6i-a31-i2c"; 1094 reg = <0x07003000 0x400>; 1095 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1096 clocks = <&ccu CLK_BUS_I2C2>; 1097 resets = <&ccu RST_BUS_I2C2>; 1098 status = "disabled"; 1099 #address-cells = <1>; 1100 #size-cells = <0>; 1101 }; 1102 1103 i2c3: i2c@7003400 { 1104 compatible = "allwinner,sun6i-a31-i2c"; 1105 reg = <0x07003400 0x400>; 1106 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1107 clocks = <&ccu CLK_BUS_I2C3>; 1108 resets = <&ccu RST_BUS_I2C3>; 1109 status = "disabled"; 1110 #address-cells = <1>; 1111 #size-cells = <0>; 1112 }; 1113 1114 i2c4: i2c@7003800 { 1115 compatible = "allwinner,sun6i-a31-i2c"; 1116 reg = <0x07003800 0x400>; 1117 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1118 clocks = <&ccu CLK_BUS_I2C4>; 1119 resets = <&ccu RST_BUS_I2C4>; 1120 status = "disabled"; 1121 #address-cells = <1>; 1122 #size-cells = <0>; 1123 }; 1124 1125 r_wdt: watchdog@8001000 { 1126 compatible = "allwinner,sun6i-a31-wdt"; 1127 reg = <0x08001000 0x20>; 1128 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 1129 }; 1130 1131 prcm@8001400 { 1132 compatible = "allwinner,sun9i-a80-prcm"; 1133 reg = <0x08001400 0x200>; 1134 }; 1135 1136 apbs_rst: reset@80014b0 { 1137 reg = <0x080014b0 0x4>; 1138 compatible = "allwinner,sun6i-a31-clock-reset"; 1139 #reset-cells = <1>; 1140 }; 1141 1142 nmi_intc: interrupt-controller@80015a0 { 1143 compatible = "allwinner,sun9i-a80-nmi"; 1144 interrupt-controller; 1145 #interrupt-cells = <2>; 1146 reg = <0x080015a0 0xc>; 1147 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1148 }; 1149 1150 r_ir: ir@8002000 { 1151 compatible = "allwinner,sun5i-a13-ir"; 1152 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1153 pinctrl-names = "default"; 1154 pinctrl-0 = <&r_ir_pins>; 1155 clocks = <&apbs_gates 1>, <&r_ir_clk>; 1156 clock-names = "apb", "ir"; 1157 resets = <&apbs_rst 1>; 1158 reg = <0x08002000 0x40>; 1159 status = "disabled"; 1160 }; 1161 1162 r_uart: serial@8002800 { 1163 compatible = "snps,dw-apb-uart"; 1164 reg = <0x08002800 0x400>; 1165 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 1166 reg-shift = <2>; 1167 reg-io-width = <4>; 1168 clocks = <&apbs_gates 4>; 1169 resets = <&apbs_rst 4>; 1170 status = "disabled"; 1171 }; 1172 1173 r_pio: pinctrl@8002c00 { 1174 compatible = "allwinner,sun9i-a80-r-pinctrl"; 1175 reg = <0x08002c00 0x400>; 1176 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 1177 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 1178 clocks = <&apbs_gates 0>, <&osc24M>, <&osc32k>; 1179 clock-names = "apb", "hosc", "losc"; 1180 resets = <&apbs_rst 0>; 1181 gpio-controller; 1182 interrupt-controller; 1183 #interrupt-cells = <3>; 1184 #gpio-cells = <3>; 1185 1186 r_ir_pins: r-ir-pins { 1187 pins = "PL6"; 1188 function = "s_cir_rx"; 1189 }; 1190 1191 r_rsb_pins: r-rsb-pins { 1192 pins = "PN0", "PN1"; 1193 function = "s_rsb"; 1194 drive-strength = <20>; 1195 bias-pull-up; 1196 }; 1197 }; 1198 1199 r_rsb: i2c@8003400 { 1200 compatible = "allwinner,sun8i-a23-rsb"; 1201 reg = <0x08003400 0x400>; 1202 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 1203 clocks = <&apbs_gates 3>; 1204 clock-frequency = <3000000>; 1205 resets = <&apbs_rst 3>; 1206 pinctrl-names = "default"; 1207 pinctrl-0 = <&r_rsb_pins>; 1208 status = "disabled"; 1209 #address-cells = <1>; 1210 #size-cells = <0>; 1211 }; 1212 }; 1213}; 1214