1// SPDX-License-Identifier: GPL-2.0
2/*
3 *  Copyright (C) 2015 Andrea Merello <adnrea.merello@gmail.com>
4 *  Copyright (C) 2017 Alexander Graf <agraf@suse.de>
5 *
6 *  Based on zynq-zed.dts which is:
7 *  Copyright (C) 2011 - 2014 Xilinx
8 *  Copyright (C) 2012 National Instruments Corp.
9 *
10 */
11
12/dts-v1/;
13/include/ "zynq-7000.dtsi"
14
15/ {
16	compatible = "xlnx,zynq-7000";
17
18	aliases {
19		ethernet0 = &gem0;
20		serial0 = &uart1;
21		serial1 = &uart0;
22		mmc0 = &sdhci0;
23	};
24
25	memory@0 {
26		device_type = "memory";
27		reg = <0x0 0x40000000>;
28	};
29
30	chosen {
31		stdout-path = "serial0:115200n8";
32	};
33
34	gpio-leds {
35		compatible = "gpio-leds";
36		usr-led1 {
37			label = "usr-led1";
38			gpios = <&gpio0 0x0 0x1>;
39			default-state = "off";
40		};
41
42		usr-led2 {
43			label = "usr-led2";
44			gpios = <&gpio0 0x9 0x1>;
45			default-state = "off";
46		};
47	};
48
49	gpio-keys {
50		compatible = "gpio-keys";
51		autorepeat;
52		K1 {
53			label = "K1";
54			gpios = <&gpio0 0x32 0x1>;
55			linux,code = <0x66>;
56			wakeup-source;
57			autorepeat;
58		};
59	};
60};
61
62&clkc {
63	ps-clk-frequency = <33333333>;
64};
65
66&qspi {
67	u-boot,dm-pre-reloc;
68	status = "okay";
69};
70
71&gem0 {
72	status = "okay";
73	phy-mode = "rgmii-id";
74	phy-handle = <&ethernet_phy>;
75
76	ethernet_phy: ethernet-phy@0 {
77	};
78};
79
80&sdhci0 {
81	u-boot,dm-pre-reloc;
82	status = "okay";
83};
84
85&uart0 {
86	u-boot,dm-pre-reloc;
87	status = "okay";
88};
89
90&uart1 {
91	u-boot,dm-pre-reloc;
92	status = "okay";
93};
94
95&usb0 {
96	status = "okay";
97	dr_mode = "host";
98};
99
100&can0 {
101	status = "okay";
102};
103
104&i2c0 {
105	status = "okay";
106	clock-frequency = <400000>;
107
108	stlm75@49 {
109		status = "okay";
110		compatible = "lm75";
111		reg = <0x49>;
112	};
113
114	accelerometer@53 {
115		compatible = "adi,adxl345";
116		reg = <0x53>;
117		interrupt-parent = <&intc>;
118		interrupts = <0x0 0x1e 0x4>;
119	};
120};
121