1 /* SPDX-License-Identifier: GPL-2.0
2 *
3 * Copyright (C) 2020 Marvell International Ltd.
4 *
5 * https://spdx.org/licenses
6 */
7 #ifndef __CSRS_NPA_H__
8 #define __CSRS_NPA_H__
9
10 /**
11 * @file
12 *
13 * Configuration and status register (CSR) address and type definitions for
14 * NPA.
15 *
16 * This file is auto generated. Do not edit.
17 *
18 */
19
20 /**
21 * Enumeration npa_af_int_vec_e
22 *
23 * NPA Admin Function Interrupt Vector Enumeration Enumerates the NPA AF
24 * MSI-X interrupt vectors.
25 */
26 #define NPA_AF_INT_VEC_E_AF_ERR (3)
27 #define NPA_AF_INT_VEC_E_AQ_DONE (2)
28 #define NPA_AF_INT_VEC_E_GEN (1)
29 #define NPA_AF_INT_VEC_E_POISON (4)
30 #define NPA_AF_INT_VEC_E_RVU (0)
31
32 /**
33 * Enumeration npa_aq_comp_e
34 *
35 * NPA Admin Queue Completion Enumeration Enumerates the values of
36 * NPA_AQ_RES_S[COMPCODE].
37 */
38 #define NPA_AQ_COMP_E_CTX_FAULT (4)
39 #define NPA_AQ_COMP_E_CTX_POISON (3)
40 #define NPA_AQ_COMP_E_GOOD (1)
41 #define NPA_AQ_COMP_E_LOCKERR (5)
42 #define NPA_AQ_COMP_E_NOTDONE (0)
43 #define NPA_AQ_COMP_E_SWERR (2)
44
45 /**
46 * Enumeration npa_aq_ctype_e
47 *
48 * NPA Admin Queue Context Type Enumeration Enumerates
49 * NPA_AQ_INST_S[CTYPE] values.
50 */
51 #define NPA_AQ_CTYPE_E_AURA (0)
52 #define NPA_AQ_CTYPE_E_POOL (1)
53
54 /**
55 * Enumeration npa_aq_instop_e
56 *
57 * NPA Admin Queue Opcode Enumeration Enumerates NPA_AQ_INST_S[OP]
58 * values.
59 */
60 #define NPA_AQ_INSTOP_E_INIT (1)
61 #define NPA_AQ_INSTOP_E_LOCK (4)
62 #define NPA_AQ_INSTOP_E_NOP (0)
63 #define NPA_AQ_INSTOP_E_READ (3)
64 #define NPA_AQ_INSTOP_E_UNLOCK (5)
65 #define NPA_AQ_INSTOP_E_WRITE (2)
66
67 /**
68 * Enumeration npa_aura_err_int_e
69 *
70 * NPA Aura Error Interrupt Enumeration Enumerates the bit index of
71 * NPA_AURA_S[ERR_INT], and NPA_AURA_S[ERR_INT_ENA].
72 */
73 #define NPA_AURA_ERR_INT_E_AURA_ADD_OVER (1)
74 #define NPA_AURA_ERR_INT_E_AURA_ADD_UNDER (2)
75 #define NPA_AURA_ERR_INT_E_AURA_FREE_UNDER (0)
76 #define NPA_AURA_ERR_INT_E_POOL_DIS (3)
77 #define NPA_AURA_ERR_INT_E_RX(a) (0 + (a))
78
79 /**
80 * Enumeration npa_bpintf_e
81 *
82 * NPA Backpressure Interface Enumeration Enumerates index of
83 * NPA_AURA_S[BP_ENA].
84 */
85 #define NPA_BPINTF_E_NIXX_RX(a) (0 + (a))
86
87 /**
88 * Enumeration npa_inpq_e
89 *
90 * NPA Input Queue Enumeration Enumerates ALLOC/FREE input queues from
91 * coprocessors.
92 */
93 #define NPA_INPQ_E_AURA_OP (0xe)
94 #define NPA_INPQ_E_BPHY (7)
95 #define NPA_INPQ_E_DPI (6)
96 #define NPA_INPQ_E_INTERNAL_RSV (0xf)
97 #define NPA_INPQ_E_NIXX_RX(a) (0 + 2 * (a))
98 #define NPA_INPQ_E_NIXX_TX(a) (1 + 2 * (a))
99 #define NPA_INPQ_E_RX(a) (0 + (a))
100 #define NPA_INPQ_E_SSO (4)
101 #define NPA_INPQ_E_TIM (5)
102
103 /**
104 * Enumeration npa_lf_int_vec_e
105 *
106 * NPA Local Function Interrupt Vector Enumeration Enumerates the NPA
107 * MSI-X interrupt vectors per LF.
108 */
109 #define NPA_LF_INT_VEC_E_ERR_INT (0x40)
110 #define NPA_LF_INT_VEC_E_POISON (0x41)
111 #define NPA_LF_INT_VEC_E_QINTX(a) (0 + (a))
112
113 /**
114 * Enumeration npa_ndc0_port_e
115 *
116 * NPA NDC0 Port Enumeration Enumerates NPA NDC0 (NDC_IDX_E::NPA_U(0))
117 * ports and the PORT index of NDC_AF_PORT()_RT()_RW()_REQ_PC and
118 * NDC_AF_PORT()_RT()_RW()_LAT_PC.
119 */
120 #define NPA_NDC0_PORT_E_AURA0 (0)
121 #define NPA_NDC0_PORT_E_AURA1 (1)
122 #define NPA_NDC0_PORT_E_POOL0 (2)
123 #define NPA_NDC0_PORT_E_POOL1 (3)
124 #define NPA_NDC0_PORT_E_STACK0 (4)
125 #define NPA_NDC0_PORT_E_STACK1 (5)
126
127 /**
128 * Enumeration npa_pool_err_int_e
129 *
130 * NPA Pool Error Interrupt Enumeration Enumerates the bit index of
131 * NPA_POOL_S[ERR_INT] and NPA_POOL_S[ERR_INT_ENA].
132 */
133 #define NPA_POOL_ERR_INT_E_OVFLS (0)
134 #define NPA_POOL_ERR_INT_E_PERR (2)
135 #define NPA_POOL_ERR_INT_E_RX(a) (0 + (a))
136 #define NPA_POOL_ERR_INT_E_RANGE (1)
137
138 /**
139 * Structure npa_aq_inst_s
140 *
141 * NPA Admin Queue Instruction Structure This structure specifies the AQ
142 * instruction. Instructions and associated software structures are
143 * stored in memory as little-endian unless NPA_AF_GEN_CFG[AF_BE] is set.
144 * Hardware reads of NPA_AQ_INST_S do not allocate into LLC. Hardware
145 * reads and writes of the context structure selected by [CTYPE], [LF]
146 * and [CINDEX] use the NDC and LLC caching style configured for that
147 * context, i.e.: * NPA_AURA_HW_S reads and writes use
148 * NPA_AF_LF()_AURAS_CFG[CACHING] and NPA_AF_LF()_AURAS_CFG[WAY_MASK]. *
149 * NPA_POOL_HW_S reads and writes use NPA_AURA_HW_S[POOL_CACHING] and
150 * NPA_AURA_HW_S[POOL_WAY_MASK].
151 */
152 union npa_aq_inst_s {
153 u64 u[2];
154 struct npa_aq_inst_s_s {
155 u64 op : 4;
156 u64 ctype : 4;
157 u64 lf : 9;
158 u64 reserved_17_23 : 7;
159 u64 cindex : 20;
160 u64 reserved_44_62 : 19;
161 u64 doneint : 1;
162 u64 res_addr : 64;
163 } s;
164 /* struct npa_aq_inst_s_s cn; */
165 };
166
167 /**
168 * Structure npa_aq_res_s
169 *
170 * NPA Admin Queue Result Structure NPA writes this structure after it
171 * completes the NPA_AQ_INST_S instruction. The result structure is
172 * exactly 16 bytes, and each instruction completion produces exactly one
173 * result structure. Results and associated software structures are
174 * stored in memory as little-endian unless NPA_AF_GEN_CFG[AF_BE] is set.
175 * When [OP] = NPA_AQ_INSTOP_E::INIT, WRITE or READ, this structure is
176 * immediately followed by context read or write data. See
177 * NPA_AQ_INSTOP_E. Hardware writes of NPA_AQ_RES_S and context data
178 * always allocate into LLC. Hardware reads of context data do not
179 * allocate into LLC.
180 */
181 union npa_aq_res_s {
182 u64 u[2];
183 struct npa_aq_res_s_s {
184 u64 op : 4;
185 u64 ctype : 4;
186 u64 compcode : 8;
187 u64 doneint : 1;
188 u64 reserved_17_63 : 47;
189 u64 reserved_64_127 : 64;
190 } s;
191 /* struct npa_aq_res_s_s cn; */
192 };
193
194 /**
195 * Structure npa_aura_op_wdata_s
196 *
197 * NPA Aura Operation Write Data Structure This structure specifies the
198 * write data format of a 64-bit atomic load-and-add to
199 * NPA_LF_AURA_OP_ALLOC() and NPA_LF_POOL_OP_PC, and a 128-bit atomic
200 * CASP operation to NPA_LF_AURA_OP_ALLOC().
201 */
202 union npa_aura_op_wdata_s {
203 u64 u;
204 struct npa_aura_op_wdata_s_s {
205 u64 aura : 20;
206 u64 reserved_20_62 : 43;
207 u64 drop : 1;
208 } s;
209 /* struct npa_aura_op_wdata_s_s cn; */
210 };
211
212 /**
213 * Structure npa_aura_s
214 *
215 * NPA Aura Context Structure This structure specifies the format used by
216 * software with the NPA admin queue to read and write an aura's
217 * NPA_AURA_HW_S structure maintained by hardware in LLC/DRAM.
218 */
219 union npa_aura_s {
220 u64 u[8];
221 struct npa_aura_s_s {
222 u64 pool_addr : 64;
223 u64 ena : 1;
224 u64 reserved_65_66 : 2;
225 u64 pool_caching : 1;
226 u64 pool_way_mask : 16;
227 u64 avg_con : 9;
228 u64 reserved_93 : 1;
229 u64 pool_drop_ena : 1;
230 u64 aura_drop_ena : 1;
231 u64 bp_ena : 2;
232 u64 reserved_98_103 : 6;
233 u64 aura_drop : 8;
234 u64 shift : 6;
235 u64 reserved_118_119 : 2;
236 u64 avg_level : 8;
237 u64 count : 36;
238 u64 reserved_164_167 : 4;
239 u64 nix0_bpid : 9;
240 u64 reserved_177_179 : 3;
241 u64 nix1_bpid : 9;
242 u64 reserved_189_191 : 3;
243 u64 limit : 36;
244 u64 reserved_228_231 : 4;
245 u64 bp : 8;
246 u64 reserved_240_243 : 4;
247 u64 fc_ena : 1;
248 u64 fc_up_crossing : 1;
249 u64 fc_stype : 2;
250 u64 fc_hyst_bits : 4;
251 u64 reserved_252_255 : 4;
252 u64 fc_addr : 64;
253 u64 pool_drop : 8;
254 u64 update_time : 16;
255 u64 err_int : 8;
256 u64 err_int_ena : 8;
257 u64 thresh_int : 1;
258 u64 thresh_int_ena : 1;
259 u64 thresh_up : 1;
260 u64 reserved_363 : 1;
261 u64 thresh_qint_idx : 7;
262 u64 reserved_371 : 1;
263 u64 err_qint_idx : 7;
264 u64 reserved_379_383 : 5;
265 u64 thresh : 36;
266 u64 reserved_420_447 : 28;
267 u64 reserved_448_511 : 64;
268 } s;
269 /* struct npa_aura_s_s cn; */
270 };
271
272 /**
273 * Structure npa_pool_s
274 *
275 * NPA Pool Context Structure This structure specifies the format used by
276 * software with the NPA admin queue to read and write a pool's
277 * NPA_POOL_HW_S structure maintained by hardware in LLC/DRAM.
278 */
279 union npa_pool_s {
280 u64 u[16];
281 struct npa_pool_s_s {
282 u64 stack_base : 64;
283 u64 ena : 1;
284 u64 nat_align : 1;
285 u64 reserved_66_67 : 2;
286 u64 stack_caching : 1;
287 u64 reserved_69_71 : 3;
288 u64 stack_way_mask : 16;
289 u64 buf_offset : 12;
290 u64 reserved_100_103 : 4;
291 u64 buf_size : 11;
292 u64 reserved_115_127 : 13;
293 u64 stack_max_pages : 32;
294 u64 stack_pages : 32;
295 u64 op_pc : 48;
296 u64 reserved_240_255 : 16;
297 u64 stack_offset : 4;
298 u64 reserved_260_263 : 4;
299 u64 shift : 6;
300 u64 reserved_270_271 : 2;
301 u64 avg_level : 8;
302 u64 avg_con : 9;
303 u64 fc_ena : 1;
304 u64 fc_stype : 2;
305 u64 fc_hyst_bits : 4;
306 u64 fc_up_crossing : 1;
307 u64 reserved_297_299 : 3;
308 u64 update_time : 16;
309 u64 reserved_316_319 : 4;
310 u64 fc_addr : 64;
311 u64 ptr_start : 64;
312 u64 ptr_end : 64;
313 u64 reserved_512_535 : 24;
314 u64 err_int : 8;
315 u64 err_int_ena : 8;
316 u64 thresh_int : 1;
317 u64 thresh_int_ena : 1;
318 u64 thresh_up : 1;
319 u64 reserved_555 : 1;
320 u64 thresh_qint_idx : 7;
321 u64 reserved_563 : 1;
322 u64 err_qint_idx : 7;
323 u64 reserved_571_575 : 5;
324 u64 thresh : 36;
325 u64 reserved_612_639 : 28;
326 u64 reserved_640_703 : 64;
327 u64 reserved_704_767 : 64;
328 u64 reserved_768_831 : 64;
329 u64 reserved_832_895 : 64;
330 u64 reserved_896_959 : 64;
331 u64 reserved_960_1023 : 64;
332 } s;
333 /* struct npa_pool_s_s cn; */
334 };
335
336 /**
337 * Structure npa_qint_hw_s
338 *
339 * NPA Queue Interrupt Context Hardware Structure This structure contains
340 * context state maintained by hardware for each queue interrupt (QINT)
341 * in NDC/LLC/DRAM. Software accesses this structure with the
342 * NPA_LF_QINT()_* registers. Hardware maintains a table of
343 * NPA_AF_CONST[QINTS] contiguous NPA_QINT_HW_S structures per LF
344 * starting at IOVA NPA_AF_LF()_QINTS_BASE. Always stored in byte
345 * invariant little-endian format (LE8).
346 */
347 union npa_qint_hw_s {
348 u32 u;
349 struct npa_qint_hw_s_s {
350 u32 count : 22;
351 u32 reserved_22_30 : 9;
352 u32 ena : 1;
353 } s;
354 /* struct npa_qint_hw_s_s cn; */
355 };
356
357 /**
358 * Register (RVU_PF_BAR0) npa_af_active_cycles_pc
359 *
360 * NPA AF Active Cycles Register
361 */
362 union npa_af_active_cycles_pc {
363 u64 u;
364 struct npa_af_active_cycles_pc_s {
365 u64 act_cyc : 64;
366 } s;
367 /* struct npa_af_active_cycles_pc_s cn; */
368 };
369
370 static inline u64 NPA_AF_ACTIVE_CYCLES_PC(void)
371 __attribute__ ((pure, always_inline));
NPA_AF_ACTIVE_CYCLES_PC(void)372 static inline u64 NPA_AF_ACTIVE_CYCLES_PC(void)
373 {
374 return 0xf0;
375 }
376
377 /**
378 * Register (RVU_PF_BAR0) npa_af_aq_base
379 *
380 * NPA AF Admin Queue Base Address Register
381 */
382 union npa_af_aq_base {
383 u64 u;
384 struct npa_af_aq_base_s {
385 u64 reserved_0_6 : 7;
386 u64 base_addr : 46;
387 u64 reserved_53_63 : 11;
388 } s;
389 /* struct npa_af_aq_base_s cn; */
390 };
391
392 static inline u64 NPA_AF_AQ_BASE(void)
393 __attribute__ ((pure, always_inline));
NPA_AF_AQ_BASE(void)394 static inline u64 NPA_AF_AQ_BASE(void)
395 {
396 return 0x610;
397 }
398
399 /**
400 * Register (RVU_PF_BAR0) npa_af_aq_cfg
401 *
402 * NPA AF Admin Queue Configuration Register
403 */
404 union npa_af_aq_cfg {
405 u64 u;
406 struct npa_af_aq_cfg_s {
407 u64 qsize : 4;
408 u64 reserved_4_63 : 60;
409 } s;
410 /* struct npa_af_aq_cfg_s cn; */
411 };
412
413 static inline u64 NPA_AF_AQ_CFG(void)
414 __attribute__ ((pure, always_inline));
NPA_AF_AQ_CFG(void)415 static inline u64 NPA_AF_AQ_CFG(void)
416 {
417 return 0x600;
418 }
419
420 /**
421 * Register (RVU_PF_BAR0) npa_af_aq_done
422 *
423 * NPA AF AQ Done Count Register
424 */
425 union npa_af_aq_done {
426 u64 u;
427 struct npa_af_aq_done_s {
428 u64 done : 20;
429 u64 reserved_20_63 : 44;
430 } s;
431 /* struct npa_af_aq_done_s cn; */
432 };
433
434 static inline u64 NPA_AF_AQ_DONE(void)
435 __attribute__ ((pure, always_inline));
NPA_AF_AQ_DONE(void)436 static inline u64 NPA_AF_AQ_DONE(void)
437 {
438 return 0x650;
439 }
440
441 /**
442 * Register (RVU_PF_BAR0) npa_af_aq_done_ack
443 *
444 * NPA AF AQ Done Count Ack Register This register is written by software
445 * to acknowledge interrupts.
446 */
447 union npa_af_aq_done_ack {
448 u64 u;
449 struct npa_af_aq_done_ack_s {
450 u64 done_ack : 20;
451 u64 reserved_20_63 : 44;
452 } s;
453 /* struct npa_af_aq_done_ack_s cn; */
454 };
455
456 static inline u64 NPA_AF_AQ_DONE_ACK(void)
457 __attribute__ ((pure, always_inline));
NPA_AF_AQ_DONE_ACK(void)458 static inline u64 NPA_AF_AQ_DONE_ACK(void)
459 {
460 return 0x660;
461 }
462
463 /**
464 * Register (RVU_PF_BAR0) npa_af_aq_done_ena_w1c
465 *
466 * NPA AF AQ Done Interrupt Enable Clear Register This register clears
467 * interrupt enable bits.
468 */
469 union npa_af_aq_done_ena_w1c {
470 u64 u;
471 struct npa_af_aq_done_ena_w1c_s {
472 u64 done : 1;
473 u64 reserved_1_63 : 63;
474 } s;
475 /* struct npa_af_aq_done_ena_w1c_s cn; */
476 };
477
478 static inline u64 NPA_AF_AQ_DONE_ENA_W1C(void)
479 __attribute__ ((pure, always_inline));
NPA_AF_AQ_DONE_ENA_W1C(void)480 static inline u64 NPA_AF_AQ_DONE_ENA_W1C(void)
481 {
482 return 0x698;
483 }
484
485 /**
486 * Register (RVU_PF_BAR0) npa_af_aq_done_ena_w1s
487 *
488 * NPA AF AQ Done Interrupt Enable Set Register This register sets
489 * interrupt enable bits.
490 */
491 union npa_af_aq_done_ena_w1s {
492 u64 u;
493 struct npa_af_aq_done_ena_w1s_s {
494 u64 done : 1;
495 u64 reserved_1_63 : 63;
496 } s;
497 /* struct npa_af_aq_done_ena_w1s_s cn; */
498 };
499
500 static inline u64 NPA_AF_AQ_DONE_ENA_W1S(void)
501 __attribute__ ((pure, always_inline));
NPA_AF_AQ_DONE_ENA_W1S(void)502 static inline u64 NPA_AF_AQ_DONE_ENA_W1S(void)
503 {
504 return 0x690;
505 }
506
507 /**
508 * Register (RVU_PF_BAR0) npa_af_aq_done_int
509 *
510 * NPA AF AQ Done Interrupt Register
511 */
512 union npa_af_aq_done_int {
513 u64 u;
514 struct npa_af_aq_done_int_s {
515 u64 done : 1;
516 u64 reserved_1_63 : 63;
517 } s;
518 /* struct npa_af_aq_done_int_s cn; */
519 };
520
521 static inline u64 NPA_AF_AQ_DONE_INT(void)
522 __attribute__ ((pure, always_inline));
NPA_AF_AQ_DONE_INT(void)523 static inline u64 NPA_AF_AQ_DONE_INT(void)
524 {
525 return 0x680;
526 }
527
528 /**
529 * Register (RVU_PF_BAR0) npa_af_aq_done_int_w1s
530 *
531 * INTERNAL: NPA AF AQ Done Interrupt Set Register
532 */
533 union npa_af_aq_done_int_w1s {
534 u64 u;
535 struct npa_af_aq_done_int_w1s_s {
536 u64 done : 1;
537 u64 reserved_1_63 : 63;
538 } s;
539 /* struct npa_af_aq_done_int_w1s_s cn; */
540 };
541
542 static inline u64 NPA_AF_AQ_DONE_INT_W1S(void)
543 __attribute__ ((pure, always_inline));
NPA_AF_AQ_DONE_INT_W1S(void)544 static inline u64 NPA_AF_AQ_DONE_INT_W1S(void)
545 {
546 return 0x688;
547 }
548
549 /**
550 * Register (RVU_PF_BAR0) npa_af_aq_done_timer
551 *
552 * NPA AF Admin Queue Done Interrupt Timer Register Used to debug the
553 * queue interrupt coalescing timer.
554 */
555 union npa_af_aq_done_timer {
556 u64 u;
557 struct npa_af_aq_done_timer_s {
558 u64 count : 16;
559 u64 reserved_16_63 : 48;
560 } s;
561 /* struct npa_af_aq_done_timer_s cn; */
562 };
563
564 static inline u64 NPA_AF_AQ_DONE_TIMER(void)
565 __attribute__ ((pure, always_inline));
NPA_AF_AQ_DONE_TIMER(void)566 static inline u64 NPA_AF_AQ_DONE_TIMER(void)
567 {
568 return 0x670;
569 }
570
571 /**
572 * Register (RVU_PF_BAR0) npa_af_aq_done_wait
573 *
574 * NPA AF AQ Done Interrupt Coalescing Wait Register Specifies the queue
575 * interrupt coalescing settings.
576 */
577 union npa_af_aq_done_wait {
578 u64 u;
579 struct npa_af_aq_done_wait_s {
580 u64 num_wait : 20;
581 u64 reserved_20_31 : 12;
582 u64 time_wait : 16;
583 u64 reserved_48_63 : 16;
584 } s;
585 /* struct npa_af_aq_done_wait_s cn; */
586 };
587
588 static inline u64 NPA_AF_AQ_DONE_WAIT(void)
589 __attribute__ ((pure, always_inline));
NPA_AF_AQ_DONE_WAIT(void)590 static inline u64 NPA_AF_AQ_DONE_WAIT(void)
591 {
592 return 0x640;
593 }
594
595 /**
596 * Register (RVU_PF_BAR0) npa_af_aq_door
597 *
598 * NPA AF Admin Queue Doorbell Register Software writes to this register
599 * to enqueue one or more entries to AQ.
600 */
601 union npa_af_aq_door {
602 u64 u;
603 struct npa_af_aq_door_s {
604 u64 count : 16;
605 u64 reserved_16_63 : 48;
606 } s;
607 /* struct npa_af_aq_door_s cn; */
608 };
609
610 static inline u64 NPA_AF_AQ_DOOR(void)
611 __attribute__ ((pure, always_inline));
NPA_AF_AQ_DOOR(void)612 static inline u64 NPA_AF_AQ_DOOR(void)
613 {
614 return 0x630;
615 }
616
617 /**
618 * Register (RVU_PF_BAR0) npa_af_aq_status
619 *
620 * NPA AF Admin Queue Status Register
621 */
622 union npa_af_aq_status {
623 u64 u;
624 struct npa_af_aq_status_s {
625 u64 reserved_0_3 : 4;
626 u64 head_ptr : 20;
627 u64 reserved_24_35 : 12;
628 u64 tail_ptr : 20;
629 u64 reserved_56_61 : 6;
630 u64 aq_busy : 1;
631 u64 aq_err : 1;
632 } s;
633 struct npa_af_aq_status_cn {
634 u64 reserved_0_3 : 4;
635 u64 head_ptr : 20;
636 u64 reserved_24_31 : 8;
637 u64 reserved_32_35 : 4;
638 u64 tail_ptr : 20;
639 u64 reserved_56_61 : 6;
640 u64 aq_busy : 1;
641 u64 aq_err : 1;
642 } cn;
643 };
644
645 static inline u64 NPA_AF_AQ_STATUS(void)
646 __attribute__ ((pure, always_inline));
NPA_AF_AQ_STATUS(void)647 static inline u64 NPA_AF_AQ_STATUS(void)
648 {
649 return 0x620;
650 }
651
652 /**
653 * Register (RVU_PF_BAR0) npa_af_avg_delay
654 *
655 * NPA AF Queue Average Delay Register
656 */
657 union npa_af_avg_delay {
658 u64 u;
659 struct npa_af_avg_delay_s {
660 u64 avg_dly : 19;
661 u64 reserved_19_23 : 5;
662 u64 avg_timer : 16;
663 u64 reserved_40_62 : 23;
664 u64 avg_timer_dis : 1;
665 } s;
666 /* struct npa_af_avg_delay_s cn; */
667 };
668
669 static inline u64 NPA_AF_AVG_DELAY(void)
670 __attribute__ ((pure, always_inline));
NPA_AF_AVG_DELAY(void)671 static inline u64 NPA_AF_AVG_DELAY(void)
672 {
673 return 0x100;
674 }
675
676 /**
677 * Register (RVU_PF_BAR0) npa_af_bar2_alias#
678 *
679 * INTERNAL: NPA Admin Function BAR2 Alias Registers These registers
680 * alias to the NPA BAR2 registers for the PF and function selected by
681 * NPA_AF_BAR2_SEL[PF_FUNC]. Internal: Not implemented. Placeholder for
682 * bug33464.
683 */
684 union npa_af_bar2_aliasx {
685 u64 u;
686 struct npa_af_bar2_aliasx_s {
687 u64 data : 64;
688 } s;
689 /* struct npa_af_bar2_aliasx_s cn; */
690 };
691
692 static inline u64 NPA_AF_BAR2_ALIASX(u64 a)
693 __attribute__ ((pure, always_inline));
NPA_AF_BAR2_ALIASX(u64 a)694 static inline u64 NPA_AF_BAR2_ALIASX(u64 a)
695 {
696 return 0x9100000 + 8 * a;
697 }
698
699 /**
700 * Register (RVU_PF_BAR0) npa_af_bar2_sel
701 *
702 * INTERNAL: NPA Admin Function BAR2 Select Register This register
703 * configures BAR2 accesses from the NPA_AF_BAR2_ALIAS() registers in
704 * BAR0. Internal: Not implemented. Placeholder for bug33464.
705 */
706 union npa_af_bar2_sel {
707 u64 u;
708 struct npa_af_bar2_sel_s {
709 u64 alias_pf_func : 16;
710 u64 alias_ena : 1;
711 u64 reserved_17_63 : 47;
712 } s;
713 /* struct npa_af_bar2_sel_s cn; */
714 };
715
716 static inline u64 NPA_AF_BAR2_SEL(void)
717 __attribute__ ((pure, always_inline));
NPA_AF_BAR2_SEL(void)718 static inline u64 NPA_AF_BAR2_SEL(void)
719 {
720 return 0x9000000;
721 }
722
723 /**
724 * Register (RVU_PF_BAR0) npa_af_blk_rst
725 *
726 * NPA AF Block Reset Register
727 */
728 union npa_af_blk_rst {
729 u64 u;
730 struct npa_af_blk_rst_s {
731 u64 rst : 1;
732 u64 reserved_1_62 : 62;
733 u64 busy : 1;
734 } s;
735 /* struct npa_af_blk_rst_s cn; */
736 };
737
738 static inline u64 NPA_AF_BLK_RST(void)
739 __attribute__ ((pure, always_inline));
NPA_AF_BLK_RST(void)740 static inline u64 NPA_AF_BLK_RST(void)
741 {
742 return 0;
743 }
744
745 /**
746 * Register (RVU_PF_BAR0) npa_af_bp_test
747 *
748 * INTERNAL: NPA AF Backpressure Test Register
749 */
750 union npa_af_bp_test {
751 u64 u;
752 struct npa_af_bp_test_s {
753 u64 lfsr_freq : 12;
754 u64 reserved_12_15 : 4;
755 u64 bp_cfg : 32;
756 u64 enable : 16;
757 } s;
758 /* struct npa_af_bp_test_s cn; */
759 };
760
761 static inline u64 NPA_AF_BP_TEST(void)
762 __attribute__ ((pure, always_inline));
NPA_AF_BP_TEST(void)763 static inline u64 NPA_AF_BP_TEST(void)
764 {
765 return 0x200;
766 }
767
768 /**
769 * Register (RVU_PF_BAR0) npa_af_const
770 *
771 * NPA AF Constants Register This register contains constants for
772 * software discovery.
773 */
774 union npa_af_const {
775 u64 u;
776 struct npa_af_const_s {
777 u64 stack_page_bytes : 8;
778 u64 stack_page_ptrs : 8;
779 u64 lfs : 12;
780 u64 qints : 12;
781 u64 num_ndc : 3;
782 u64 reserved_43_63 : 21;
783 } s;
784 /* struct npa_af_const_s cn; */
785 };
786
787 static inline u64 NPA_AF_CONST(void)
788 __attribute__ ((pure, always_inline));
NPA_AF_CONST(void)789 static inline u64 NPA_AF_CONST(void)
790 {
791 return 0x10;
792 }
793
794 /**
795 * Register (RVU_PF_BAR0) npa_af_const1
796 *
797 * NPA AF Constants Register 1 This register contains constants for
798 * software discovery.
799 */
800 union npa_af_const1 {
801 u64 u;
802 struct npa_af_const1_s {
803 u64 aura_log2bytes : 4;
804 u64 pool_log2bytes : 4;
805 u64 qint_log2bytes : 4;
806 u64 reserved_12_63 : 52;
807 } s;
808 /* struct npa_af_const1_s cn; */
809 };
810
811 static inline u64 NPA_AF_CONST1(void)
812 __attribute__ ((pure, always_inline));
NPA_AF_CONST1(void)813 static inline u64 NPA_AF_CONST1(void)
814 {
815 return 0x18;
816 }
817
818 /**
819 * Register (RVU_PF_BAR0) npa_af_dtx_filter_ctl
820 *
821 * NPA AF DTX LF Filter Control Register
822 */
823 union npa_af_dtx_filter_ctl {
824 u64 u;
825 struct npa_af_dtx_filter_ctl_s {
826 u64 ena : 1;
827 u64 reserved_1_3 : 3;
828 u64 lf : 7;
829 u64 reserved_11_63 : 53;
830 } s;
831 /* struct npa_af_dtx_filter_ctl_s cn; */
832 };
833
834 static inline u64 NPA_AF_DTX_FILTER_CTL(void)
835 __attribute__ ((pure, always_inline));
NPA_AF_DTX_FILTER_CTL(void)836 static inline u64 NPA_AF_DTX_FILTER_CTL(void)
837 {
838 return 0x10040;
839 }
840
841 /**
842 * Register (RVU_PF_BAR0) npa_af_eco
843 *
844 * INTERNAL: NPA AF ECO Register
845 */
846 union npa_af_eco {
847 u64 u;
848 struct npa_af_eco_s {
849 u64 eco_rw : 32;
850 u64 reserved_32_63 : 32;
851 } s;
852 /* struct npa_af_eco_s cn; */
853 };
854
855 static inline u64 NPA_AF_ECO(void)
856 __attribute__ ((pure, always_inline));
NPA_AF_ECO(void)857 static inline u64 NPA_AF_ECO(void)
858 {
859 return 0x300;
860 }
861
862 /**
863 * Register (RVU_PF_BAR0) npa_af_err_int
864 *
865 * NPA Admin Function Error Interrupt Register
866 */
867 union npa_af_err_int {
868 u64 u;
869 struct npa_af_err_int_s {
870 u64 reserved_0_11 : 12;
871 u64 aq_door_err : 1;
872 u64 aq_res_fault : 1;
873 u64 aq_inst_fault : 1;
874 u64 reserved_15_63 : 49;
875 } s;
876 /* struct npa_af_err_int_s cn; */
877 };
878
879 static inline u64 NPA_AF_ERR_INT(void)
880 __attribute__ ((pure, always_inline));
NPA_AF_ERR_INT(void)881 static inline u64 NPA_AF_ERR_INT(void)
882 {
883 return 0x180;
884 }
885
886 /**
887 * Register (RVU_PF_BAR0) npa_af_err_int_ena_w1c
888 *
889 * NPA Admin Function Error Interrupt Enable Clear Register This register
890 * clears interrupt enable bits.
891 */
892 union npa_af_err_int_ena_w1c {
893 u64 u;
894 struct npa_af_err_int_ena_w1c_s {
895 u64 reserved_0_11 : 12;
896 u64 aq_door_err : 1;
897 u64 aq_res_fault : 1;
898 u64 aq_inst_fault : 1;
899 u64 reserved_15_63 : 49;
900 } s;
901 /* struct npa_af_err_int_ena_w1c_s cn; */
902 };
903
904 static inline u64 NPA_AF_ERR_INT_ENA_W1C(void)
905 __attribute__ ((pure, always_inline));
NPA_AF_ERR_INT_ENA_W1C(void)906 static inline u64 NPA_AF_ERR_INT_ENA_W1C(void)
907 {
908 return 0x198;
909 }
910
911 /**
912 * Register (RVU_PF_BAR0) npa_af_err_int_ena_w1s
913 *
914 * NPA Admin Function Error Interrupt Enable Set Register This register
915 * sets interrupt enable bits.
916 */
917 union npa_af_err_int_ena_w1s {
918 u64 u;
919 struct npa_af_err_int_ena_w1s_s {
920 u64 reserved_0_11 : 12;
921 u64 aq_door_err : 1;
922 u64 aq_res_fault : 1;
923 u64 aq_inst_fault : 1;
924 u64 reserved_15_63 : 49;
925 } s;
926 /* struct npa_af_err_int_ena_w1s_s cn; */
927 };
928
929 static inline u64 NPA_AF_ERR_INT_ENA_W1S(void)
930 __attribute__ ((pure, always_inline));
NPA_AF_ERR_INT_ENA_W1S(void)931 static inline u64 NPA_AF_ERR_INT_ENA_W1S(void)
932 {
933 return 0x190;
934 }
935
936 /**
937 * Register (RVU_PF_BAR0) npa_af_err_int_w1s
938 *
939 * NPA Admin Function Error Interrupt Set Register This register sets
940 * interrupt bits.
941 */
942 union npa_af_err_int_w1s {
943 u64 u;
944 struct npa_af_err_int_w1s_s {
945 u64 reserved_0_11 : 12;
946 u64 aq_door_err : 1;
947 u64 aq_res_fault : 1;
948 u64 aq_inst_fault : 1;
949 u64 reserved_15_63 : 49;
950 } s;
951 /* struct npa_af_err_int_w1s_s cn; */
952 };
953
954 static inline u64 NPA_AF_ERR_INT_W1S(void)
955 __attribute__ ((pure, always_inline));
NPA_AF_ERR_INT_W1S(void)956 static inline u64 NPA_AF_ERR_INT_W1S(void)
957 {
958 return 0x188;
959 }
960
961 /**
962 * Register (RVU_PF_BAR0) npa_af_gen_cfg
963 *
964 * NPA AF General Configuration Register This register provides NPA
965 * control and status information.
966 */
967 union npa_af_gen_cfg {
968 u64 u;
969 struct npa_af_gen_cfg_s {
970 u64 reserved_0 : 1;
971 u64 af_be : 1;
972 u64 reserved_2 : 1;
973 u64 force_cond_clk_en : 1;
974 u64 force_intf_clk_en : 1;
975 u64 reserved_5_9 : 5;
976 u64 ocla_bp : 1;
977 u64 reserved_11 : 1;
978 u64 ratem1 : 4;
979 u64 reserved_16_63 : 48;
980 } s;
981 /* struct npa_af_gen_cfg_s cn; */
982 };
983
984 static inline u64 NPA_AF_GEN_CFG(void)
985 __attribute__ ((pure, always_inline));
NPA_AF_GEN_CFG(void)986 static inline u64 NPA_AF_GEN_CFG(void)
987 {
988 return 0x30;
989 }
990
991 /**
992 * Register (RVU_PF_BAR0) npa_af_gen_int
993 *
994 * NPA AF General Interrupt Register This register contains general error
995 * interrupt summary bits.
996 */
997 union npa_af_gen_int {
998 u64 u;
999 struct npa_af_gen_int_s {
1000 u64 free_dis : 16;
1001 u64 alloc_dis : 16;
1002 u64 unmapped_pf_func : 1;
1003 u64 reserved_33_63 : 31;
1004 } s;
1005 /* struct npa_af_gen_int_s cn; */
1006 };
1007
1008 static inline u64 NPA_AF_GEN_INT(void)
1009 __attribute__ ((pure, always_inline));
NPA_AF_GEN_INT(void)1010 static inline u64 NPA_AF_GEN_INT(void)
1011 {
1012 return 0x140;
1013 }
1014
1015 /**
1016 * Register (RVU_PF_BAR0) npa_af_gen_int_ena_w1c
1017 *
1018 * NPA AF General Interrupt Enable Clear Register This register clears
1019 * interrupt enable bits.
1020 */
1021 union npa_af_gen_int_ena_w1c {
1022 u64 u;
1023 struct npa_af_gen_int_ena_w1c_s {
1024 u64 free_dis : 16;
1025 u64 alloc_dis : 16;
1026 u64 unmapped_pf_func : 1;
1027 u64 reserved_33_63 : 31;
1028 } s;
1029 /* struct npa_af_gen_int_ena_w1c_s cn; */
1030 };
1031
1032 static inline u64 NPA_AF_GEN_INT_ENA_W1C(void)
1033 __attribute__ ((pure, always_inline));
NPA_AF_GEN_INT_ENA_W1C(void)1034 static inline u64 NPA_AF_GEN_INT_ENA_W1C(void)
1035 {
1036 return 0x158;
1037 }
1038
1039 /**
1040 * Register (RVU_PF_BAR0) npa_af_gen_int_ena_w1s
1041 *
1042 * NPA AF General Interrupt Enable Set Register This register sets
1043 * interrupt enable bits.
1044 */
1045 union npa_af_gen_int_ena_w1s {
1046 u64 u;
1047 struct npa_af_gen_int_ena_w1s_s {
1048 u64 free_dis : 16;
1049 u64 alloc_dis : 16;
1050 u64 unmapped_pf_func : 1;
1051 u64 reserved_33_63 : 31;
1052 } s;
1053 /* struct npa_af_gen_int_ena_w1s_s cn; */
1054 };
1055
1056 static inline u64 NPA_AF_GEN_INT_ENA_W1S(void)
1057 __attribute__ ((pure, always_inline));
NPA_AF_GEN_INT_ENA_W1S(void)1058 static inline u64 NPA_AF_GEN_INT_ENA_W1S(void)
1059 {
1060 return 0x150;
1061 }
1062
1063 /**
1064 * Register (RVU_PF_BAR0) npa_af_gen_int_w1s
1065 *
1066 * NPA AF General Interrupt Set Register This register sets interrupt
1067 * bits.
1068 */
1069 union npa_af_gen_int_w1s {
1070 u64 u;
1071 struct npa_af_gen_int_w1s_s {
1072 u64 free_dis : 16;
1073 u64 alloc_dis : 16;
1074 u64 unmapped_pf_func : 1;
1075 u64 reserved_33_63 : 31;
1076 } s;
1077 /* struct npa_af_gen_int_w1s_s cn; */
1078 };
1079
1080 static inline u64 NPA_AF_GEN_INT_W1S(void)
1081 __attribute__ ((pure, always_inline));
NPA_AF_GEN_INT_W1S(void)1082 static inline u64 NPA_AF_GEN_INT_W1S(void)
1083 {
1084 return 0x148;
1085 }
1086
1087 /**
1088 * Register (RVU_PF_BAR0) npa_af_inp_ctl
1089 *
1090 * NPA AF Input Control Register
1091 */
1092 union npa_af_inp_ctl {
1093 u64 u;
1094 struct npa_af_inp_ctl_s {
1095 u64 free_dis : 16;
1096 u64 alloc_dis : 16;
1097 u64 reserved_32_63 : 32;
1098 } s;
1099 /* struct npa_af_inp_ctl_s cn; */
1100 };
1101
1102 static inline u64 NPA_AF_INP_CTL(void)
1103 __attribute__ ((pure, always_inline));
NPA_AF_INP_CTL(void)1104 static inline u64 NPA_AF_INP_CTL(void)
1105 {
1106 return 0xd0;
1107 }
1108
1109 /**
1110 * Register (RVU_PF_BAR0) npa_af_lf#_auras_cfg
1111 *
1112 * NPA AF Local Function Auras Configuration Registers
1113 */
1114 union npa_af_lfx_auras_cfg {
1115 u64 u;
1116 struct npa_af_lfx_auras_cfg_s {
1117 u64 way_mask : 16;
1118 u64 loc_aura_size : 4;
1119 u64 loc_aura_offset : 14;
1120 u64 caching : 1;
1121 u64 be : 1;
1122 u64 rmt_aura_size : 4;
1123 u64 rmt_aura_offset : 14;
1124 u64 rmt_lf : 7;
1125 u64 reserved_61_63 : 3;
1126 } s;
1127 struct npa_af_lfx_auras_cfg_cn96xxp1 {
1128 u64 way_mask : 16;
1129 u64 loc_aura_size : 4;
1130 u64 loc_aura_offset : 14;
1131 u64 caching : 1;
1132 u64 reserved_35 : 1;
1133 u64 rmt_aura_size : 4;
1134 u64 rmt_aura_offset : 14;
1135 u64 rmt_lf : 7;
1136 u64 reserved_61_63 : 3;
1137 } cn96xxp1;
1138 /* struct npa_af_lfx_auras_cfg_s cn96xxp3; */
1139 /* struct npa_af_lfx_auras_cfg_s cnf95xx; */
1140 };
1141
1142 static inline u64 NPA_AF_LFX_AURAS_CFG(u64 a)
1143 __attribute__ ((pure, always_inline));
NPA_AF_LFX_AURAS_CFG(u64 a)1144 static inline u64 NPA_AF_LFX_AURAS_CFG(u64 a)
1145 {
1146 return 0x4000 + 0x40000 * a;
1147 }
1148
1149 /**
1150 * Register (RVU_PF_BAR0) npa_af_lf#_loc_auras_base
1151 *
1152 * NPA AF Local Function Auras Base Registers
1153 */
1154 union npa_af_lfx_loc_auras_base {
1155 u64 u;
1156 struct npa_af_lfx_loc_auras_base_s {
1157 u64 reserved_0_6 : 7;
1158 u64 addr : 46;
1159 u64 reserved_53_63 : 11;
1160 } s;
1161 /* struct npa_af_lfx_loc_auras_base_s cn; */
1162 };
1163
1164 static inline u64 NPA_AF_LFX_LOC_AURAS_BASE(u64 a)
1165 __attribute__ ((pure, always_inline));
NPA_AF_LFX_LOC_AURAS_BASE(u64 a)1166 static inline u64 NPA_AF_LFX_LOC_AURAS_BASE(u64 a)
1167 {
1168 return 0x4010 + 0x40000 * a;
1169 }
1170
1171 /**
1172 * Register (RVU_PF_BAR0) npa_af_lf#_qints_base
1173 *
1174 * NPA AF Local Function Queue Interrupts Base Registers
1175 */
1176 union npa_af_lfx_qints_base {
1177 u64 u;
1178 struct npa_af_lfx_qints_base_s {
1179 u64 reserved_0_6 : 7;
1180 u64 addr : 46;
1181 u64 reserved_53_63 : 11;
1182 } s;
1183 /* struct npa_af_lfx_qints_base_s cn; */
1184 };
1185
1186 static inline u64 NPA_AF_LFX_QINTS_BASE(u64 a)
1187 __attribute__ ((pure, always_inline));
NPA_AF_LFX_QINTS_BASE(u64 a)1188 static inline u64 NPA_AF_LFX_QINTS_BASE(u64 a)
1189 {
1190 return 0x4110 + 0x40000 * a;
1191 }
1192
1193 /**
1194 * Register (RVU_PF_BAR0) npa_af_lf#_qints_cfg
1195 *
1196 * NPA AF Local Function Queue Interrupts Configuration Registers This
1197 * register controls access to the LF's queue interrupt context table in
1198 * LLC/DRAM. The table consists of NPA_AF_CONST[QINTS] contiguous
1199 * NPA_QINT_HW_S structures. The size of each structure is 1 \<\<
1200 * NPA_AF_CONST1[QINT_LOG2BYTES] bytes.
1201 */
1202 union npa_af_lfx_qints_cfg {
1203 u64 u;
1204 struct npa_af_lfx_qints_cfg_s {
1205 u64 reserved_0_19 : 20;
1206 u64 way_mask : 16;
1207 u64 caching : 2;
1208 u64 reserved_38_63 : 26;
1209 } s;
1210 /* struct npa_af_lfx_qints_cfg_s cn; */
1211 };
1212
1213 static inline u64 NPA_AF_LFX_QINTS_CFG(u64 a)
1214 __attribute__ ((pure, always_inline));
NPA_AF_LFX_QINTS_CFG(u64 a)1215 static inline u64 NPA_AF_LFX_QINTS_CFG(u64 a)
1216 {
1217 return 0x4100 + 0x40000 * a;
1218 }
1219
1220 /**
1221 * Register (RVU_PF_BAR0) npa_af_lf_rst
1222 *
1223 * NPA Admin Function LF Reset Register
1224 */
1225 union npa_af_lf_rst {
1226 u64 u;
1227 struct npa_af_lf_rst_s {
1228 u64 lf : 8;
1229 u64 reserved_8_11 : 4;
1230 u64 exec : 1;
1231 u64 reserved_13_63 : 51;
1232 } s;
1233 /* struct npa_af_lf_rst_s cn; */
1234 };
1235
1236 static inline u64 NPA_AF_LF_RST(void)
1237 __attribute__ ((pure, always_inline));
NPA_AF_LF_RST(void)1238 static inline u64 NPA_AF_LF_RST(void)
1239 {
1240 return 0x20;
1241 }
1242
1243 /**
1244 * Register (RVU_PF_BAR0) npa_af_ndc_cfg
1245 *
1246 * NDC AF General Configuration Register This register provides NDC
1247 * control.
1248 */
1249 union npa_af_ndc_cfg {
1250 u64 u;
1251 struct npa_af_ndc_cfg_s {
1252 u64 ndc_bypass : 1;
1253 u64 ndc_ign_pois : 1;
1254 u64 byp_aura : 1;
1255 u64 byp_pool : 1;
1256 u64 byp_stack : 1;
1257 u64 byp_qint : 1;
1258 u64 reserved_6_63 : 58;
1259 } s;
1260 /* struct npa_af_ndc_cfg_s cn; */
1261 };
1262
1263 static inline u64 NPA_AF_NDC_CFG(void)
1264 __attribute__ ((pure, always_inline));
NPA_AF_NDC_CFG(void)1265 static inline u64 NPA_AF_NDC_CFG(void)
1266 {
1267 return 0x40;
1268 }
1269
1270 /**
1271 * Register (RVU_PF_BAR0) npa_af_ndc_sync
1272 *
1273 * NPA AF NDC Sync Register Used to synchronize the NPA NDC.
1274 */
1275 union npa_af_ndc_sync {
1276 u64 u;
1277 struct npa_af_ndc_sync_s {
1278 u64 lf : 8;
1279 u64 reserved_8_11 : 4;
1280 u64 exec : 1;
1281 u64 reserved_13_63 : 51;
1282 } s;
1283 /* struct npa_af_ndc_sync_s cn; */
1284 };
1285
1286 static inline u64 NPA_AF_NDC_SYNC(void)
1287 __attribute__ ((pure, always_inline));
NPA_AF_NDC_SYNC(void)1288 static inline u64 NPA_AF_NDC_SYNC(void)
1289 {
1290 return 0x50;
1291 }
1292
1293 /**
1294 * Register (RVU_PF_BAR0) npa_af_ras
1295 *
1296 * NPA AF RAS Interrupt Register This register is intended for delivery
1297 * of RAS events to the SCP, so should be ignored by OS drivers.
1298 */
1299 union npa_af_ras {
1300 u64 u;
1301 struct npa_af_ras_s {
1302 u64 reserved_0_31 : 32;
1303 u64 aq_ctx_poison : 1;
1304 u64 aq_res_poison : 1;
1305 u64 aq_inst_poison : 1;
1306 u64 reserved_35_63 : 29;
1307 } s;
1308 /* struct npa_af_ras_s cn; */
1309 };
1310
1311 static inline u64 NPA_AF_RAS(void)
1312 __attribute__ ((pure, always_inline));
NPA_AF_RAS(void)1313 static inline u64 NPA_AF_RAS(void)
1314 {
1315 return 0x1a0;
1316 }
1317
1318 /**
1319 * Register (RVU_PF_BAR0) npa_af_ras_ena_w1c
1320 *
1321 * NPA AF RAS Interrupt Enable Clear Register This register clears
1322 * interrupt enable bits.
1323 */
1324 union npa_af_ras_ena_w1c {
1325 u64 u;
1326 struct npa_af_ras_ena_w1c_s {
1327 u64 reserved_0_31 : 32;
1328 u64 aq_ctx_poison : 1;
1329 u64 aq_res_poison : 1;
1330 u64 aq_inst_poison : 1;
1331 u64 reserved_35_63 : 29;
1332 } s;
1333 /* struct npa_af_ras_ena_w1c_s cn; */
1334 };
1335
1336 static inline u64 NPA_AF_RAS_ENA_W1C(void)
1337 __attribute__ ((pure, always_inline));
NPA_AF_RAS_ENA_W1C(void)1338 static inline u64 NPA_AF_RAS_ENA_W1C(void)
1339 {
1340 return 0x1b8;
1341 }
1342
1343 /**
1344 * Register (RVU_PF_BAR0) npa_af_ras_ena_w1s
1345 *
1346 * NPA AF RAS Interrupt Enable Set Register This register sets interrupt
1347 * enable bits.
1348 */
1349 union npa_af_ras_ena_w1s {
1350 u64 u;
1351 struct npa_af_ras_ena_w1s_s {
1352 u64 reserved_0_31 : 32;
1353 u64 aq_ctx_poison : 1;
1354 u64 aq_res_poison : 1;
1355 u64 aq_inst_poison : 1;
1356 u64 reserved_35_63 : 29;
1357 } s;
1358 /* struct npa_af_ras_ena_w1s_s cn; */
1359 };
1360
1361 static inline u64 NPA_AF_RAS_ENA_W1S(void)
1362 __attribute__ ((pure, always_inline));
NPA_AF_RAS_ENA_W1S(void)1363 static inline u64 NPA_AF_RAS_ENA_W1S(void)
1364 {
1365 return 0x1b0;
1366 }
1367
1368 /**
1369 * Register (RVU_PF_BAR0) npa_af_ras_w1s
1370 *
1371 * NPA AF RAS Interrupt Set Register This register sets interrupt bits.
1372 */
1373 union npa_af_ras_w1s {
1374 u64 u;
1375 struct npa_af_ras_w1s_s {
1376 u64 reserved_0_31 : 32;
1377 u64 aq_ctx_poison : 1;
1378 u64 aq_res_poison : 1;
1379 u64 aq_inst_poison : 1;
1380 u64 reserved_35_63 : 29;
1381 } s;
1382 /* struct npa_af_ras_w1s_s cn; */
1383 };
1384
1385 static inline u64 NPA_AF_RAS_W1S(void)
1386 __attribute__ ((pure, always_inline));
NPA_AF_RAS_W1S(void)1387 static inline u64 NPA_AF_RAS_W1S(void)
1388 {
1389 return 0x1a8;
1390 }
1391
1392 /**
1393 * Register (RVU_PF_BAR0) npa_af_rvu_int
1394 *
1395 * NPA AF RVU Interrupt Register This register contains RVU error
1396 * interrupt summary bits.
1397 */
1398 union npa_af_rvu_int {
1399 u64 u;
1400 struct npa_af_rvu_int_s {
1401 u64 unmapped_slot : 1;
1402 u64 reserved_1_63 : 63;
1403 } s;
1404 /* struct npa_af_rvu_int_s cn; */
1405 };
1406
1407 static inline u64 NPA_AF_RVU_INT(void)
1408 __attribute__ ((pure, always_inline));
NPA_AF_RVU_INT(void)1409 static inline u64 NPA_AF_RVU_INT(void)
1410 {
1411 return 0x160;
1412 }
1413
1414 /**
1415 * Register (RVU_PF_BAR0) npa_af_rvu_int_ena_w1c
1416 *
1417 * NPA AF RVU Interrupt Enable Clear Register This register clears
1418 * interrupt enable bits.
1419 */
1420 union npa_af_rvu_int_ena_w1c {
1421 u64 u;
1422 struct npa_af_rvu_int_ena_w1c_s {
1423 u64 unmapped_slot : 1;
1424 u64 reserved_1_63 : 63;
1425 } s;
1426 /* struct npa_af_rvu_int_ena_w1c_s cn; */
1427 };
1428
1429 static inline u64 NPA_AF_RVU_INT_ENA_W1C(void)
1430 __attribute__ ((pure, always_inline));
NPA_AF_RVU_INT_ENA_W1C(void)1431 static inline u64 NPA_AF_RVU_INT_ENA_W1C(void)
1432 {
1433 return 0x178;
1434 }
1435
1436 /**
1437 * Register (RVU_PF_BAR0) npa_af_rvu_int_ena_w1s
1438 *
1439 * NPA AF RVU Interrupt Enable Set Register This register sets interrupt
1440 * enable bits.
1441 */
1442 union npa_af_rvu_int_ena_w1s {
1443 u64 u;
1444 struct npa_af_rvu_int_ena_w1s_s {
1445 u64 unmapped_slot : 1;
1446 u64 reserved_1_63 : 63;
1447 } s;
1448 /* struct npa_af_rvu_int_ena_w1s_s cn; */
1449 };
1450
1451 static inline u64 NPA_AF_RVU_INT_ENA_W1S(void)
1452 __attribute__ ((pure, always_inline));
NPA_AF_RVU_INT_ENA_W1S(void)1453 static inline u64 NPA_AF_RVU_INT_ENA_W1S(void)
1454 {
1455 return 0x170;
1456 }
1457
1458 /**
1459 * Register (RVU_PF_BAR0) npa_af_rvu_int_w1s
1460 *
1461 * NPA AF RVU Interrupt Set Register This register sets interrupt bits.
1462 */
1463 union npa_af_rvu_int_w1s {
1464 u64 u;
1465 struct npa_af_rvu_int_w1s_s {
1466 u64 unmapped_slot : 1;
1467 u64 reserved_1_63 : 63;
1468 } s;
1469 /* struct npa_af_rvu_int_w1s_s cn; */
1470 };
1471
1472 static inline u64 NPA_AF_RVU_INT_W1S(void)
1473 __attribute__ ((pure, always_inline));
NPA_AF_RVU_INT_W1S(void)1474 static inline u64 NPA_AF_RVU_INT_W1S(void)
1475 {
1476 return 0x168;
1477 }
1478
1479 /**
1480 * Register (RVU_PF_BAR0) npa_af_rvu_lf_cfg_debug
1481 *
1482 * NPA Privileged LF Configuration Debug Register This debug register
1483 * allows software to lookup the reverse mapping from VF/PF slot to LF.
1484 * The forward mapping is programmed with NPA_PRIV_LF()_CFG.
1485 */
1486 union npa_af_rvu_lf_cfg_debug {
1487 u64 u;
1488 struct npa_af_rvu_lf_cfg_debug_s {
1489 u64 lf : 12;
1490 u64 lf_valid : 1;
1491 u64 exec : 1;
1492 u64 reserved_14_15 : 2;
1493 u64 slot : 8;
1494 u64 pf_func : 16;
1495 u64 reserved_40_63 : 24;
1496 } s;
1497 /* struct npa_af_rvu_lf_cfg_debug_s cn; */
1498 };
1499
1500 static inline u64 NPA_AF_RVU_LF_CFG_DEBUG(void)
1501 __attribute__ ((pure, always_inline));
NPA_AF_RVU_LF_CFG_DEBUG(void)1502 static inline u64 NPA_AF_RVU_LF_CFG_DEBUG(void)
1503 {
1504 return 0x10030;
1505 }
1506
1507 /**
1508 * Register (RVU_PFVF_BAR2) npa_lf_aura_op_alloc#
1509 *
1510 * NPA Aura Allocate Operation Registers These registers are used to
1511 * allocate one or two pointers from a given aura's pool. A 64-bit atomic
1512 * load-and-add to NPA_LF_AURA_OP_ALLOC(0) allocates a single pointer. A
1513 * 128-bit atomic CASP operation to NPA_LF_AURA_OP_ALLOC(0..1) allocates
1514 * two pointers. The atomic write data format is NPA_AURA_OP_WDATA_S. For
1515 * CASP, the first SWAP word in the write data contains
1516 * NPA_AURA_OP_WDATA_S and the remaining write data words are ignored.
1517 * All other accesses to this register (e.g. reads and writes) are
1518 * RAZ/WI. RSL accesses to this register are RAZ/WI.
1519 */
1520 union npa_lf_aura_op_allocx {
1521 u64 u;
1522 struct npa_lf_aura_op_allocx_s {
1523 u64 addr : 64;
1524 } s;
1525 /* struct npa_lf_aura_op_allocx_s cn; */
1526 };
1527
1528 static inline u64 NPA_LF_AURA_OP_ALLOCX(u64 a)
1529 __attribute__ ((pure, always_inline));
NPA_LF_AURA_OP_ALLOCX(u64 a)1530 static inline u64 NPA_LF_AURA_OP_ALLOCX(u64 a)
1531 {
1532 return 0x10 + 8 * a;
1533 }
1534
1535 /**
1536 * Register (RVU_PFVF_BAR2) npa_lf_aura_op_cnt
1537 *
1538 * NPA LF Aura Count Register A 64-bit atomic load-and-add to this
1539 * register returns a given aura's count. A write sets or adds the aura's
1540 * count. A read is RAZ. RSL accesses to this register are RAZ/WI.
1541 */
1542 union npa_lf_aura_op_cnt {
1543 u64 u;
1544 struct npa_lf_aura_op_cnt_s {
1545 u64 count : 36;
1546 u64 reserved_36_41 : 6;
1547 u64 op_err : 1;
1548 u64 cnt_add : 1;
1549 u64 aura : 20;
1550 } s;
1551 /* struct npa_lf_aura_op_cnt_s cn; */
1552 };
1553
1554 static inline u64 NPA_LF_AURA_OP_CNT(void)
1555 __attribute__ ((pure, always_inline));
NPA_LF_AURA_OP_CNT(void)1556 static inline u64 NPA_LF_AURA_OP_CNT(void)
1557 {
1558 return 0x30;
1559 }
1560
1561 /**
1562 * Register (RVU_PFVF_BAR2) npa_lf_aura_op_free0
1563 *
1564 * NPA LF Aura Free Operation Register 0 A 128-bit write (STP) to
1565 * NPA_LF_AURA_OP_FREE0 and NPA_LF_AURA_OP_FREE1 frees a pointer into a
1566 * given aura's pool. All other accesses to these registers (e.g. reads
1567 * and 64-bit writes) are RAZ/WI. RSL accesses to this register are
1568 * RAZ/WI.
1569 */
1570 union npa_lf_aura_op_free0 {
1571 u64 u;
1572 struct npa_lf_aura_op_free0_s {
1573 u64 addr : 64;
1574 } s;
1575 /* struct npa_lf_aura_op_free0_s cn; */
1576 };
1577
1578 static inline u64 NPA_LF_AURA_OP_FREE0(void)
1579 __attribute__ ((pure, always_inline));
NPA_LF_AURA_OP_FREE0(void)1580 static inline u64 NPA_LF_AURA_OP_FREE0(void)
1581 {
1582 return 0x20;
1583 }
1584
1585 /**
1586 * Register (RVU_PFVF_BAR2) npa_lf_aura_op_free1
1587 *
1588 * NPA LF Aura Free Operation Register 1 See NPA_LF_AURA_OP_FREE0. RSL
1589 * accesses to this register are RAZ/WI.
1590 */
1591 union npa_lf_aura_op_free1 {
1592 u64 u;
1593 struct npa_lf_aura_op_free1_s {
1594 u64 aura : 20;
1595 u64 reserved_20_62 : 43;
1596 u64 fabs : 1;
1597 } s;
1598 /* struct npa_lf_aura_op_free1_s cn; */
1599 };
1600
1601 static inline u64 NPA_LF_AURA_OP_FREE1(void)
1602 __attribute__ ((pure, always_inline));
NPA_LF_AURA_OP_FREE1(void)1603 static inline u64 NPA_LF_AURA_OP_FREE1(void)
1604 {
1605 return 0x28;
1606 }
1607
1608 /**
1609 * Register (RVU_PFVF_BAR2) npa_lf_aura_op_int
1610 *
1611 * NPA LF Aura Interrupt Operation Register A 64-bit atomic load-and-add
1612 * to this register reads
1613 * NPA_AURA_HW_S[ERR_INT,ERR_INT_ENA,THRESH_INT,THRESH_INT_ENA]. A write
1614 * optionally sets or clears these fields. A read is RAZ. RSL accesses
1615 * to this register are RAZ/WI.
1616 */
1617 union npa_lf_aura_op_int {
1618 u64 u;
1619 struct npa_lf_aura_op_int_s {
1620 u64 err_int : 8;
1621 u64 err_int_ena : 8;
1622 u64 thresh_int : 1;
1623 u64 thresh_int_ena : 1;
1624 u64 reserved_18_41 : 24;
1625 u64 op_err : 1;
1626 u64 setop : 1;
1627 u64 aura : 20;
1628 } s;
1629 /* struct npa_lf_aura_op_int_s cn; */
1630 };
1631
1632 static inline u64 NPA_LF_AURA_OP_INT(void)
1633 __attribute__ ((pure, always_inline));
NPA_LF_AURA_OP_INT(void)1634 static inline u64 NPA_LF_AURA_OP_INT(void)
1635 {
1636 return 0x60;
1637 }
1638
1639 /**
1640 * Register (RVU_PFVF_BAR2) npa_lf_aura_op_limit
1641 *
1642 * NPA LF Aura Allocation Limit Register A 64-bit atomic load-and-add to
1643 * this register returns a given aura's limit. A write sets the aura's
1644 * limit. A read is RAZ. RSL accesses to this register are RAZ/WI.
1645 */
1646 union npa_lf_aura_op_limit {
1647 u64 u;
1648 struct npa_lf_aura_op_limit_s {
1649 u64 limit : 36;
1650 u64 reserved_36_41 : 6;
1651 u64 op_err : 1;
1652 u64 reserved_43 : 1;
1653 u64 aura : 20;
1654 } s;
1655 /* struct npa_lf_aura_op_limit_s cn; */
1656 };
1657
1658 static inline u64 NPA_LF_AURA_OP_LIMIT(void)
1659 __attribute__ ((pure, always_inline));
NPA_LF_AURA_OP_LIMIT(void)1660 static inline u64 NPA_LF_AURA_OP_LIMIT(void)
1661 {
1662 return 0x50;
1663 }
1664
1665 /**
1666 * Register (RVU_PFVF_BAR2) npa_lf_aura_op_thresh
1667 *
1668 * NPA LF Aura Threshold Operation Register A 64-bit atomic load-and-add
1669 * to this register reads NPA_AURA_HW_S[THRESH_UP,THRESH]. A write to the
1670 * register writes NPA_AURA_HW_S[THRESH_UP,THRESH] and recomputes
1671 * NPA_AURA_HW_S[THRESH_INT]. A read is RAZ. RSL accesses to this
1672 * register are RAZ/WI.
1673 */
1674 union npa_lf_aura_op_thresh {
1675 u64 u;
1676 struct npa_lf_aura_op_thresh_s {
1677 u64 thresh : 36;
1678 u64 reserved_36_41 : 6;
1679 u64 op_err : 1;
1680 u64 thresh_up : 1;
1681 u64 aura : 20;
1682 } s;
1683 /* struct npa_lf_aura_op_thresh_s cn; */
1684 };
1685
1686 static inline u64 NPA_LF_AURA_OP_THRESH(void)
1687 __attribute__ ((pure, always_inline));
NPA_LF_AURA_OP_THRESH(void)1688 static inline u64 NPA_LF_AURA_OP_THRESH(void)
1689 {
1690 return 0x70;
1691 }
1692
1693 /**
1694 * Register (RVU_PFVF_BAR2) npa_lf_err_int
1695 *
1696 * NPA LF Error Interrupt Register
1697 */
1698 union npa_lf_err_int {
1699 u64 u;
1700 struct npa_lf_err_int_s {
1701 u64 aura_dis : 1;
1702 u64 aura_oor : 1;
1703 u64 reserved_2 : 1;
1704 u64 rmt_req_oor : 1;
1705 u64 reserved_4_11 : 8;
1706 u64 aura_fault : 1;
1707 u64 pool_fault : 1;
1708 u64 stack_fault : 1;
1709 u64 qint_fault : 1;
1710 u64 reserved_16_63 : 48;
1711 } s;
1712 /* struct npa_lf_err_int_s cn; */
1713 };
1714
1715 static inline u64 NPA_LF_ERR_INT(void)
1716 __attribute__ ((pure, always_inline));
NPA_LF_ERR_INT(void)1717 static inline u64 NPA_LF_ERR_INT(void)
1718 {
1719 return 0x200;
1720 }
1721
1722 /**
1723 * Register (RVU_PFVF_BAR2) npa_lf_err_int_ena_w1c
1724 *
1725 * NPA LF Error Interrupt Enable Clear Register This register clears
1726 * interrupt enable bits.
1727 */
1728 union npa_lf_err_int_ena_w1c {
1729 u64 u;
1730 struct npa_lf_err_int_ena_w1c_s {
1731 u64 aura_dis : 1;
1732 u64 aura_oor : 1;
1733 u64 reserved_2 : 1;
1734 u64 rmt_req_oor : 1;
1735 u64 reserved_4_11 : 8;
1736 u64 aura_fault : 1;
1737 u64 pool_fault : 1;
1738 u64 stack_fault : 1;
1739 u64 qint_fault : 1;
1740 u64 reserved_16_63 : 48;
1741 } s;
1742 /* struct npa_lf_err_int_ena_w1c_s cn; */
1743 };
1744
1745 static inline u64 NPA_LF_ERR_INT_ENA_W1C(void)
1746 __attribute__ ((pure, always_inline));
NPA_LF_ERR_INT_ENA_W1C(void)1747 static inline u64 NPA_LF_ERR_INT_ENA_W1C(void)
1748 {
1749 return 0x210;
1750 }
1751
1752 /**
1753 * Register (RVU_PFVF_BAR2) npa_lf_err_int_ena_w1s
1754 *
1755 * NPA LF Error Interrupt Enable Set Register This register sets
1756 * interrupt enable bits.
1757 */
1758 union npa_lf_err_int_ena_w1s {
1759 u64 u;
1760 struct npa_lf_err_int_ena_w1s_s {
1761 u64 aura_dis : 1;
1762 u64 aura_oor : 1;
1763 u64 reserved_2 : 1;
1764 u64 rmt_req_oor : 1;
1765 u64 reserved_4_11 : 8;
1766 u64 aura_fault : 1;
1767 u64 pool_fault : 1;
1768 u64 stack_fault : 1;
1769 u64 qint_fault : 1;
1770 u64 reserved_16_63 : 48;
1771 } s;
1772 /* struct npa_lf_err_int_ena_w1s_s cn; */
1773 };
1774
1775 static inline u64 NPA_LF_ERR_INT_ENA_W1S(void)
1776 __attribute__ ((pure, always_inline));
NPA_LF_ERR_INT_ENA_W1S(void)1777 static inline u64 NPA_LF_ERR_INT_ENA_W1S(void)
1778 {
1779 return 0x218;
1780 }
1781
1782 /**
1783 * Register (RVU_PFVF_BAR2) npa_lf_err_int_w1s
1784 *
1785 * NPA LF Error Interrupt Set Register This register sets interrupt bits.
1786 */
1787 union npa_lf_err_int_w1s {
1788 u64 u;
1789 struct npa_lf_err_int_w1s_s {
1790 u64 aura_dis : 1;
1791 u64 aura_oor : 1;
1792 u64 reserved_2 : 1;
1793 u64 rmt_req_oor : 1;
1794 u64 reserved_4_11 : 8;
1795 u64 aura_fault : 1;
1796 u64 pool_fault : 1;
1797 u64 stack_fault : 1;
1798 u64 qint_fault : 1;
1799 u64 reserved_16_63 : 48;
1800 } s;
1801 /* struct npa_lf_err_int_w1s_s cn; */
1802 };
1803
1804 static inline u64 NPA_LF_ERR_INT_W1S(void)
1805 __attribute__ ((pure, always_inline));
NPA_LF_ERR_INT_W1S(void)1806 static inline u64 NPA_LF_ERR_INT_W1S(void)
1807 {
1808 return 0x208;
1809 }
1810
1811 /**
1812 * Register (RVU_PFVF_BAR2) npa_lf_pool_op_available
1813 *
1814 * NPA LF Pool Available Count Operation Register A 64-bit atomic load-
1815 * and-add to this register returns a given pool's free pointer count.
1816 * Reads and writes are RAZ/WI. RSL accesses to this register are
1817 * RAZ/WI.
1818 */
1819 union npa_lf_pool_op_available {
1820 u64 u;
1821 struct npa_lf_pool_op_available_s {
1822 u64 count : 36;
1823 u64 reserved_36_41 : 6;
1824 u64 op_err : 1;
1825 u64 reserved_43 : 1;
1826 u64 aura : 20;
1827 } s;
1828 /* struct npa_lf_pool_op_available_s cn; */
1829 };
1830
1831 static inline u64 NPA_LF_POOL_OP_AVAILABLE(void)
1832 __attribute__ ((pure, always_inline));
NPA_LF_POOL_OP_AVAILABLE(void)1833 static inline u64 NPA_LF_POOL_OP_AVAILABLE(void)
1834 {
1835 return 0x110;
1836 }
1837
1838 /**
1839 * Register (RVU_PFVF_BAR2) npa_lf_pool_op_int
1840 *
1841 * NPA LF Pool Interrupt Operation Register A 64-bit atomic load-and-add
1842 * to this register reads
1843 * NPA_POOL_S[ERR_INT,ERR_INT_ENA,THRESH_INT,THRESH_INT_ENA]. A write
1844 * optionally sets or clears these fields. A read is RAZ. RSL accesses
1845 * to this register are RAZ/WI.
1846 */
1847 union npa_lf_pool_op_int {
1848 u64 u;
1849 struct npa_lf_pool_op_int_s {
1850 u64 err_int : 8;
1851 u64 err_int_ena : 8;
1852 u64 thresh_int : 1;
1853 u64 thresh_int_ena : 1;
1854 u64 reserved_18_41 : 24;
1855 u64 op_err : 1;
1856 u64 setop : 1;
1857 u64 aura : 20;
1858 } s;
1859 /* struct npa_lf_pool_op_int_s cn; */
1860 };
1861
1862 static inline u64 NPA_LF_POOL_OP_INT(void)
1863 __attribute__ ((pure, always_inline));
NPA_LF_POOL_OP_INT(void)1864 static inline u64 NPA_LF_POOL_OP_INT(void)
1865 {
1866 return 0x160;
1867 }
1868
1869 /**
1870 * Register (RVU_PFVF_BAR2) npa_lf_pool_op_pc
1871 *
1872 * NPA LF Pool Performance Count Register A 64-bit atomic load-and-add to
1873 * this register reads NPA_POOL_S[OP_PC] from a given aura's pool. The
1874 * aura is selected by the atomic write data, whose format is
1875 * NPA_AURA_OP_WDATA_S. Reads and writes are RAZ/WI. RSL accesses to
1876 * this register are RAZ/WI.
1877 */
1878 union npa_lf_pool_op_pc {
1879 u64 u;
1880 struct npa_lf_pool_op_pc_s {
1881 u64 op_pc : 48;
1882 u64 op_err : 1;
1883 u64 reserved_49_63 : 15;
1884 } s;
1885 /* struct npa_lf_pool_op_pc_s cn; */
1886 };
1887
1888 static inline u64 NPA_LF_POOL_OP_PC(void)
1889 __attribute__ ((pure, always_inline));
NPA_LF_POOL_OP_PC(void)1890 static inline u64 NPA_LF_POOL_OP_PC(void)
1891 {
1892 return 0x100;
1893 }
1894
1895 /**
1896 * Register (RVU_PFVF_BAR2) npa_lf_pool_op_ptr_end0
1897 *
1898 * NPA LF Pool Pointer End Operation Register 0 A 128-bit write (STP) to
1899 * the NPA_LF_POOL_OP_PTR_END0 and NPA_LF_POOL_OP_PTR_END1 registers
1900 * writes to a given pool's pointer end value. All other accesses to
1901 * these registers (e.g. reads and 64-bit writes) are RAZ/WI. RSL
1902 * accesses to this register are RAZ/WI.
1903 */
1904 union npa_lf_pool_op_ptr_end0 {
1905 u64 u;
1906 struct npa_lf_pool_op_ptr_end0_s {
1907 u64 ptr_end : 64;
1908 } s;
1909 /* struct npa_lf_pool_op_ptr_end0_s cn; */
1910 };
1911
1912 static inline u64 NPA_LF_POOL_OP_PTR_END0(void)
1913 __attribute__ ((pure, always_inline));
NPA_LF_POOL_OP_PTR_END0(void)1914 static inline u64 NPA_LF_POOL_OP_PTR_END0(void)
1915 {
1916 return 0x130;
1917 }
1918
1919 /**
1920 * Register (RVU_PFVF_BAR2) npa_lf_pool_op_ptr_end1
1921 *
1922 * NPA LF Pool Pointer End Operation Register 1 See
1923 * NPA_LF_POOL_OP_PTR_END0. RSL accesses to this register are RAZ/WI.
1924 */
1925 union npa_lf_pool_op_ptr_end1 {
1926 u64 u;
1927 struct npa_lf_pool_op_ptr_end1_s {
1928 u64 aura : 20;
1929 u64 reserved_20_63 : 44;
1930 } s;
1931 /* struct npa_lf_pool_op_ptr_end1_s cn; */
1932 };
1933
1934 static inline u64 NPA_LF_POOL_OP_PTR_END1(void)
1935 __attribute__ ((pure, always_inline));
NPA_LF_POOL_OP_PTR_END1(void)1936 static inline u64 NPA_LF_POOL_OP_PTR_END1(void)
1937 {
1938 return 0x138;
1939 }
1940
1941 /**
1942 * Register (RVU_PFVF_BAR2) npa_lf_pool_op_ptr_start0
1943 *
1944 * NPA LF Pool Pointer Start Operation Register 0 A 128-bit write (STP)
1945 * to the NPA_LF_POOL_OP_PTR_START0 and NPA_LF_POOL_OP_PTR_START1
1946 * registers writes to a given pool's pointer start value. All other
1947 * accesses to these registers (e.g. reads and 64-bit writes) are RAZ/WI.
1948 * RSL accesses to this register are RAZ/WI.
1949 */
1950 union npa_lf_pool_op_ptr_start0 {
1951 u64 u;
1952 struct npa_lf_pool_op_ptr_start0_s {
1953 u64 ptr_start : 64;
1954 } s;
1955 /* struct npa_lf_pool_op_ptr_start0_s cn; */
1956 };
1957
1958 static inline u64 NPA_LF_POOL_OP_PTR_START0(void)
1959 __attribute__ ((pure, always_inline));
NPA_LF_POOL_OP_PTR_START0(void)1960 static inline u64 NPA_LF_POOL_OP_PTR_START0(void)
1961 {
1962 return 0x120;
1963 }
1964
1965 /**
1966 * Register (RVU_PFVF_BAR2) npa_lf_pool_op_ptr_start1
1967 *
1968 * NPA LF Pool Pointer Start Operation Register 1 See
1969 * NPA_LF_POOL_OP_PTR_START0. RSL accesses to this register are RAZ/WI.
1970 */
1971 union npa_lf_pool_op_ptr_start1 {
1972 u64 u;
1973 struct npa_lf_pool_op_ptr_start1_s {
1974 u64 aura : 20;
1975 u64 reserved_20_63 : 44;
1976 } s;
1977 /* struct npa_lf_pool_op_ptr_start1_s cn; */
1978 };
1979
1980 static inline u64 NPA_LF_POOL_OP_PTR_START1(void)
1981 __attribute__ ((pure, always_inline));
NPA_LF_POOL_OP_PTR_START1(void)1982 static inline u64 NPA_LF_POOL_OP_PTR_START1(void)
1983 {
1984 return 0x128;
1985 }
1986
1987 /**
1988 * Register (RVU_PFVF_BAR2) npa_lf_pool_op_thresh
1989 *
1990 * NPA LF Pool Threshold Operation Register A 64-bit atomic load-and-add
1991 * to this register reads NPA_POOL_S[THRESH_UP,THRESH]. A write to the
1992 * register writes NPA_POOL_S[THRESH_UP,THRESH]. A read is RAZ. RSL
1993 * accesses to this register are RAZ/WI.
1994 */
1995 union npa_lf_pool_op_thresh {
1996 u64 u;
1997 struct npa_lf_pool_op_thresh_s {
1998 u64 thresh : 36;
1999 u64 reserved_36_41 : 6;
2000 u64 op_err : 1;
2001 u64 thresh_up : 1;
2002 u64 aura : 20;
2003 } s;
2004 /* struct npa_lf_pool_op_thresh_s cn; */
2005 };
2006
2007 static inline u64 NPA_LF_POOL_OP_THRESH(void)
2008 __attribute__ ((pure, always_inline));
NPA_LF_POOL_OP_THRESH(void)2009 static inline u64 NPA_LF_POOL_OP_THRESH(void)
2010 {
2011 return 0x170;
2012 }
2013
2014 /**
2015 * Register (RVU_PFVF_BAR2) npa_lf_qint#_cnt
2016 *
2017 * NPA LF Queue Interrupt Count Registers
2018 */
2019 union npa_lf_qintx_cnt {
2020 u64 u;
2021 struct npa_lf_qintx_cnt_s {
2022 u64 count : 22;
2023 u64 reserved_22_63 : 42;
2024 } s;
2025 /* struct npa_lf_qintx_cnt_s cn; */
2026 };
2027
2028 static inline u64 NPA_LF_QINTX_CNT(u64 a)
2029 __attribute__ ((pure, always_inline));
NPA_LF_QINTX_CNT(u64 a)2030 static inline u64 NPA_LF_QINTX_CNT(u64 a)
2031 {
2032 return 0x300 + 0x1000 * a;
2033 }
2034
2035 /**
2036 * Register (RVU_PFVF_BAR2) npa_lf_qint#_ena_w1c
2037 *
2038 * NPA LF Queue Interrupt Enable Clear Registers This register clears
2039 * interrupt enable bits.
2040 */
2041 union npa_lf_qintx_ena_w1c {
2042 u64 u;
2043 struct npa_lf_qintx_ena_w1c_s {
2044 u64 intr : 1;
2045 u64 reserved_1_63 : 63;
2046 } s;
2047 /* struct npa_lf_qintx_ena_w1c_s cn; */
2048 };
2049
2050 static inline u64 NPA_LF_QINTX_ENA_W1C(u64 a)
2051 __attribute__ ((pure, always_inline));
NPA_LF_QINTX_ENA_W1C(u64 a)2052 static inline u64 NPA_LF_QINTX_ENA_W1C(u64 a)
2053 {
2054 return 0x330 + 0x1000 * a;
2055 }
2056
2057 /**
2058 * Register (RVU_PFVF_BAR2) npa_lf_qint#_ena_w1s
2059 *
2060 * NPA LF Queue Interrupt Enable Set Registers This register sets
2061 * interrupt enable bits.
2062 */
2063 union npa_lf_qintx_ena_w1s {
2064 u64 u;
2065 struct npa_lf_qintx_ena_w1s_s {
2066 u64 intr : 1;
2067 u64 reserved_1_63 : 63;
2068 } s;
2069 /* struct npa_lf_qintx_ena_w1s_s cn; */
2070 };
2071
2072 static inline u64 NPA_LF_QINTX_ENA_W1S(u64 a)
2073 __attribute__ ((pure, always_inline));
NPA_LF_QINTX_ENA_W1S(u64 a)2074 static inline u64 NPA_LF_QINTX_ENA_W1S(u64 a)
2075 {
2076 return 0x320 + 0x1000 * a;
2077 }
2078
2079 /**
2080 * Register (RVU_PFVF_BAR2) npa_lf_qint#_int
2081 *
2082 * NPA LF Queue Interrupt Registers
2083 */
2084 union npa_lf_qintx_int {
2085 u64 u;
2086 struct npa_lf_qintx_int_s {
2087 u64 intr : 1;
2088 u64 reserved_1_63 : 63;
2089 } s;
2090 /* struct npa_lf_qintx_int_s cn; */
2091 };
2092
2093 static inline u64 NPA_LF_QINTX_INT(u64 a)
2094 __attribute__ ((pure, always_inline));
NPA_LF_QINTX_INT(u64 a)2095 static inline u64 NPA_LF_QINTX_INT(u64 a)
2096 {
2097 return 0x310 + 0x1000 * a;
2098 }
2099
2100 /**
2101 * Register (RVU_PFVF_BAR2) npa_lf_qint#_int_w1s
2102 *
2103 * INTERNAL: NPA LF Queue Interrupt Set Registers
2104 */
2105 union npa_lf_qintx_int_w1s {
2106 u64 u;
2107 struct npa_lf_qintx_int_w1s_s {
2108 u64 intr : 1;
2109 u64 reserved_1_63 : 63;
2110 } s;
2111 /* struct npa_lf_qintx_int_w1s_s cn; */
2112 };
2113
2114 static inline u64 NPA_LF_QINTX_INT_W1S(u64 a)
2115 __attribute__ ((pure, always_inline));
NPA_LF_QINTX_INT_W1S(u64 a)2116 static inline u64 NPA_LF_QINTX_INT_W1S(u64 a)
2117 {
2118 return 0x318 + 0x1000 * a;
2119 }
2120
2121 /**
2122 * Register (RVU_PFVF_BAR2) npa_lf_ras
2123 *
2124 * NPA LF RAS Interrupt Register
2125 */
2126 union npa_lf_ras {
2127 u64 u;
2128 struct npa_lf_ras_s {
2129 u64 aura_poison : 1;
2130 u64 pool_poison : 1;
2131 u64 stack_poison : 1;
2132 u64 qint_poison : 1;
2133 u64 reserved_4_63 : 60;
2134 } s;
2135 /* struct npa_lf_ras_s cn; */
2136 };
2137
2138 static inline u64 NPA_LF_RAS(void)
2139 __attribute__ ((pure, always_inline));
NPA_LF_RAS(void)2140 static inline u64 NPA_LF_RAS(void)
2141 {
2142 return 0x220;
2143 }
2144
2145 /**
2146 * Register (RVU_PFVF_BAR2) npa_lf_ras_ena_w1c
2147 *
2148 * NPA LF RAS Interrupt Enable Clear Register This register clears
2149 * interrupt enable bits.
2150 */
2151 union npa_lf_ras_ena_w1c {
2152 u64 u;
2153 struct npa_lf_ras_ena_w1c_s {
2154 u64 aura_poison : 1;
2155 u64 pool_poison : 1;
2156 u64 stack_poison : 1;
2157 u64 qint_poison : 1;
2158 u64 reserved_4_63 : 60;
2159 } s;
2160 /* struct npa_lf_ras_ena_w1c_s cn; */
2161 };
2162
2163 static inline u64 NPA_LF_RAS_ENA_W1C(void)
2164 __attribute__ ((pure, always_inline));
NPA_LF_RAS_ENA_W1C(void)2165 static inline u64 NPA_LF_RAS_ENA_W1C(void)
2166 {
2167 return 0x230;
2168 }
2169
2170 /**
2171 * Register (RVU_PFVF_BAR2) npa_lf_ras_ena_w1s
2172 *
2173 * NPA LF RAS Interrupt Enable Set Register This register sets interrupt
2174 * enable bits.
2175 */
2176 union npa_lf_ras_ena_w1s {
2177 u64 u;
2178 struct npa_lf_ras_ena_w1s_s {
2179 u64 aura_poison : 1;
2180 u64 pool_poison : 1;
2181 u64 stack_poison : 1;
2182 u64 qint_poison : 1;
2183 u64 reserved_4_63 : 60;
2184 } s;
2185 /* struct npa_lf_ras_ena_w1s_s cn; */
2186 };
2187
2188 static inline u64 NPA_LF_RAS_ENA_W1S(void)
2189 __attribute__ ((pure, always_inline));
NPA_LF_RAS_ENA_W1S(void)2190 static inline u64 NPA_LF_RAS_ENA_W1S(void)
2191 {
2192 return 0x238;
2193 }
2194
2195 /**
2196 * Register (RVU_PFVF_BAR2) npa_lf_ras_w1s
2197 *
2198 * NPA LF RAS Interrupt Set Register This register sets interrupt bits.
2199 */
2200 union npa_lf_ras_w1s {
2201 u64 u;
2202 struct npa_lf_ras_w1s_s {
2203 u64 aura_poison : 1;
2204 u64 pool_poison : 1;
2205 u64 stack_poison : 1;
2206 u64 qint_poison : 1;
2207 u64 reserved_4_63 : 60;
2208 } s;
2209 /* struct npa_lf_ras_w1s_s cn; */
2210 };
2211
2212 static inline u64 NPA_LF_RAS_W1S(void)
2213 __attribute__ ((pure, always_inline));
NPA_LF_RAS_W1S(void)2214 static inline u64 NPA_LF_RAS_W1S(void)
2215 {
2216 return 0x228;
2217 }
2218
2219 /**
2220 * Register (RVU_PF_BAR0) npa_priv_af_int_cfg
2221 *
2222 * NPA Privileged AF Interrupt Configuration Register
2223 */
2224 union npa_priv_af_int_cfg {
2225 u64 u;
2226 struct npa_priv_af_int_cfg_s {
2227 u64 msix_offset : 11;
2228 u64 reserved_11 : 1;
2229 u64 msix_size : 8;
2230 u64 reserved_20_63 : 44;
2231 } s;
2232 /* struct npa_priv_af_int_cfg_s cn; */
2233 };
2234
2235 static inline u64 NPA_PRIV_AF_INT_CFG(void)
2236 __attribute__ ((pure, always_inline));
NPA_PRIV_AF_INT_CFG(void)2237 static inline u64 NPA_PRIV_AF_INT_CFG(void)
2238 {
2239 return 0x10000;
2240 }
2241
2242 /**
2243 * Register (RVU_PF_BAR0) npa_priv_lf#_cfg
2244 *
2245 * NPA Privileged Local Function Configuration Registers These registers
2246 * allow each NPA local function (LF) to be provisioned to a VF/PF slot
2247 * for RVU. See also NPA_AF_RVU_LF_CFG_DEBUG. Software should read this
2248 * register after write to ensure that the LF is mapped to [PF_FUNC]
2249 * before issuing transactions to the mapped PF and function. [SLOT]
2250 * must be zero. Internal: Hardware ignores [SLOT] and always assumes
2251 * 0x0.
2252 */
2253 union npa_priv_lfx_cfg {
2254 u64 u;
2255 struct npa_priv_lfx_cfg_s {
2256 u64 slot : 8;
2257 u64 pf_func : 16;
2258 u64 reserved_24_62 : 39;
2259 u64 ena : 1;
2260 } s;
2261 /* struct npa_priv_lfx_cfg_s cn; */
2262 };
2263
2264 static inline u64 NPA_PRIV_LFX_CFG(u64 a)
2265 __attribute__ ((pure, always_inline));
NPA_PRIV_LFX_CFG(u64 a)2266 static inline u64 NPA_PRIV_LFX_CFG(u64 a)
2267 {
2268 return 0x10010 + 0x100 * a;
2269 }
2270
2271 /**
2272 * Register (RVU_PF_BAR0) npa_priv_lf#_int_cfg
2273 *
2274 * NPA Privileged LF Interrupt Configuration Registers
2275 */
2276 union npa_priv_lfx_int_cfg {
2277 u64 u;
2278 struct npa_priv_lfx_int_cfg_s {
2279 u64 msix_offset : 11;
2280 u64 reserved_11 : 1;
2281 u64 msix_size : 8;
2282 u64 reserved_20_63 : 44;
2283 } s;
2284 /* struct npa_priv_lfx_int_cfg_s cn; */
2285 };
2286
2287 static inline u64 NPA_PRIV_LFX_INT_CFG(u64 a)
2288 __attribute__ ((pure, always_inline));
NPA_PRIV_LFX_INT_CFG(u64 a)2289 static inline u64 NPA_PRIV_LFX_INT_CFG(u64 a)
2290 {
2291 return 0x10020 + 0x100 * a;
2292 }
2293
2294 #endif /* __CSRS_NPA_H__ */
2295