1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * board/renesas/alt/alt.c
4 *
5 * Copyright (C) 2014, 2015 Renesas Electronics Corporation
6 */
7
8 #include <common.h>
9 #include <cpu_func.h>
10 #include <env.h>
11 #include <hang.h>
12 #include <init.h>
13 #include <malloc.h>
14 #include <dm.h>
15 #include <asm/global_data.h>
16 #include <dm/platform_data/serial_sh.h>
17 #include <env_internal.h>
18 #include <asm/processor.h>
19 #include <asm/mach-types.h>
20 #include <asm/io.h>
21 #include <linux/bitops.h>
22 #include <linux/delay.h>
23 #include <linux/errno.h>
24 #include <asm/arch/sys_proto.h>
25 #include <asm/gpio.h>
26 #include <asm/arch/rmobile.h>
27 #include <asm/arch/rcar-mstp.h>
28 #include <asm/arch/mmc.h>
29 #include <asm/arch/sh_sdhi.h>
30 #include <netdev.h>
31 #include <miiphy.h>
32 #include <i2c.h>
33 #include <div64.h>
34 #include "qos.h"
35
36 DECLARE_GLOBAL_DATA_PTR;
37
s_init(void)38 void s_init(void)
39 {
40 struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
41 struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
42
43 /* Watchdog init */
44 writel(0xA5A5A500, &rwdt->rwtcsra);
45 writel(0xA5A5A500, &swdt->swtcsra);
46
47 /* QoS */
48 qos_init();
49 }
50
51 #define TMU0_MSTP125 BIT(25)
52 #define MMC0_MSTP315 BIT(15)
53
54 #define SD1CKCR 0xE6150078
55 #define SD_97500KHZ 0x7
56
board_early_init_f(void)57 int board_early_init_f(void)
58 {
59 /* TMU */
60 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
61
62 /* Set SD1 to the 97.5MHz */
63 writel(SD_97500KHZ, SD1CKCR);
64
65 return 0;
66 }
67
68 #define ETHERNET_PHY_RESET 56 /* GPIO 1 24 */
69
board_init(void)70 int board_init(void)
71 {
72 /* adress of boot parameters */
73 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
74
75 /* Force ethernet PHY out of reset */
76 gpio_request(ETHERNET_PHY_RESET, "phy_reset");
77 gpio_direction_output(ETHERNET_PHY_RESET, 0);
78 mdelay(20);
79 gpio_direction_output(ETHERNET_PHY_RESET, 1);
80 udelay(1);
81
82 return 0;
83 }
84
dram_init(void)85 int dram_init(void)
86 {
87 if (fdtdec_setup_mem_size_base() != 0)
88 return -EINVAL;
89
90 return 0;
91 }
92
dram_init_banksize(void)93 int dram_init_banksize(void)
94 {
95 fdtdec_setup_memory_banksize();
96
97 return 0;
98 }
99
100 /* KSZ8041RNLI */
101 #define PHY_CONTROL1 0x1E
102 #define PHY_LED_MODE 0xC000
103 #define PHY_LED_MODE_ACK 0x4000
board_phy_config(struct phy_device * phydev)104 int board_phy_config(struct phy_device *phydev)
105 {
106 int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
107 ret &= ~PHY_LED_MODE;
108 ret |= PHY_LED_MODE_ACK;
109 ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
110
111 return 0;
112 }
113
reset_cpu(void)114 void reset_cpu(void)
115 {
116 struct udevice *dev;
117 const u8 pmic_bus = 7;
118 const u8 pmic_addr = 0x58;
119 u8 data;
120 int ret;
121
122 ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev);
123 if (ret)
124 hang();
125
126 ret = dm_i2c_read(dev, 0x13, &data, 1);
127 if (ret)
128 hang();
129
130 data |= BIT(1);
131
132 ret = dm_i2c_write(dev, 0x13, &data, 1);
133 if (ret)
134 hang();
135 }
136
env_get_location(enum env_operation op,int prio)137 enum env_location env_get_location(enum env_operation op, int prio)
138 {
139 const u32 load_magic = 0xb33fc0de;
140
141 /* Block environment access if loaded using JTAG */
142 if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
143 (op != ENVOP_INIT))
144 return ENVL_UNKNOWN;
145
146 if (prio)
147 return ENVL_UNKNOWN;
148
149 return ENVL_SPI_FLASH;
150 }
151