1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Renesas R8A7791 CPG MSSR driver
4 *
5 * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
6 *
7 * Based on the following driver from Linux kernel:
8 * r8a7791 Clock Pulse Generator / Module Standby and Software Reset
9 *
10 * Copyright (C) 2015-2017 Glider bvba
11 *
12 * Based on clk-rcar-gen2.c
13 *
14 * Copyright (C) 2013 Ideas On Board SPRL
15 */
16
17 #include <common.h>
18 #include <clk-uclass.h>
19 #include <dm.h>
20 #include <linux/bitops.h>
21
22 #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
23
24 #include "renesas-cpg-mssr.h"
25 #include "rcar-gen2-cpg.h"
26
27 enum clk_ids {
28 /* Core Clock Outputs exported to DT */
29 LAST_DT_CORE_CLK = R8A7791_CLK_OSC,
30
31 /* External Input Clocks */
32 CLK_EXTAL,
33 CLK_USB_EXTAL,
34
35 /* Internal Core Clocks */
36 CLK_MAIN,
37 CLK_PLL0,
38 CLK_PLL1,
39 CLK_PLL3,
40 CLK_PLL1_DIV2,
41
42 /* Module Clocks */
43 MOD_CLK_BASE
44 };
45
46 static const struct cpg_core_clk r8a7791_core_clks[] = {
47 /* External Clock Inputs */
48 DEF_INPUT("extal", CLK_EXTAL),
49 DEF_INPUT("usb_extal", CLK_USB_EXTAL),
50
51 /* Internal Core Clocks */
52 DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),
53 DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
54 DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
55 DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
56
57 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
58
59 /* Core Clock Outputs */
60 DEF_BASE("z", R8A7791_CLK_Z, CLK_TYPE_GEN2_Z, CLK_PLL0),
61 DEF_BASE("adsp", R8A7791_CLK_ADSP, CLK_TYPE_GEN2_ADSP, CLK_PLL1),
62 DEF_BASE("sdh", R8A7791_CLK_SDH, CLK_TYPE_GEN2_SDH, CLK_PLL1),
63 DEF_BASE("sd0", R8A7791_CLK_SD0, CLK_TYPE_GEN2_SD0, CLK_PLL1),
64 DEF_BASE("qspi", R8A7791_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2),
65 DEF_BASE("rcan", R8A7791_CLK_RCAN, CLK_TYPE_GEN2_RCAN, CLK_USB_EXTAL),
66
67 DEF_FIXED("zg", R8A7791_CLK_ZG, CLK_PLL1, 3, 1),
68 DEF_FIXED("zx", R8A7791_CLK_ZX, CLK_PLL1, 3, 1),
69 DEF_FIXED("zs", R8A7791_CLK_ZS, CLK_PLL1, 6, 1),
70 DEF_FIXED("hp", R8A7791_CLK_HP, CLK_PLL1, 12, 1),
71 DEF_FIXED("i", R8A7791_CLK_I, CLK_PLL1, 2, 1),
72 DEF_FIXED("b", R8A7791_CLK_B, CLK_PLL1, 12, 1),
73 DEF_FIXED("lb", R8A7791_CLK_LB, CLK_PLL1, 24, 1),
74 DEF_FIXED("p", R8A7791_CLK_P, CLK_PLL1, 24, 1),
75 DEF_FIXED("cl", R8A7791_CLK_CL, CLK_PLL1, 48, 1),
76 DEF_FIXED("m2", R8A7791_CLK_M2, CLK_PLL1, 8, 1),
77 DEF_FIXED("zb3", R8A7791_CLK_ZB3, CLK_PLL3, 4, 1),
78 DEF_FIXED("zb3d2", R8A7791_CLK_ZB3D2, CLK_PLL3, 8, 1),
79 DEF_FIXED("ddr", R8A7791_CLK_DDR, CLK_PLL3, 8, 1),
80 DEF_FIXED("mp", R8A7791_CLK_MP, CLK_PLL1_DIV2, 15, 1),
81 DEF_FIXED("cp", R8A7791_CLK_CP, CLK_EXTAL, 2, 1),
82 DEF_FIXED("r", R8A7791_CLK_R, CLK_PLL1, 49152, 1),
83 DEF_FIXED("osc", R8A7791_CLK_OSC, CLK_PLL1, 12288, 1),
84
85 DEF_DIV6P1("sd2", R8A7791_CLK_SD2, CLK_PLL1_DIV2, 0x078),
86 DEF_DIV6P1("sd3", R8A7791_CLK_SD3, CLK_PLL1_DIV2, 0x26c),
87 DEF_DIV6P1("mmc0", R8A7791_CLK_MMC0, CLK_PLL1_DIV2, 0x240),
88 DEF_DIV6P1("ssp", R8A7791_CLK_SSP, CLK_PLL1_DIV2, 0x248),
89 DEF_DIV6P1("ssprs", R8A7791_CLK_SSPRS, CLK_PLL1_DIV2, 0x24c),
90 };
91
92 static const struct mssr_mod_clk r8a7791_mod_clks[] = {
93 DEF_MOD("msiof0", 0, R8A7791_CLK_MP),
94 DEF_MOD("vcp0", 101, R8A7791_CLK_ZS),
95 DEF_MOD("vpc0", 103, R8A7791_CLK_ZS),
96 DEF_MOD("jpu", 106, R8A7791_CLK_M2),
97 DEF_MOD("ssp1", 109, R8A7791_CLK_ZS),
98 DEF_MOD("tmu1", 111, R8A7791_CLK_P),
99 DEF_MOD("3dg", 112, R8A7791_CLK_ZG),
100 DEF_MOD("2d-dmac", 115, R8A7791_CLK_ZS),
101 DEF_MOD("fdp1-1", 118, R8A7791_CLK_ZS),
102 DEF_MOD("fdp1-0", 119, R8A7791_CLK_ZS),
103 DEF_MOD("tmu3", 121, R8A7791_CLK_P),
104 DEF_MOD("tmu2", 122, R8A7791_CLK_P),
105 DEF_MOD("cmt0", 124, R8A7791_CLK_R),
106 DEF_MOD("tmu0", 125, R8A7791_CLK_CP),
107 DEF_MOD("vsp1du1", 127, R8A7791_CLK_ZS),
108 DEF_MOD("vsp1du0", 128, R8A7791_CLK_ZS),
109 DEF_MOD("vsps", 131, R8A7791_CLK_ZS),
110 DEF_MOD("scifa2", 202, R8A7791_CLK_MP),
111 DEF_MOD("scifa1", 203, R8A7791_CLK_MP),
112 DEF_MOD("scifa0", 204, R8A7791_CLK_MP),
113 DEF_MOD("msiof2", 205, R8A7791_CLK_MP),
114 DEF_MOD("scifb0", 206, R8A7791_CLK_MP),
115 DEF_MOD("scifb1", 207, R8A7791_CLK_MP),
116 DEF_MOD("msiof1", 208, R8A7791_CLK_MP),
117 DEF_MOD("scifb2", 216, R8A7791_CLK_MP),
118 DEF_MOD("sys-dmac1", 218, R8A7791_CLK_ZS),
119 DEF_MOD("sys-dmac0", 219, R8A7791_CLK_ZS),
120 DEF_MOD("tpu0", 304, R8A7791_CLK_CP),
121 DEF_MOD("sdhi3", 311, R8A7791_CLK_SD3),
122 DEF_MOD("sdhi2", 312, R8A7791_CLK_SD2),
123 DEF_MOD("sdhi0", 314, R8A7791_CLK_SD0),
124 DEF_MOD("mmcif0", 315, R8A7791_CLK_MMC0),
125 DEF_MOD("iic0", 318, R8A7791_CLK_HP),
126 DEF_MOD("pciec", 319, R8A7791_CLK_MP),
127 DEF_MOD("iic1", 323, R8A7791_CLK_HP),
128 DEF_MOD("usb3.0", 328, R8A7791_CLK_MP),
129 DEF_MOD("cmt1", 329, R8A7791_CLK_R),
130 DEF_MOD("usbhs-dmac0", 330, R8A7791_CLK_HP),
131 DEF_MOD("usbhs-dmac1", 331, R8A7791_CLK_HP),
132 DEF_MOD("rwdt", 402, R8A7791_CLK_R),
133 DEF_MOD("irqc", 407, R8A7791_CLK_CP),
134 DEF_MOD("intc-sys", 408, R8A7791_CLK_ZS),
135 DEF_MOD("audio-dmac1", 501, R8A7791_CLK_HP),
136 DEF_MOD("audio-dmac0", 502, R8A7791_CLK_HP),
137 DEF_MOD("adsp_mod", 506, R8A7791_CLK_ADSP),
138 DEF_MOD("thermal", 522, CLK_EXTAL),
139 DEF_MOD("pwm", 523, R8A7791_CLK_P),
140 DEF_MOD("usb-ehci", 703, R8A7791_CLK_MP),
141 DEF_MOD("usbhs", 704, R8A7791_CLK_HP),
142 DEF_MOD("hscif2", 713, R8A7791_CLK_ZS),
143 DEF_MOD("scif5", 714, R8A7791_CLK_P),
144 DEF_MOD("scif4", 715, R8A7791_CLK_P),
145 DEF_MOD("hscif1", 716, R8A7791_CLK_ZS),
146 DEF_MOD("hscif0", 717, R8A7791_CLK_ZS),
147 DEF_MOD("scif3", 718, R8A7791_CLK_P),
148 DEF_MOD("scif2", 719, R8A7791_CLK_P),
149 DEF_MOD("scif1", 720, R8A7791_CLK_P),
150 DEF_MOD("scif0", 721, R8A7791_CLK_P),
151 DEF_MOD("du1", 723, R8A7791_CLK_ZX),
152 DEF_MOD("du0", 724, R8A7791_CLK_ZX),
153 DEF_MOD("lvds0", 726, R8A7791_CLK_ZX),
154 DEF_MOD("ipmmu-sgx", 800, R8A7791_CLK_ZX),
155 DEF_MOD("mlb", 802, R8A7791_CLK_HP),
156 DEF_MOD("vin2", 809, R8A7791_CLK_ZG),
157 DEF_MOD("vin1", 810, R8A7791_CLK_ZG),
158 DEF_MOD("vin0", 811, R8A7791_CLK_ZG),
159 DEF_MOD("etheravb", 812, R8A7791_CLK_HP),
160 DEF_MOD("ether", 813, R8A7791_CLK_P),
161 DEF_MOD("sata1", 814, R8A7791_CLK_ZS),
162 DEF_MOD("sata0", 815, R8A7791_CLK_ZS),
163 DEF_MOD("gyro-adc", 901, R8A7791_CLK_P),
164 DEF_MOD("gpio7", 904, R8A7791_CLK_CP),
165 DEF_MOD("gpio6", 905, R8A7791_CLK_CP),
166 DEF_MOD("gpio5", 907, R8A7791_CLK_CP),
167 DEF_MOD("gpio4", 908, R8A7791_CLK_CP),
168 DEF_MOD("gpio3", 909, R8A7791_CLK_CP),
169 DEF_MOD("gpio2", 910, R8A7791_CLK_CP),
170 DEF_MOD("gpio1", 911, R8A7791_CLK_CP),
171 DEF_MOD("gpio0", 912, R8A7791_CLK_CP),
172 DEF_MOD("can1", 915, R8A7791_CLK_P),
173 DEF_MOD("can0", 916, R8A7791_CLK_P),
174 DEF_MOD("qspi_mod", 917, R8A7791_CLK_QSPI),
175 DEF_MOD("i2c5", 925, R8A7791_CLK_HP),
176 DEF_MOD("iicdvfs", 926, R8A7791_CLK_CP),
177 DEF_MOD("i2c4", 927, R8A7791_CLK_HP),
178 DEF_MOD("i2c3", 928, R8A7791_CLK_HP),
179 DEF_MOD("i2c2", 929, R8A7791_CLK_HP),
180 DEF_MOD("i2c1", 930, R8A7791_CLK_HP),
181 DEF_MOD("i2c0", 931, R8A7791_CLK_HP),
182 DEF_MOD("ssi-all", 1005, R8A7791_CLK_P),
183 DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
184 DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
185 DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
186 DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
187 DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
188 DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
189 DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
190 DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
191 DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
192 DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
193 DEF_MOD("scu-all", 1017, R8A7791_CLK_P),
194 DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
195 DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
196 DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
197 DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
198 DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
199 DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
200 DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
201 DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
202 DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
203 DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
204 DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
205 DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
206 DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
207 DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
208 DEF_MOD("scifa3", 1106, R8A7791_CLK_MP),
209 DEF_MOD("scifa4", 1107, R8A7791_CLK_MP),
210 DEF_MOD("scifa5", 1108, R8A7791_CLK_MP),
211 };
212
213 /*
214 * CPG Clock Data
215 */
216
217 /*
218 * MD EXTAL PLL0 PLL1 PLL3
219 * 14 13 19 (MHz) *1 *1
220 *---------------------------------------------------
221 * 0 0 0 15 x172/2 x208/2 x106
222 * 0 0 1 15 x172/2 x208/2 x88
223 * 0 1 0 20 x130/2 x156/2 x80
224 * 0 1 1 20 x130/2 x156/2 x66
225 * 1 0 0 26 / 2 x200/2 x240/2 x122
226 * 1 0 1 26 / 2 x200/2 x240/2 x102
227 * 1 1 0 30 / 2 x172/2 x208/2 x106
228 * 1 1 1 30 / 2 x172/2 x208/2 x88
229 *
230 * *1 : Table 7.5a indicates VCO output (PLLx = VCO/2)
231 */
232 #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \
233 (((md) & BIT(13)) >> 12) | \
234 (((md) & BIT(19)) >> 19))
235 static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] = {
236 { 1, 208, 106 }, { 1, 208, 88 }, { 1, 156, 80 }, { 1, 156, 66 },
237 { 2, 240, 122 }, { 2, 240, 102 }, { 2, 208, 106 }, { 2, 208, 88 },
238 };
239
240 static const struct mstp_stop_table r8a7791_mstp_table[] = {
241 { 0x00640801, 0x400000, 0x00640801, 0x0 },
242 { 0x9B6C9B5A, 0x0, 0x9B6C9B5A, 0x0 },
243 { 0x100D21FC, 0x2000, 0x100D21FC, 0x0 },
244 { 0xF08CD810, 0x0, 0xF08CD810, 0x0 },
245 { 0x800001C4, 0x180, 0x800001C4, 0x0 },
246 { 0x44C00046, 0x0, 0x44C00046, 0x0 },
247 { 0x0, 0x0, 0x0, 0x0 }, /* SMSTP6 is not present on Gen2 */
248 { 0x25BFE618, 0x200000, 0x25BFE618, 0x0 },
249 { 0x40C0FE85, 0x0, 0x40C0FE85, 0x0 },
250 { 0xFF979FFF, 0x0, 0xFF979FFF, 0x0 },
251 { 0xFFFEFFE0, 0x0, 0xFFFEFFE0, 0x0 },
252 { 0x000001C0, 0x0, 0x000001C0, 0x0 },
253 };
254
r8a7791_get_pll_config(const u32 cpg_mode)255 static const void *r8a7791_get_pll_config(const u32 cpg_mode)
256 {
257 return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
258 }
259
260 static const struct cpg_mssr_info r8a7791_cpg_mssr_info = {
261 .core_clk = r8a7791_core_clks,
262 .core_clk_size = ARRAY_SIZE(r8a7791_core_clks),
263 .mod_clk = r8a7791_mod_clks,
264 .mod_clk_size = ARRAY_SIZE(r8a7791_mod_clks),
265 .mstp_table = r8a7791_mstp_table,
266 .mstp_table_size = ARRAY_SIZE(r8a7791_mstp_table),
267 .reset_node = "renesas,r8a7791-rst",
268 .reset_modemr_offset = CPG_RST_MODEMR,
269 .extal_usb_node = "usb_extal",
270 .mod_clk_base = MOD_CLK_BASE,
271 .clk_extal_id = CLK_EXTAL,
272 .clk_extal_usb_id = CLK_USB_EXTAL,
273 .pll0_div = 2,
274 .get_pll_config = r8a7791_get_pll_config,
275 };
276
277 static const struct udevice_id r8a7791_clk_ids[] = {
278 {
279 .compatible = "renesas,r8a7791-cpg-mssr",
280 .data = (ulong)&r8a7791_cpg_mssr_info
281 },
282 {
283 .compatible = "renesas,r8a7793-cpg-mssr",
284 .data = (ulong)&r8a7791_cpg_mssr_info
285 },
286 { }
287 };
288
289 U_BOOT_DRIVER(clk_r8a7791) = {
290 .name = "clk_r8a7791",
291 .id = UCLASS_CLK,
292 .of_match = r8a7791_clk_ids,
293 .priv_auto = sizeof(struct gen2_clk_priv),
294 .ops = &gen2_clk_ops,
295 .probe = gen2_clk_probe,
296 .remove = gen2_clk_remove,
297 };
298