1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2018 NXP
4  */
5 
6 #ifndef __ASM_ARCH_IMX8_REGS_H__
7 #define __ASM_ARCH_IMX8_REGS_H__
8 
9 #define ARCH_MXC
10 
11 #define LPUART_BASE		0x5A060000
12 
13 #define GPT1_BASE_ADDR		0x5D140000
14 #define SCU_LPUART_BASE		0x33220000
15 #define GPIO1_BASE_ADDR		0x5D080000
16 #define GPIO2_BASE_ADDR		0x5D090000
17 #define GPIO3_BASE_ADDR		0x5D0A0000
18 #define GPIO4_BASE_ADDR		0x5D0B0000
19 #define GPIO5_BASE_ADDR		0x5D0C0000
20 #define GPIO6_BASE_ADDR		0x5D0D0000
21 #define GPIO7_BASE_ADDR		0x5D0E0000
22 #define GPIO8_BASE_ADDR		0x5D0F0000
23 #define LPI2C1_BASE_ADDR	0x5A800000
24 #define LPI2C2_BASE_ADDR	0x5A810000
25 #define LPI2C3_BASE_ADDR	0x5A820000
26 #define LPI2C4_BASE_ADDR	0x5A830000
27 #define LPI2C5_BASE_ADDR	0x5A840000
28 
29 #ifdef CONFIG_IMX8QXP
30 #define LVDS0_PHYCTRL_BASE	0x56221000
31 #define LVDS1_PHYCTRL_BASE	0x56241000
32 #define MIPI0_SS_BASE		0x56220000
33 #define MIPI1_SS_BASE		0x56240000
34 #endif
35 
36 #define APBH_DMA_ARB_BASE_ADDR	0x5B810000
37 #define APBH_DMA_ARB_END_ADDR	0x5B81FFFF
38 #define MXS_APBH_BASE		APBH_DMA_ARB_BASE_ADDR
39 
40 #define MXS_GPMI_BASE		(APBH_DMA_ARB_BASE_ADDR + 0x02000)
41 #define MXS_BCH_BASE		(APBH_DMA_ARB_BASE_ADDR + 0x04000)
42 
43 #define PASS_OVER_INFO_ADDR	0x0010fe00
44 
45 #define USB_BASE_ADDR		0x5b0d0000
46 #define USB_PHY0_BASE_ADDR	0x5b100000
47 
48 #endif /* __ASM_ARCH_IMX8_REGS_H__ */
49