1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * board.c
4 *
5 * Board functions for Birdland Audio BAV335x Network Processor
6 *
7 * Copyright (c) 2012-2014 Birdland Audio - http://birdland.com/oem
8 */
9
10 #include <common.h>
11 #include <env.h>
12 #include <errno.h>
13 #include <init.h>
14 #include <net.h>
15 #include <serial.h>
16 #include <spl.h>
17 #include <asm/arch/cpu.h>
18 #include <asm/arch/hardware.h>
19 #include <asm/arch/omap.h>
20 #include <asm/arch/ddr_defs.h>
21 #include <asm/arch/clock.h>
22 #include <asm/arch/gpio.h>
23 #include <asm/arch/mmc_host_def.h>
24 #include <asm/arch/sys_proto.h>
25 #include <asm/arch/mem.h>
26 #include <asm/io.h>
27 #include <asm/emif.h>
28 #include <asm/gpio.h>
29 #include <i2c.h>
30 #include <miiphy.h>
31 #include <cpsw.h>
32 #include <power/tps65217.h>
33 #include <power/tps65910.h>
34 #include <env_internal.h>
35 #include <watchdog.h>
36 #include "board.h"
37
38 DECLARE_GLOBAL_DATA_PTR;
39
40 /* GPIO that controls power to DDR on EVM-SK */
41 #define GPIO_DDR_VTT_EN 7
42
43 static __maybe_unused struct ctrl_dev *cdev =
44 (struct ctrl_dev *)CTRL_DEVICE_BASE;
45
46
47
48 /*
49 * Read header information from EEPROM into global structure.
50 */
read_eeprom(struct board_eeconfig * header)51 static int read_eeprom(struct board_eeconfig *header)
52 {
53 /* Check if baseboard eeprom is available */
54 if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR))
55 return -ENODEV;
56
57 /* read the eeprom using i2c */
58 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,
59 sizeof(struct board_eeconfig)))
60 return -EIO;
61
62 if (header->magic != BOARD_MAGIC) {
63 /* read the i2c eeprom again using only a 1 byte address */
64 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
65 sizeof(struct board_eeconfig)))
66 return -EIO;
67
68 if (header->magic != BOARD_MAGIC)
69 return -EINVAL;
70 }
71 return 0;
72 }
73
74
75
76
get_board_type(bool debug)77 enum board_type get_board_type(bool debug)
78 {
79 int ecode;
80 struct board_eeconfig header;
81
82 ecode = read_eeprom(&header);
83 if (ecode == 0) {
84 if (header.version[1] == 'A') {
85 if (debug)
86 puts("=== Detected Board model BAV335x Rev.A");
87 return BAV335A;
88 } else if (header.version[1] == 'B') {
89 if (debug)
90 puts("=== Detected Board model BAV335x Rev.B");
91 return BAV335B;
92 } else if (debug) {
93 puts("### Un-known board model in serial-EE\n");
94 }
95 } else if (debug) {
96 switch (ecode) {
97 case -ENODEV:
98 puts("### Board doesn't have a serial-EE\n");
99 break;
100 case -EINVAL:
101 puts("### Board serial-EE signature is incorrect.\n");
102 break;
103 default:
104 puts("### IO Error reading serial-EE.\n");
105 break;
106 }
107 }
108
109 #if (CONFIG_BAV_VERSION == 1)
110 if (debug)
111 puts("### Selecting BAV335A as per config\n");
112 return BAV335A;
113 #elif (CONFIG_BAV_VERSION == 2)
114 if (debug)
115 puts("### Selecting BAV335B as per config\n");
116 return BAV335B;
117 #endif
118 #if (NOT_DEFINED == 2)
119 #error "SHOULD NEVER DISPLAY THIS"
120 #endif
121
122 if (debug)
123 puts("### Defaulting to model BAV335x Rev.B\n");
124 return BAV335B;
125 }
126
127
128
129 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
130 static const struct ddr_data ddr3_bav335x_data = {
131 .datardsratio0 = MT41K256M16HA125E_RD_DQS,
132 .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
133 .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
134 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
135 };
136
137 static const struct cmd_control ddr3_bav335x_cmd_ctrl_data = {
138 .cmd0csratio = MT41K256M16HA125E_RATIO,
139 .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
140 .cmd1csratio = MT41K256M16HA125E_RATIO,
141 .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
142 .cmd2csratio = MT41K256M16HA125E_RATIO,
143 .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
144 };
145
146
147 static struct emif_regs ddr3_bav335x_emif_reg_data = {
148 .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
149 .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
150 .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
151 .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
152 .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
153 .zq_config = MT41K256M16HA125E_ZQ_CFG,
154 .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
155 };
156
157
158 #ifdef CONFIG_SPL_OS_BOOT
spl_start_uboot(void)159 int spl_start_uboot(void)
160 {
161 /* break into full u-boot on 'c' */
162 if (serial_tstc() && serial_getc() == 'c')
163 return 1;
164
165 #ifdef CONFIG_SPL_ENV_SUPPORT
166 env_init();
167 env_load();
168 if (env_get_yesno("boot_os") != 1)
169 return 1;
170 #endif
171
172 return 0;
173 }
174 #endif
175
176 #define OSC (V_OSCK/1000000)
177 const struct dpll_params dpll_ddr = {
178 266, OSC-1, 1, -1, -1, -1, -1};
179 const struct dpll_params dpll_ddr_evm_sk = {
180 303, OSC-1, 1, -1, -1, -1, -1};
181 const struct dpll_params dpll_ddr_bone_black = {
182 400, OSC-1, 1, -1, -1, -1, -1};
183
am33xx_spl_board_init(void)184 void am33xx_spl_board_init(void)
185 {
186 /* debug print detect status */
187 (void)get_board_type(true);
188
189 /* Get the frequency */
190 /* dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); */
191 dpll_mpu_opp100.m = MPUPLL_M_1000;
192
193 if (i2c_probe(TPS65217_CHIP_PM))
194 return;
195
196 /* Set the USB Current Limit */
197 if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, TPS65217_POWER_PATH,
198 TPS65217_USB_INPUT_CUR_LIMIT_1800MA,
199 TPS65217_USB_INPUT_CUR_LIMIT_MASK))
200 puts("! tps65217_reg_write: could not set USB limit\n");
201
202 /* Set the Core Voltage (DCDC3) to 1.125V */
203 if (tps65217_voltage_update(TPS65217_DEFDCDC3,
204 TPS65217_DCDC_VOLT_SEL_1125MV)) {
205 puts("! tps65217_reg_write: could not set Core Voltage\n");
206 return;
207 }
208
209 /* Set CORE Frequencies to OPP100 */
210 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
211
212 /* Set the MPU Voltage (DCDC2) */
213 if (tps65217_voltage_update(TPS65217_DEFDCDC2,
214 TPS65217_DCDC_VOLT_SEL_1325MV)) {
215 puts("! tps65217_reg_write: could not set MPU Voltage\n");
216 return;
217 }
218
219 /*
220 * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
221 * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black.
222 */
223 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, TPS65217_DEFLS1,
224 TPS65217_LDO_VOLTAGE_OUT_1_8, TPS65217_LDO_MASK))
225 puts("! tps65217_reg_write: could not set LDO3\n");
226
227 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, TPS65217_DEFLS2,
228 TPS65217_LDO_VOLTAGE_OUT_3_3, TPS65217_LDO_MASK))
229 puts("! tps65217_reg_write: could not set LDO4\n");
230
231 /* Set MPU Frequency to what we detected now that voltages are set */
232 do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
233 }
234
get_dpll_ddr_params(void)235 const struct dpll_params *get_dpll_ddr_params(void)
236 {
237 enable_i2c0_pin_mux();
238 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
239
240 return &dpll_ddr_bone_black;
241 }
242
set_uart_mux_conf(void)243 void set_uart_mux_conf(void)
244 {
245 #if CONFIG_CONS_INDEX == 1
246 enable_uart0_pin_mux();
247 #elif CONFIG_CONS_INDEX == 2
248 enable_uart1_pin_mux();
249 #elif CONFIG_CONS_INDEX == 3
250 enable_uart2_pin_mux();
251 #elif CONFIG_CONS_INDEX == 4
252 enable_uart3_pin_mux();
253 #elif CONFIG_CONS_INDEX == 5
254 enable_uart4_pin_mux();
255 #elif CONFIG_CONS_INDEX == 6
256 enable_uart5_pin_mux();
257 #endif
258 }
259
set_mux_conf_regs(void)260 void set_mux_conf_regs(void)
261 {
262 enum board_type board;
263
264 board = get_board_type(false);
265 enable_board_pin_mux(board);
266 }
267
268 const struct ctrl_ioregs ioregs_bonelt = {
269 .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
270 .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
271 .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
272 .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
273 .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
274 };
275
276
sdram_init(void)277 void sdram_init(void)
278 {
279 config_ddr(400, &ioregs_bonelt,
280 &ddr3_bav335x_data,
281 &ddr3_bav335x_cmd_ctrl_data,
282 &ddr3_bav335x_emif_reg_data, 0);
283 }
284 #endif
285
286 /*
287 * Basic board specific setup. Pinmux has been handled already.
288 */
board_init(void)289 int board_init(void)
290 {
291 #if defined(CONFIG_HW_WATCHDOG)
292 hw_watchdog_init();
293 #endif
294
295 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
296 #if defined(CONFIG_NOR) || defined(CONFIG_MTD_RAW_NAND)
297 gpmc_init();
298 #endif
299 return 0;
300 }
301
302 #ifdef CONFIG_BOARD_LATE_INIT
board_late_init(void)303 int board_late_init(void)
304 {
305 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
306 env_set("board_name", "BAV335xB");
307 env_set("board_rev", "B"); /* Fix me, but why bother.. */
308 #endif
309 return 0;
310 }
311 #endif
312
313
314 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
315 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
cpsw_control(int enabled)316 static void cpsw_control(int enabled)
317 {
318 /* VTP can be added here */
319 return;
320 }
321
322 static struct cpsw_slave_data cpsw_slaves[] = {
323 {
324 .slave_reg_ofs = 0x208,
325 .sliver_reg_ofs = 0xd80,
326 .phy_addr = 0,
327 },
328 {
329 .slave_reg_ofs = 0x308,
330 .sliver_reg_ofs = 0xdc0,
331 .phy_addr = 1,
332 },
333 };
334
335 static struct cpsw_platform_data cpsw_data = {
336 .mdio_base = CPSW_MDIO_BASE,
337 .cpsw_base = CPSW_BASE,
338 .mdio_div = 0xff,
339 .channels = 8,
340 .cpdma_reg_ofs = 0x800,
341 .slaves = 1,
342 .slave_data = cpsw_slaves,
343 .ale_reg_ofs = 0xd00,
344 .ale_entries = 1024,
345 .host_port_reg_ofs = 0x108,
346 .hw_stats_reg_ofs = 0x900,
347 .bd_ram_ofs = 0x2000,
348 .mac_control = (1 << 5),
349 .control = cpsw_control,
350 .host_port_num = 0,
351 .version = CPSW_CTRL_VERSION_2,
352 };
353 #endif
354
355
356 /*
357 * This function will:
358 * Perform fixups to the PHY present on certain boards. We only need this
359 * function in:
360 * - SPL with either CPSW or USB ethernet support
361 * - Full U-Boot, with either CPSW or USB ethernet
362 * Build in only these cases to avoid warnings about unused variables
363 * when we build an SPL that has neither option but full U-Boot will.
364 */
365 #if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USB_ETHER)) &&\
366 defined(CONFIG_SPL_BUILD)) || \
367 ((defined(CONFIG_DRIVER_TI_CPSW) || \
368 defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)) && \
369 !defined(CONFIG_SPL_BUILD))
board_eth_init(bd_t * bis)370 int board_eth_init(bd_t *bis)
371 {
372 int ecode, rv, n;
373 uint8_t mac_addr[6];
374 struct board_eeconfig header;
375 __maybe_unused enum board_type board;
376
377 /* Default manufacturing address; used when no EE or invalid */
378 n = 0;
379 mac_addr[0] = 0;
380 mac_addr[1] = 0x20;
381 mac_addr[2] = 0x18;
382 mac_addr[3] = 0x1C;
383 mac_addr[4] = 0x00;
384 mac_addr[5] = 0x01;
385
386 ecode = read_eeprom(&header);
387 /* if we have a valid EE, get mac address from there */
388 if ((ecode == 0) &&
389 is_valid_ethaddr((const u8 *)&header.mac_addr[0][0])) {
390 memcpy(mac_addr, (const void *)&header.mac_addr[0][0], 6);
391 }
392
393
394 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
395 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
396
397 if (!env_get("ethaddr")) {
398 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
399
400 if (is_valid_ethaddr(mac_addr))
401 eth_env_set_enetaddr("ethaddr", mac_addr);
402 }
403
404 #ifdef CONFIG_DRIVER_TI_CPSW
405
406 board = get_board_type(false);
407
408 /* Rev.A uses 10/100 PHY in mii mode */
409 if (board == BAV335A) {
410 writel(MII_MODE_ENABLE, &cdev->miisel);
411 cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_MII;
412 cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_MII;
413 }
414 /* Rev.B (default) uses GB PHY in rmii mode */
415 else {
416 writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
417 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if
418 = PHY_INTERFACE_MODE_RGMII;
419 }
420
421 rv = cpsw_register(&cpsw_data);
422 if (rv < 0)
423 printf("Error %d registering CPSW switch\n", rv);
424 else
425 n += rv;
426 #endif
427
428 #endif
429
430 return n;
431 }
432 #endif
433