1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2 /*
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
4 */
5
6 #include <common.h>
7 #include <adc.h>
8 #include <log.h>
9 #include <net.h>
10 #include <asm/arch/stm32.h>
11 #include <asm/arch/sys_proto.h>
12 #include <asm/gpio.h>
13 #include <asm/io.h>
14 #include <bootm.h>
15 #include <clk.h>
16 #include <config.h>
17 #include <dm.h>
18 #include <dm/device.h>
19 #include <dm/uclass.h>
20 #include <env.h>
21 #include <env_internal.h>
22 #include <g_dnl.h>
23 #include <generic-phy.h>
24 #include <hang.h>
25 #include <i2c.h>
26 #include <i2c_eeprom.h>
27 #include <init.h>
28 #include <led.h>
29 #include <memalign.h>
30 #include <misc.h>
31 #include <mtd.h>
32 #include <mtd_node.h>
33 #include <netdev.h>
34 #include <phy.h>
35 #include <linux/bitops.h>
36 #include <linux/delay.h>
37 #include <power/regulator.h>
38 #include <remoteproc.h>
39 #include <reset.h>
40 #include <syscon.h>
41 #include <usb.h>
42 #include <usb/dwc2_udc.h>
43 #include <watchdog.h>
44
45 /* SYSCFG registers */
46 #define SYSCFG_BOOTR 0x00
47 #define SYSCFG_PMCSETR 0x04
48 #define SYSCFG_IOCTRLSETR 0x18
49 #define SYSCFG_ICNR 0x1C
50 #define SYSCFG_CMPCR 0x20
51 #define SYSCFG_CMPENSETR 0x24
52 #define SYSCFG_PMCCLRR 0x44
53
54 #define SYSCFG_BOOTR_BOOT_MASK GENMASK(2, 0)
55 #define SYSCFG_BOOTR_BOOTPD_SHIFT 4
56
57 #define SYSCFG_IOCTRLSETR_HSLVEN_TRACE BIT(0)
58 #define SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI BIT(1)
59 #define SYSCFG_IOCTRLSETR_HSLVEN_ETH BIT(2)
60 #define SYSCFG_IOCTRLSETR_HSLVEN_SDMMC BIT(3)
61 #define SYSCFG_IOCTRLSETR_HSLVEN_SPI BIT(4)
62
63 #define SYSCFG_CMPCR_SW_CTRL BIT(1)
64 #define SYSCFG_CMPCR_READY BIT(8)
65
66 #define SYSCFG_CMPENSETR_MPU_EN BIT(0)
67
68 #define SYSCFG_PMCSETR_ETH_CLK_SEL BIT(16)
69 #define SYSCFG_PMCSETR_ETH_REF_CLK_SEL BIT(17)
70
71 #define SYSCFG_PMCSETR_ETH_SELMII BIT(20)
72
73 #define SYSCFG_PMCSETR_ETH_SEL_MASK GENMASK(23, 21)
74 #define SYSCFG_PMCSETR_ETH_SEL_GMII_MII 0
75 #define SYSCFG_PMCSETR_ETH_SEL_RGMII BIT(21)
76 #define SYSCFG_PMCSETR_ETH_SEL_RMII BIT(23)
77
78 /*
79 * Get a global data pointer
80 */
81 DECLARE_GLOBAL_DATA_PTR;
82
setup_mac_address(void)83 int setup_mac_address(void)
84 {
85 unsigned char enetaddr[6];
86 struct udevice *dev;
87 int off, ret;
88
89 ret = eth_env_get_enetaddr("ethaddr", enetaddr);
90 if (ret) /* ethaddr is already set */
91 return 0;
92
93 off = fdt_path_offset(gd->fdt_blob, "eeprom0");
94 if (off < 0) {
95 printf("%s: No eeprom0 path offset\n", __func__);
96 return off;
97 }
98
99 ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev);
100 if (ret) {
101 printf("Cannot find EEPROM!\n");
102 return ret;
103 }
104
105 ret = i2c_eeprom_read(dev, 0xfa, enetaddr, 0x6);
106 if (ret) {
107 printf("Error reading configuration EEPROM!\n");
108 return ret;
109 }
110
111 if (is_valid_ethaddr(enetaddr))
112 eth_env_set_enetaddr("ethaddr", enetaddr);
113
114 return 0;
115 }
116
checkboard(void)117 int checkboard(void)
118 {
119 char *mode;
120 const char *fdt_compat;
121 int fdt_compat_len;
122
123 if (IS_ENABLED(CONFIG_TFABOOT))
124 mode = "trusted";
125 else
126 mode = "basic";
127
128 printf("Board: stm32mp1 in %s mode", mode);
129 fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
130 &fdt_compat_len);
131 if (fdt_compat && fdt_compat_len)
132 printf(" (%s)", fdt_compat);
133 puts("\n");
134
135 return 0;
136 }
137
138 #ifdef CONFIG_BOARD_EARLY_INIT_F
139 static u8 brdcode __section("data");
140 static u8 ddr3code __section("data");
141 static u8 somcode __section("data");
142
board_get_coding_straps(void)143 static void board_get_coding_straps(void)
144 {
145 struct gpio_desc gpio[4];
146 ofnode node;
147 int i, ret;
148
149 node = ofnode_path("/config");
150 if (!ofnode_valid(node)) {
151 printf("%s: no /config node?\n", __func__);
152 return;
153 }
154
155 brdcode = 0;
156 ddr3code = 0;
157 somcode = 0;
158
159 ret = gpio_request_list_by_name_nodev(node, "dh,som-coding-gpios",
160 gpio, ARRAY_SIZE(gpio),
161 GPIOD_IS_IN);
162 for (i = 0; i < ret; i++)
163 somcode |= !!dm_gpio_get_value(&(gpio[i])) << i;
164
165 ret = gpio_request_list_by_name_nodev(node, "dh,ddr3-coding-gpios",
166 gpio, ARRAY_SIZE(gpio),
167 GPIOD_IS_IN);
168 for (i = 0; i < ret; i++)
169 ddr3code |= !!dm_gpio_get_value(&(gpio[i])) << i;
170
171 ret = gpio_request_list_by_name_nodev(node, "dh,board-coding-gpios",
172 gpio, ARRAY_SIZE(gpio),
173 GPIOD_IS_IN);
174 for (i = 0; i < ret; i++)
175 brdcode |= !!dm_gpio_get_value(&(gpio[i])) << i;
176
177 printf("Code: SoM:rev=%d,ddr3=%d Board:rev=%d\n",
178 somcode, ddr3code, brdcode);
179 }
180
board_stm32mp1_ddr_config_name_match(struct udevice * dev,const char * name)181 int board_stm32mp1_ddr_config_name_match(struct udevice *dev,
182 const char *name)
183 {
184 if (ddr3code == 1 &&
185 !strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-2x1gb-533mhz"))
186 return 0;
187
188 if (ddr3code == 2 &&
189 !strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-2x2gb-533mhz"))
190 return 0;
191
192 if (ddr3code == 3 &&
193 !strcmp(name, "st,ddr3l-dhsom-1066-888-bin-g-2x4gb-533mhz"))
194 return 0;
195
196 return -EINVAL;
197 }
198
board_early_init_f(void)199 int board_early_init_f(void)
200 {
201 board_get_coding_straps();
202
203 return 0;
204 }
205
206 #ifdef CONFIG_SPL_LOAD_FIT
board_fit_config_name_match(const char * name)207 int board_fit_config_name_match(const char *name)
208 {
209 char test[20];
210
211 snprintf(test, sizeof(test), "somrev%d_boardrev%d", somcode, brdcode);
212
213 if (!strcmp(name, test))
214 return 0;
215
216 return -EINVAL;
217 }
218 #endif
219 #endif
220
board_key_check(void)221 static void board_key_check(void)
222 {
223 #if defined(CONFIG_FASTBOOT) || defined(CONFIG_CMD_STM32PROG)
224 ofnode node;
225 struct gpio_desc gpio;
226 enum forced_boot_mode boot_mode = BOOT_NORMAL;
227
228 node = ofnode_path("/config");
229 if (!ofnode_valid(node)) {
230 debug("%s: no /config node?\n", __func__);
231 return;
232 }
233 #ifdef CONFIG_FASTBOOT
234 if (gpio_request_by_name_nodev(node, "st,fastboot-gpios", 0,
235 &gpio, GPIOD_IS_IN)) {
236 debug("%s: could not find a /config/st,fastboot-gpios\n",
237 __func__);
238 } else {
239 if (dm_gpio_get_value(&gpio)) {
240 puts("Fastboot key pressed, ");
241 boot_mode = BOOT_FASTBOOT;
242 }
243
244 dm_gpio_free(NULL, &gpio);
245 }
246 #endif
247 #ifdef CONFIG_CMD_STM32PROG
248 if (gpio_request_by_name_nodev(node, "st,stm32prog-gpios", 0,
249 &gpio, GPIOD_IS_IN)) {
250 debug("%s: could not find a /config/st,stm32prog-gpios\n",
251 __func__);
252 } else {
253 if (dm_gpio_get_value(&gpio)) {
254 puts("STM32Programmer key pressed, ");
255 boot_mode = BOOT_STM32PROG;
256 }
257 dm_gpio_free(NULL, &gpio);
258 }
259 #endif
260
261 if (boot_mode != BOOT_NORMAL) {
262 puts("entering download mode...\n");
263 clrsetbits_le32(TAMP_BOOT_CONTEXT,
264 TAMP_BOOT_FORCED_MASK,
265 boot_mode);
266 }
267 #endif
268 }
269
270 #if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
271
272 #include <usb/dwc2_udc.h>
g_dnl_board_usb_cable_connected(void)273 int g_dnl_board_usb_cable_connected(void)
274 {
275 struct udevice *dwc2_udc_otg;
276 int ret;
277
278 ret = uclass_get_device_by_driver(UCLASS_USB_GADGET_GENERIC,
279 DM_GET_DRIVER(dwc2_udc_otg),
280 &dwc2_udc_otg);
281 if (!ret)
282 debug("dwc2_udc_otg init failed\n");
283
284 return dwc2_udc_B_session_valid(dwc2_udc_otg);
285 }
286
287 #define STM32MP1_G_DNL_DFU_PRODUCT_NUM 0xdf11
288 #define STM32MP1_G_DNL_FASTBOOT_PRODUCT_NUM 0x0afb
289
g_dnl_bind_fixup(struct usb_device_descriptor * dev,const char * name)290 int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
291 {
292 if (!strcmp(name, "usb_dnl_dfu"))
293 put_unaligned(STM32MP1_G_DNL_DFU_PRODUCT_NUM, &dev->idProduct);
294 else if (!strcmp(name, "usb_dnl_fastboot"))
295 put_unaligned(STM32MP1_G_DNL_FASTBOOT_PRODUCT_NUM,
296 &dev->idProduct);
297 else
298 put_unaligned(CONFIG_USB_GADGET_PRODUCT_NUM, &dev->idProduct);
299
300 return 0;
301 }
302
303 #endif /* CONFIG_USB_GADGET */
304
305 #ifdef CONFIG_LED
get_led(struct udevice ** dev,char * led_string)306 static int get_led(struct udevice **dev, char *led_string)
307 {
308 char *led_name;
309 int ret;
310
311 led_name = fdtdec_get_config_string(gd->fdt_blob, led_string);
312 if (!led_name) {
313 pr_debug("%s: could not find %s config string\n",
314 __func__, led_string);
315 return -ENOENT;
316 }
317 ret = led_get_by_label(led_name, dev);
318 if (ret) {
319 debug("%s: get=%d\n", __func__, ret);
320 return ret;
321 }
322
323 return 0;
324 }
325
setup_led(enum led_state_t cmd)326 static int setup_led(enum led_state_t cmd)
327 {
328 struct udevice *dev;
329 int ret;
330
331 ret = get_led(&dev, "u-boot,boot-led");
332 if (ret)
333 return ret;
334
335 ret = led_set_state(dev, cmd);
336 return ret;
337 }
338 #endif
339
led_error_blink(u32 nb_blink)340 static void __maybe_unused led_error_blink(u32 nb_blink)
341 {
342 #ifdef CONFIG_LED
343 int ret;
344 struct udevice *led;
345 u32 i;
346 #endif
347
348 if (!nb_blink)
349 return;
350
351 #ifdef CONFIG_LED
352 ret = get_led(&led, "u-boot,error-led");
353 if (!ret) {
354 /* make u-boot,error-led blinking */
355 /* if U32_MAX and 125ms interval, for 17.02 years */
356 for (i = 0; i < 2 * nb_blink; i++) {
357 led_set_state(led, LEDST_TOGGLE);
358 mdelay(125);
359 WATCHDOG_RESET();
360 }
361 }
362 #endif
363
364 /* infinite: the boot process must be stopped */
365 if (nb_blink == U32_MAX)
366 hang();
367 }
368
sysconf_init(void)369 static void sysconf_init(void)
370 {
371 #ifndef CONFIG_TFABOOT
372 u8 *syscfg;
373 #ifdef CONFIG_DM_REGULATOR
374 struct udevice *pwr_dev;
375 struct udevice *pwr_reg;
376 struct udevice *dev;
377 int ret;
378 u32 otp = 0;
379 #endif
380 u32 bootr;
381
382 syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
383
384 /* interconnect update : select master using the port 1 */
385 /* LTDC = AXI_M9 */
386 /* GPU = AXI_M8 */
387 /* today information is hardcoded in U-Boot */
388 writel(BIT(9), syscfg + SYSCFG_ICNR);
389
390 /* disable Pull-Down for boot pin connected to VDD */
391 bootr = readl(syscfg + SYSCFG_BOOTR);
392 bootr &= ~(SYSCFG_BOOTR_BOOT_MASK << SYSCFG_BOOTR_BOOTPD_SHIFT);
393 bootr |= (bootr & SYSCFG_BOOTR_BOOT_MASK) << SYSCFG_BOOTR_BOOTPD_SHIFT;
394 writel(bootr, syscfg + SYSCFG_BOOTR);
395
396 #ifdef CONFIG_DM_REGULATOR
397 /* High Speed Low Voltage Pad mode Enable for SPI, SDMMC, ETH, QSPI
398 * and TRACE. Needed above ~50MHz and conditioned by AFMUX selection.
399 * The customer will have to disable this for low frequencies
400 * or if AFMUX is selected but the function not used, typically for
401 * TRACE. Otherwise, impact on power consumption.
402 *
403 * WARNING:
404 * enabling High Speed mode while VDD>2.7V
405 * with the OTP product_below_2v5 (OTP 18, BIT 13)
406 * erroneously set to 1 can damage the IC!
407 * => U-Boot set the register only if VDD < 2.7V (in DT)
408 * but this value need to be consistent with board design
409 */
410 ret = uclass_get_device_by_driver(UCLASS_PMIC,
411 DM_GET_DRIVER(stm32mp_pwr_pmic),
412 &pwr_dev);
413 if (!ret) {
414 ret = uclass_get_device_by_driver(UCLASS_MISC,
415 DM_GET_DRIVER(stm32mp_bsec),
416 &dev);
417 if (ret) {
418 pr_err("Can't find stm32mp_bsec driver\n");
419 return;
420 }
421
422 ret = misc_read(dev, STM32_BSEC_SHADOW(18), &otp, 4);
423 if (ret > 0)
424 otp = otp & BIT(13);
425
426 /* get VDD = vdd-supply */
427 ret = device_get_supply_regulator(pwr_dev, "vdd-supply",
428 &pwr_reg);
429
430 /* check if VDD is Low Voltage */
431 if (!ret) {
432 if (regulator_get_value(pwr_reg) < 2700000) {
433 writel(SYSCFG_IOCTRLSETR_HSLVEN_TRACE |
434 SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI |
435 SYSCFG_IOCTRLSETR_HSLVEN_ETH |
436 SYSCFG_IOCTRLSETR_HSLVEN_SDMMC |
437 SYSCFG_IOCTRLSETR_HSLVEN_SPI,
438 syscfg + SYSCFG_IOCTRLSETR);
439
440 if (!otp)
441 pr_err("product_below_2v5=0: HSLVEN protected by HW\n");
442 } else {
443 if (otp)
444 pr_err("product_below_2v5=1: HSLVEN update is destructive, no update as VDD>2.7V\n");
445 }
446 } else {
447 debug("VDD unknown");
448 }
449 }
450 #endif
451
452 /* activate automatic I/O compensation
453 * warning: need to ensure CSI enabled and ready in clock driver
454 */
455 writel(SYSCFG_CMPENSETR_MPU_EN, syscfg + SYSCFG_CMPENSETR);
456
457 while (!(readl(syscfg + SYSCFG_CMPCR) & SYSCFG_CMPCR_READY))
458 ;
459 clrbits_le32(syscfg + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
460 #endif
461 }
462
board_init_fmc2(void)463 static void board_init_fmc2(void)
464 {
465 #define STM32_FMC2_BCR1 0x0
466 #define STM32_FMC2_BTR1 0x4
467 #define STM32_FMC2_BWTR1 0x104
468 #define STM32_FMC2_BCR(x) ((x) * 0x8 + STM32_FMC2_BCR1)
469 #define STM32_FMC2_BCRx_FMCEN BIT(31)
470 #define STM32_FMC2_BCRx_WREN BIT(12)
471 #define STM32_FMC2_BCRx_RSVD BIT(7)
472 #define STM32_FMC2_BCRx_FACCEN BIT(6)
473 #define STM32_FMC2_BCRx_MWID(n) ((n) << 4)
474 #define STM32_FMC2_BCRx_MTYP(n) ((n) << 2)
475 #define STM32_FMC2_BCRx_MUXEN BIT(1)
476 #define STM32_FMC2_BCRx_MBKEN BIT(0)
477 #define STM32_FMC2_BTR(x) ((x) * 0x8 + STM32_FMC2_BTR1)
478 #define STM32_FMC2_BTRx_DATAHLD(n) ((n) << 30)
479 #define STM32_FMC2_BTRx_BUSTURN(n) ((n) << 16)
480 #define STM32_FMC2_BTRx_DATAST(n) ((n) << 8)
481 #define STM32_FMC2_BTRx_ADDHLD(n) ((n) << 4)
482 #define STM32_FMC2_BTRx_ADDSET(n) ((n) << 0)
483
484 #define RCC_MP_AHB6RSTCLRR 0x218
485 #define RCC_MP_AHB6RSTCLRR_FMCRST BIT(12)
486 #define RCC_MP_AHB6ENSETR 0x19c
487 #define RCC_MP_AHB6ENSETR_FMCEN BIT(12)
488
489 const u32 bcr = STM32_FMC2_BCRx_WREN |STM32_FMC2_BCRx_RSVD |
490 STM32_FMC2_BCRx_FACCEN | STM32_FMC2_BCRx_MWID(1) |
491 STM32_FMC2_BCRx_MTYP(2) | STM32_FMC2_BCRx_MUXEN |
492 STM32_FMC2_BCRx_MBKEN;
493 const u32 btr = STM32_FMC2_BTRx_DATAHLD(3) |
494 STM32_FMC2_BTRx_BUSTURN(2) |
495 STM32_FMC2_BTRx_DATAST(0x22) |
496 STM32_FMC2_BTRx_ADDHLD(2) |
497 STM32_FMC2_BTRx_ADDSET(2);
498
499 /* Set up FMC2 bus for KS8851-16MLL and X11 SRAM */
500 writel(RCC_MP_AHB6RSTCLRR_FMCRST, STM32_RCC_BASE + RCC_MP_AHB6RSTCLRR);
501 writel(RCC_MP_AHB6ENSETR_FMCEN, STM32_RCC_BASE + RCC_MP_AHB6ENSETR);
502
503 /* KS8851-16MLL -- Muxed mode */
504 writel(bcr, STM32_FMC2_BASE + STM32_FMC2_BCR(1));
505 writel(btr, STM32_FMC2_BASE + STM32_FMC2_BTR(1));
506 /* AS7C34098 SRAM on X11 -- Muxed mode */
507 writel(bcr, STM32_FMC2_BASE + STM32_FMC2_BCR(3));
508 writel(btr, STM32_FMC2_BASE + STM32_FMC2_BTR(3));
509
510 setbits_le32(STM32_FMC2_BASE + STM32_FMC2_BCR1, STM32_FMC2_BCRx_FMCEN);
511 }
512
513 /* board dependent setup after realloc */
board_init(void)514 int board_init(void)
515 {
516 struct udevice *dev;
517
518 /* address of boot parameters */
519 gd->bd->bi_boot_params = STM32_DDR_BASE + 0x100;
520
521 /* probe all PINCTRL for hog */
522 for (uclass_first_device(UCLASS_PINCTRL, &dev);
523 dev;
524 uclass_next_device(&dev)) {
525 pr_debug("probe pincontrol = %s\n", dev->name);
526 }
527
528 board_key_check();
529
530 #ifdef CONFIG_DM_REGULATOR
531 regulators_enable_boot_on(_DEBUG);
532 #endif
533
534 sysconf_init();
535
536 board_init_fmc2();
537
538 if (CONFIG_IS_ENABLED(LED))
539 led_default_state();
540
541 return 0;
542 }
543
board_late_init(void)544 int board_late_init(void)
545 {
546 char *boot_device;
547 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
548 const void *fdt_compat;
549 int fdt_compat_len;
550
551 fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
552 &fdt_compat_len);
553 if (fdt_compat && fdt_compat_len) {
554 if (strncmp(fdt_compat, "st,", 3) != 0)
555 env_set("board_name", fdt_compat);
556 else
557 env_set("board_name", fdt_compat + 3);
558 }
559 #endif
560
561 /* Check the boot-source to disable bootdelay */
562 boot_device = env_get("boot_device");
563 if (!strcmp(boot_device, "serial") || !strcmp(boot_device, "usb"))
564 env_set("bootdelay", "0");
565
566 #ifdef CONFIG_BOARD_EARLY_INIT_F
567 env_set_ulong("dh_som_rev", somcode);
568 env_set_ulong("dh_board_rev", brdcode);
569 env_set_ulong("dh_ddr3_code", ddr3code);
570 #endif
571
572 return 0;
573 }
574
board_quiesce_devices(void)575 void board_quiesce_devices(void)
576 {
577 #ifdef CONFIG_LED
578 setup_led(LEDST_OFF);
579 #endif
580 }
581
582 /* eth init function : weak called in eqos driver */
board_interface_eth_init(struct udevice * dev,phy_interface_t interface_type)583 int board_interface_eth_init(struct udevice *dev,
584 phy_interface_t interface_type)
585 {
586 u8 *syscfg;
587 u32 value;
588 bool eth_clk_sel_reg = false;
589 bool eth_ref_clk_sel_reg = false;
590
591 /* Gigabit Ethernet 125MHz clock selection. */
592 eth_clk_sel_reg = dev_read_bool(dev, "st,eth_clk_sel");
593
594 /* Ethernet 50Mhz RMII clock selection */
595 eth_ref_clk_sel_reg =
596 dev_read_bool(dev, "st,eth_ref_clk_sel");
597
598 syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
599
600 if (!syscfg)
601 return -ENODEV;
602
603 switch (interface_type) {
604 case PHY_INTERFACE_MODE_MII:
605 value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII |
606 SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
607 debug("%s: PHY_INTERFACE_MODE_MII\n", __func__);
608 break;
609 case PHY_INTERFACE_MODE_GMII:
610 if (eth_clk_sel_reg)
611 value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII |
612 SYSCFG_PMCSETR_ETH_CLK_SEL;
613 else
614 value = SYSCFG_PMCSETR_ETH_SEL_GMII_MII;
615 debug("%s: PHY_INTERFACE_MODE_GMII\n", __func__);
616 break;
617 case PHY_INTERFACE_MODE_RMII:
618 if (eth_ref_clk_sel_reg)
619 value = SYSCFG_PMCSETR_ETH_SEL_RMII |
620 SYSCFG_PMCSETR_ETH_REF_CLK_SEL;
621 else
622 value = SYSCFG_PMCSETR_ETH_SEL_RMII;
623 debug("%s: PHY_INTERFACE_MODE_RMII\n", __func__);
624 break;
625 case PHY_INTERFACE_MODE_RGMII:
626 case PHY_INTERFACE_MODE_RGMII_ID:
627 case PHY_INTERFACE_MODE_RGMII_RXID:
628 case PHY_INTERFACE_MODE_RGMII_TXID:
629 if (eth_clk_sel_reg)
630 value = SYSCFG_PMCSETR_ETH_SEL_RGMII |
631 SYSCFG_PMCSETR_ETH_CLK_SEL;
632 else
633 value = SYSCFG_PMCSETR_ETH_SEL_RGMII;
634 debug("%s: PHY_INTERFACE_MODE_RGMII\n", __func__);
635 break;
636 default:
637 debug("%s: Do not manage %d interface\n",
638 __func__, interface_type);
639 /* Do not manage others interfaces */
640 return -EINVAL;
641 }
642
643 /* clear and set ETH configuration bits */
644 writel(SYSCFG_PMCSETR_ETH_SEL_MASK | SYSCFG_PMCSETR_ETH_SELMII |
645 SYSCFG_PMCSETR_ETH_REF_CLK_SEL | SYSCFG_PMCSETR_ETH_CLK_SEL,
646 syscfg + SYSCFG_PMCCLRR);
647 writel(value, syscfg + SYSCFG_PMCSETR);
648
649 return 0;
650 }
651
env_get_location(enum env_operation op,int prio)652 enum env_location env_get_location(enum env_operation op, int prio)
653 {
654 if (prio)
655 return ENVL_UNKNOWN;
656
657 #ifdef CONFIG_ENV_IS_IN_SPI_FLASH
658 return ENVL_SPI_FLASH;
659 #else
660 return ENVL_NOWHERE;
661 #endif
662 }
663
664 #if defined(CONFIG_OF_BOARD_SETUP)
ft_board_setup(void * blob,bd_t * bd)665 int ft_board_setup(void *blob, bd_t *bd)
666 {
667 return 0;
668 }
669 #endif
670
board_copro_image_process(ulong fw_image,size_t fw_size)671 static void board_copro_image_process(ulong fw_image, size_t fw_size)
672 {
673 int ret, id = 0; /* Copro id fixed to 0 as only one coproc on mp1 */
674
675 if (!rproc_is_initialized())
676 if (rproc_init()) {
677 printf("Remote Processor %d initialization failed\n",
678 id);
679 return;
680 }
681
682 ret = rproc_load(id, fw_image, fw_size);
683 printf("Load Remote Processor %d with data@addr=0x%08lx %u bytes:%s\n",
684 id, fw_image, fw_size, ret ? " Failed!" : " Success!");
685
686 if (!ret) {
687 rproc_start(id);
688 env_set("copro_state", "booted");
689 }
690 }
691
692 U_BOOT_FIT_LOADABLE_HANDLER(IH_TYPE_COPRO, board_copro_image_process);
693