1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2007,2010 Freescale Semiconductor, Inc.
4 * Dave Liu <daveliu@freescale.com>
5 */
6
7 #include <common.h>
8 #include <hwconfig.h>
9 #include <i2c.h>
10 #include <init.h>
11 #include <net.h>
12 #include <asm/bitops.h>
13 #include <asm/io.h>
14 #include <asm/fsl_mpc83xx_serdes.h>
15 #include <spd_sdram.h>
16 #include <tsec.h>
17 #include <linux/delay.h>
18 #include <linux/libfdt.h>
19 #include <fdt_support.h>
20 #include <fsl_esdhc.h>
21 #include <fsl_mdio.h>
22 #include <phy.h>
23 #include "pci.h"
24 #include "../common/pq-mds-pib.h"
25
26 DECLARE_GLOBAL_DATA_PTR;
27
board_early_init_f(void)28 int board_early_init_f(void)
29 {
30 u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;
31
32 /* Enable flash write */
33 bcsr[0x9] &= ~0x04;
34 /* Clear all of the interrupt of BCSR */
35 bcsr[0xe] = 0xff;
36
37 #ifdef CONFIG_FSL_SERDES
38 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
39 u32 spridr = in_be32(&immr->sysconf.spridr);
40
41 /* we check only part num, and don't look for CPU revisions */
42 switch (PARTID_NO_E(spridr)) {
43 case SPR_8377:
44 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
45 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
46 break;
47 case SPR_8378:
48 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SGMII,
49 FSL_SERDES_CLK_125, FSL_SERDES_VDD_1V);
50 break;
51 case SPR_8379:
52 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
53 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
54 fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA,
55 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
56 break;
57 default:
58 printf("serdes not configured: unknown CPU part number: "
59 "%04x\n", spridr >> 16);
60 break;
61 }
62 #endif /* CONFIG_FSL_SERDES */
63 return 0;
64 }
65
66 #ifdef CONFIG_FSL_ESDHC
board_mmc_init(bd_t * bd)67 int board_mmc_init(bd_t *bd)
68 {
69 struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
70 u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;
71
72 if (!hwconfig("esdhc"))
73 return 0;
74
75 /* Set SPI_SD, SER_SD, and IRQ4_WP so that SD signals go through */
76 bcsr[0xc] |= 0x4c;
77
78 /* Set proper bits in SICR to allow SD signals through */
79 clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD);
80 clrsetbits_be32(&im->sysconf.sicrh, SICRH_GPIO2_E | SICRH_SPI,
81 SICRH_GPIO2_E_SD | SICRH_SPI_SD);
82
83 return fsl_esdhc_mmc_init(bd);
84 }
85 #endif
86
87 #if defined(CONFIG_TSEC1) || defined(CONFIG_TSEC2)
board_eth_init(bd_t * bd)88 int board_eth_init(bd_t *bd)
89 {
90 struct fsl_pq_mdio_info mdio_info;
91 struct tsec_info_struct tsec_info[2];
92 struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
93 u32 rcwh = in_be32(&im->reset.rcwh);
94 u32 tsec_mode;
95 int num = 0;
96
97 /* New line after Net: */
98 printf("\n");
99
100 #ifdef CONFIG_TSEC1
101 SET_STD_TSEC_INFO(tsec_info[num], 1);
102
103 printf(CONFIG_TSEC1_NAME ": ");
104
105 tsec_mode = rcwh & HRCWH_TSEC1M_MASK;
106 if (tsec_mode == HRCWH_TSEC1M_IN_RGMII) {
107 printf("RGMII\n");
108 /* this is default, no need to fixup */
109 } else if (tsec_mode == HRCWH_TSEC1M_IN_SGMII) {
110 printf("SGMII\n");
111 tsec_info[num].phyaddr = TSEC1_PHY_ADDR_SGMII;
112 tsec_info[num].flags = TSEC_GIGABIT;
113 } else {
114 printf("unsupported PHY type\n");
115 }
116 num++;
117 #endif
118 #ifdef CONFIG_TSEC2
119 SET_STD_TSEC_INFO(tsec_info[num], 2);
120
121 printf(CONFIG_TSEC2_NAME ": ");
122
123 tsec_mode = rcwh & HRCWH_TSEC2M_MASK;
124 if (tsec_mode == HRCWH_TSEC2M_IN_RGMII) {
125 printf("RGMII\n");
126 /* this is default, no need to fixup */
127 } else if (tsec_mode == HRCWH_TSEC2M_IN_SGMII) {
128 printf("SGMII\n");
129 tsec_info[num].phyaddr = TSEC2_PHY_ADDR_SGMII;
130 tsec_info[num].flags = TSEC_GIGABIT;
131 } else {
132 printf("unsupported PHY type\n");
133 }
134 num++;
135 #endif
136
137 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
138 mdio_info.name = DEFAULT_MII_NAME;
139 fsl_pq_mdio_init(bd, &mdio_info);
140
141 return tsec_eth_init(bd, tsec_info, num);
142 }
143
__ft_tsec_fixup(void * blob,bd_t * bd,const char * alias,int phy_addr)144 static void __ft_tsec_fixup(void *blob, bd_t *bd, const char *alias,
145 int phy_addr)
146 {
147 const u32 *ph;
148 int off;
149 int err;
150
151 off = fdt_path_offset(blob, alias);
152 if (off < 0) {
153 printf("WARNING: could not find %s alias: %s.\n", alias,
154 fdt_strerror(off));
155 return;
156 }
157
158 err = fdt_fixup_phy_connection(blob, off, PHY_INTERFACE_MODE_SGMII);
159
160 if (err) {
161 printf("WARNING: could not set phy-connection-type for %s: "
162 "%s.\n", alias, fdt_strerror(err));
163 return;
164 }
165
166 ph = (u32 *)fdt_getprop(blob, off, "phy-handle", 0);
167 if (!ph) {
168 printf("WARNING: could not get phy-handle for %s.\n",
169 alias);
170 return;
171 }
172
173 off = fdt_node_offset_by_phandle(blob, *ph);
174 if (off < 0) {
175 printf("WARNING: could not get phy node for %s: %s\n", alias,
176 fdt_strerror(off));
177 return;
178 }
179
180 phy_addr = cpu_to_fdt32(phy_addr);
181 err = fdt_setprop(blob, off, "reg", &phy_addr, sizeof(phy_addr));
182 if (err < 0) {
183 printf("WARNING: could not set phy node's reg for %s: "
184 "%s.\n", alias, fdt_strerror(err));
185 return;
186 }
187 }
188
ft_tsec_fixup(void * blob,bd_t * bd)189 static void ft_tsec_fixup(void *blob, bd_t *bd)
190 {
191 struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
192 u32 rcwh = in_be32(&im->reset.rcwh);
193 u32 tsec_mode;
194
195 #ifdef CONFIG_TSEC1
196 tsec_mode = rcwh & HRCWH_TSEC1M_MASK;
197 if (tsec_mode == HRCWH_TSEC1M_IN_SGMII)
198 __ft_tsec_fixup(blob, bd, "ethernet0", TSEC1_PHY_ADDR_SGMII);
199 #endif
200
201 #ifdef CONFIG_TSEC2
202 tsec_mode = rcwh & HRCWH_TSEC2M_MASK;
203 if (tsec_mode == HRCWH_TSEC2M_IN_SGMII)
204 __ft_tsec_fixup(blob, bd, "ethernet1", TSEC2_PHY_ADDR_SGMII);
205 #endif
206 }
207 #else
ft_tsec_fixup(void * blob,bd_t * bd)208 static inline void ft_tsec_fixup(void *blob, bd_t *bd) {}
209 #endif /* defined(CONFIG_TSEC1) || defined(CONFIG_TSEC2) */
210
board_early_init_r(void)211 int board_early_init_r(void)
212 {
213 #ifdef CONFIG_PQ_MDS_PIB
214 pib_init();
215 #endif
216 return 0;
217 }
218
219 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
220 extern void ddr_enable_ecc(unsigned int dram_size);
221 #endif
222 int fixed_sdram(void);
223
dram_init(void)224 int dram_init(void)
225 {
226 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
227 u32 msize = 0;
228
229 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
230 return -ENXIO;
231
232 #if defined(CONFIG_SPD_EEPROM)
233 msize = spd_sdram();
234 #else
235 msize = fixed_sdram();
236 #endif
237
238 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
239 /* Initialize DDR ECC byte */
240 ddr_enable_ecc(msize * 1024 * 1024);
241 #endif
242
243 /* return total bus DDR size(bytes) */
244 gd->ram_size = msize * 1024 * 1024;
245
246 return 0;
247 }
248
249 #if !defined(CONFIG_SPD_EEPROM)
250 /*************************************************************************
251 * fixed sdram init -- doesn't use serial presence detect.
252 ************************************************************************/
fixed_sdram(void)253 int fixed_sdram(void)
254 {
255 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
256 u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
257 u32 msize_log2 = __ilog2(msize);
258
259 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
260 im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
261
262 #if (CONFIG_SYS_DDR_SIZE != 512)
263 #warning Currenly any ddr size other than 512 is not supported
264 #endif
265 im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
266 udelay(50000);
267
268 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
269 udelay(1000);
270
271 im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
272 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
273 udelay(1000);
274
275 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
276 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
277 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
278 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
279 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
280 im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
281 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
282 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
283 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
284 __asm__ __volatile__("sync");
285 udelay(1000);
286
287 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
288 udelay(2000);
289 return CONFIG_SYS_DDR_SIZE;
290 }
291 #endif /*!CONFIG_SYS_SPD_EEPROM */
292
checkboard(void)293 int checkboard(void)
294 {
295 puts("Board: Freescale MPC837xEMDS\n");
296 return 0;
297 }
298
299 #ifdef CONFIG_PCI
board_pci_host_broken(void)300 int board_pci_host_broken(void)
301 {
302 struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
303 const u32 rcw_mask = HRCWH_PCI1_ARBITER_ENABLE | HRCWH_PCI_HOST;
304
305 /* It's always OK in case of external arbiter. */
306 if (hwconfig_subarg_cmp("pci", "arbiter", "external"))
307 return 0;
308
309 if ((in_be32(&im->reset.rcwh) & rcw_mask) != rcw_mask)
310 return 1;
311
312 return 0;
313 }
314
ft_pci_fixup(void * blob,bd_t * bd)315 static void ft_pci_fixup(void *blob, bd_t *bd)
316 {
317 const char *status = "broken (no arbiter)";
318 int off;
319 int err;
320
321 off = fdt_path_offset(blob, "pci0");
322 if (off < 0) {
323 printf("WARNING: could not find pci0 alias: %s.\n",
324 fdt_strerror(off));
325 return;
326 }
327
328 err = fdt_setprop(blob, off, "status", status, strlen(status) + 1);
329 if (err) {
330 printf("WARNING: could not set status for pci0: %s.\n",
331 fdt_strerror(err));
332 return;
333 }
334 }
335 #endif
336
337 #if defined(CONFIG_OF_BOARD_SETUP)
ft_board_setup(void * blob,bd_t * bd)338 int ft_board_setup(void *blob, bd_t *bd)
339 {
340 ft_cpu_setup(blob, bd);
341 ft_tsec_fixup(blob, bd);
342 fsl_fdt_fixup_dr_usb(blob, bd);
343 fdt_fixup_esdhc(blob, bd);
344 #ifdef CONFIG_PCI
345 ft_pci_setup(blob, bd);
346 if (board_pci_host_broken())
347 ft_pci_fixup(blob, bd);
348 ft_pcie_fixup(blob, bd);
349 #endif
350
351 return 0;
352 }
353 #endif /* CONFIG_OF_BOARD_SETUP */
354