1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2007,2009-2010 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <command.h>
8 #include <init.h>
9 #include <net.h>
10 #include <pci.h>
11 #include <asm/processor.h>
12 #include <asm/mmu.h>
13 #include <asm/immap_85xx.h>
14 #include <asm/fsl_pci.h>
15 #include <fsl_ddr_sdram.h>
16 #include <asm/fsl_serdes.h>
17 #include <asm/io.h>
18 #include <miiphy.h>
19 #include <linux/libfdt.h>
20 #include <fdt_support.h>
21 #include <fsl_mdio.h>
22 #include <tsec.h>
23 #include <netdev.h>
24
25 #include "../common/sgmii_riser.h"
26
checkboard(void)27 int checkboard (void)
28 {
29 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
30 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
31 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
32 u8 vboot;
33 u8 *pixis_base = (u8 *)PIXIS_BASE;
34
35 if ((uint)&gur->porpllsr != 0xe00e0000) {
36 printf("immap size error %lx\n",(ulong)&gur->porpllsr);
37 }
38 printf ("Board: MPC8544DS, Sys ID: 0x%02x, "
39 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
40 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
41 in_8(pixis_base + PIXIS_PVER));
42
43 vboot = in_8(pixis_base + PIXIS_VBOOT);
44 if (vboot & PIXIS_VBOOT_FMAP)
45 printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6));
46 else
47 puts ("Promjet\n");
48
49 lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
50 lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
51 ecm->eedr = 0xffffffff; /* Clear ecm errors */
52 ecm->eeer = 0xffffffff; /* Enable ecm errors */
53
54 return 0;
55 }
56
57 #ifdef CONFIG_PCI1
58 static struct pci_controller pci1_hose;
59 #endif
60
61 #ifdef CONFIG_PCIE3
62 static struct pci_controller pcie3_hose;
63 #endif
64
pci_init_board(void)65 void pci_init_board(void)
66 {
67 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
68 struct fsl_pci_info pci_info;
69 u32 devdisr, pordevsr, io_sel;
70 u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
71 int first_free_busno = 0;
72
73 int pcie_ep, pcie_configured;
74
75 devdisr = in_be32(&gur->devdisr);
76 pordevsr = in_be32(&gur->pordevsr);
77 porpllsr = in_be32(&gur->porpllsr);
78 io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
79
80 debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
81
82 puts("\n");
83
84 #ifdef CONFIG_PCIE3
85 pcie_configured = is_serdes_configured(PCIE3);
86
87 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
88 /* contains both PCIE3 MEM & IO space */
89 set_next_law(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_4M,
90 LAW_TRGT_IF_PCIE_3);
91 SET_STD_PCIE_INFO(pci_info, 3);
92 pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info.regs);
93
94 /* outbound memory */
95 pci_set_region(&pcie3_hose.regions[0],
96 CONFIG_SYS_PCIE3_MEM_BUS2,
97 CONFIG_SYS_PCIE3_MEM_PHYS2,
98 CONFIG_SYS_PCIE3_MEM_SIZE2,
99 PCI_REGION_MEM);
100
101 pcie3_hose.region_count = 1;
102
103 printf("PCIE3: connected to ULI as %s (base addr %lx)\n",
104 pcie_ep ? "Endpoint" : "Root Complex",
105 pci_info.regs);
106 first_free_busno = fsl_pci_init_port(&pci_info,
107 &pcie3_hose, first_free_busno);
108
109 /*
110 * Activate ULI1575 legacy chip by performing a fake
111 * memory access. Needed to make ULI RTC work.
112 */
113 in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BUS);
114 } else {
115 printf("PCIE3: disabled\n");
116 }
117 puts("\n");
118 #else
119 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
120 #endif
121
122 #ifdef CONFIG_PCIE1
123 SET_STD_PCIE_INFO(pci_info, 1);
124 first_free_busno = fsl_pcie_init_ctrl(first_free_busno, devdisr, PCIE1, &pci_info);
125 #else
126 setbits_be32(&gur->devdisr, _DEVDISR_PCIE1); /* disable */
127 #endif
128
129 #ifdef CONFIG_PCIE2
130 SET_STD_PCIE_INFO(pci_info, 2);
131 first_free_busno = fsl_pcie_init_ctrl(first_free_busno, devdisr, PCIE2, &pci_info);
132 #else
133 setbits_be32(&gur->devdisr, _DEVDISR_PCIE2); /* disable */
134 #endif
135
136 #ifdef CONFIG_PCI1
137 pci_speed = 66666000;
138 pci_32 = 1;
139 pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
140 pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
141
142 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
143 SET_STD_PCI_INFO(pci_info, 1);
144 set_next_law(pci_info.mem_phys,
145 law_size_bits(pci_info.mem_size), pci_info.law);
146 set_next_law(pci_info.io_phys,
147 law_size_bits(pci_info.io_size), pci_info.law);
148
149 pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
150 printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
151 (pci_32) ? 32 : 64,
152 (pci_speed == 33333000) ? "33" :
153 (pci_speed == 66666000) ? "66" : "unknown",
154 pci_clk_sel ? "sync" : "async",
155 pci_agent ? "agent" : "host",
156 pci_arb ? "arbiter" : "external-arbiter",
157 pci_info.regs);
158
159 first_free_busno = fsl_pci_init_port(&pci_info,
160 &pci1_hose, first_free_busno);
161 } else {
162 printf("PCI: disabled\n");
163 }
164
165 puts("\n");
166 #else
167 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
168 #endif
169 }
170
last_stage_init(void)171 int last_stage_init(void)
172 {
173 return 0;
174 }
175
176
177 unsigned long
get_board_sys_clk(ulong dummy)178 get_board_sys_clk(ulong dummy)
179 {
180 u8 i, go_bit, rd_clks;
181 ulong val = 0;
182 u8 *pixis_base = (u8 *)PIXIS_BASE;
183
184 go_bit = in_8(pixis_base + PIXIS_VCTL);
185 go_bit &= 0x01;
186
187 rd_clks = in_8(pixis_base + PIXIS_VCFGEN0);
188 rd_clks &= 0x1C;
189
190 /*
191 * Only if both go bit and the SCLK bit in VCFGEN0 are set
192 * should we be using the AUX register. Remember, we also set the
193 * GO bit to boot from the alternate bank on the on-board flash
194 */
195
196 if (go_bit) {
197 if (rd_clks == 0x1c)
198 i = in_8(pixis_base + PIXIS_AUX);
199 else
200 i = in_8(pixis_base + PIXIS_SPD);
201 } else {
202 i = in_8(pixis_base + PIXIS_SPD);
203 }
204
205 i &= 0x07;
206
207 switch (i) {
208 case 0:
209 val = 33333333;
210 break;
211 case 1:
212 val = 40000000;
213 break;
214 case 2:
215 val = 50000000;
216 break;
217 case 3:
218 val = 66666666;
219 break;
220 case 4:
221 val = 83000000;
222 break;
223 case 5:
224 val = 100000000;
225 break;
226 case 6:
227 val = 133333333;
228 break;
229 case 7:
230 val = 166666666;
231 break;
232 }
233
234 return val;
235 }
236
237
238 #define MIIM_CIS8204_SLED_CON 0x1b
239 #define MIIM_CIS8204_SLEDCON_INIT 0x1115
240 /*
241 * Hack to write all 4 PHYs with the LED values
242 */
board_phy_config(struct phy_device * phydev)243 int board_phy_config(struct phy_device *phydev)
244 {
245 static int do_once;
246 uint phyid;
247 struct mii_dev *bus = phydev->bus;
248
249 if (phydev->drv->config)
250 phydev->drv->config(phydev);
251 if (do_once)
252 return 0;
253
254 for (phyid = 0; phyid < 4; phyid++)
255 bus->write(bus, phyid, MDIO_DEVAD_NONE, MIIM_CIS8204_SLED_CON,
256 MIIM_CIS8204_SLEDCON_INIT);
257
258 do_once = 1;
259
260 return 0;
261 }
262
263
board_eth_init(bd_t * bis)264 int board_eth_init(bd_t *bis)
265 {
266 #ifdef CONFIG_TSEC_ENET
267 struct fsl_pq_mdio_info mdio_info;
268 struct tsec_info_struct tsec_info[2];
269 int num = 0;
270
271 #ifdef CONFIG_TSEC1
272 SET_STD_TSEC_INFO(tsec_info[num], 1);
273 if (is_serdes_configured(SGMII_TSEC1)) {
274 puts("eTSEC1 is in sgmii mode.\n");
275 tsec_info[num].flags |= TSEC_SGMII;
276 }
277 num++;
278 #endif
279 #ifdef CONFIG_TSEC3
280 SET_STD_TSEC_INFO(tsec_info[num], 3);
281 if (is_serdes_configured(SGMII_TSEC3)) {
282 puts("eTSEC3 is in sgmii mode.\n");
283 tsec_info[num].flags |= TSEC_SGMII;
284 }
285 num++;
286 #endif
287
288 if (!num) {
289 printf("No TSECs initialized\n");
290
291 return 0;
292 }
293
294 if (is_serdes_configured(SGMII_TSEC1) ||
295 is_serdes_configured(SGMII_TSEC3)) {
296 fsl_sgmii_riser_init(tsec_info, num);
297 }
298
299 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
300 mdio_info.name = DEFAULT_MII_NAME;
301 fsl_pq_mdio_init(bis, &mdio_info);
302
303 tsec_eth_init(bis, tsec_info, num);
304 #endif
305 return pci_eth_init(bis);
306 }
307
308 #if defined(CONFIG_OF_BOARD_SETUP)
ft_board_setup(void * blob,bd_t * bd)309 int ft_board_setup(void *blob, bd_t *bd)
310 {
311 ft_cpu_setup(blob, bd);
312
313 FT_FSL_PCI_SETUP;
314
315 #ifdef CONFIG_FSL_SGMII_RISER
316 fsl_sgmii_riser_fdt_fixup(blob);
317 #endif
318
319 return 0;
320 }
321 #endif
322