1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Board functions for Siemens TAURUS (AT91SAM9G20) based boards
4 * (C) Copyright Siemens AG
5 *
6 * Based on:
7 * U-Boot file: board/atmel/at91sam9260ek/at91sam9260ek.c
8 *
9 * (C) Copyright 2007-2008
10 * Stelian Pop <stelian@popies.net>
11 * Lead Tech Design <www.leadtechdesign.com>
12 */
13
14 #include <command.h>
15 #include <common.h>
16 #include <dm.h>
17 #include <env.h>
18 #include <flash.h>
19 #include <init.h>
20 #include <asm/io.h>
21 #include <asm/arch/at91sam9260_matrix.h>
22 #include <asm/arch/at91sam9_smc.h>
23 #include <asm/arch/at91_common.h>
24 #include <asm/arch/at91_rstc.h>
25 #include <asm/arch/gpio.h>
26 #include <asm/arch/at91sam9_sdramc.h>
27 #include <asm/arch/atmel_serial.h>
28 #include <asm/arch/clk.h>
29 #include <asm/gpio.h>
30 #include <linux/mtd/rawnand.h>
31 #include <atmel_mci.h>
32 #include <asm/arch/at91_spi.h>
33 #include <spi.h>
34
35 #include <net.h>
36 #ifndef CONFIG_DM_ETH
37 #include <netdev.h>
38 #endif
39
40 DECLARE_GLOBAL_DATA_PTR;
41
taurus_request_gpio(void)42 static void taurus_request_gpio(void)
43 {
44 gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand ena");
45 gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand rdy");
46 gpio_request(AT91_PIN_PA25, "ena PHY");
47 }
48
taurus_nand_hw_init(void)49 static void taurus_nand_hw_init(void)
50 {
51 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
52 struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
53 unsigned long csa;
54
55 /* Assign CS3 to NAND/SmartMedia Interface */
56 csa = readl(&matrix->ebicsa);
57 csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
58 writel(csa, &matrix->ebicsa);
59
60 /* Configure SMC CS3 for NAND/SmartMedia */
61 writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
62 AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
63 &smc->cs[3].setup);
64 writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) |
65 AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(3),
66 &smc->cs[3].pulse);
67 writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
68 &smc->cs[3].cycle);
69 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
70 AT91_SMC_MODE_EXNW_DISABLE |
71 AT91_SMC_MODE_DBW_8 |
72 AT91_SMC_MODE_TDF_CYCLE(3),
73 &smc->cs[3].mode);
74
75 /* Configure RDY/BSY */
76 at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
77
78 /* Enable NandFlash */
79 at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
80 }
81
82 #if defined(CONFIG_SPL_BUILD)
83 #include <spl.h>
84 #include <nand.h>
85 #include <spi_flash.h>
86
matrix_init(void)87 void matrix_init(void)
88 {
89 struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX;
90
91 writel((readl(&mat->scfg[3]) & (~AT91_MATRIX_SLOT_CYCLE))
92 | AT91_MATRIX_SLOT_CYCLE_(0x40),
93 &mat->scfg[3]);
94 }
95
96 #if defined(CONFIG_BOARD_AXM)
at91_is_recovery(void)97 static int at91_is_recovery(void)
98 {
99 if ((at91_get_gpio_value(AT91_PIN_PA26) == 0) &&
100 (at91_get_gpio_value(AT91_PIN_PA27) == 0))
101 return 1;
102
103 return 0;
104 }
105 #elif defined(CONFIG_BOARD_TAURUS)
at91_is_recovery(void)106 static int at91_is_recovery(void)
107 {
108 if (at91_get_gpio_value(AT91_PIN_PA31) == 0)
109 return 1;
110
111 return 0;
112 }
113 #endif
114
spl_board_init(void)115 void spl_board_init(void)
116 {
117 taurus_nand_hw_init();
118 at91_spi0_hw_init(TAURUS_SPI_MASK);
119
120 #if defined(CONFIG_BOARD_AXM)
121 /* Configure LED PINs */
122 at91_set_gpio_output(AT91_PIN_PA6, 0);
123 at91_set_gpio_output(AT91_PIN_PA8, 0);
124 at91_set_gpio_output(AT91_PIN_PA9, 0);
125 at91_set_gpio_output(AT91_PIN_PA10, 0);
126 at91_set_gpio_output(AT91_PIN_PA11, 0);
127 at91_set_gpio_output(AT91_PIN_PA12, 0);
128
129 /* Configure recovery button PINs */
130 at91_set_gpio_input(AT91_PIN_PA26, 1);
131 at91_set_gpio_input(AT91_PIN_PA27, 1);
132 #elif defined(CONFIG_BOARD_TAURUS)
133 at91_set_gpio_input(AT91_PIN_PA31, 1);
134 #endif
135
136 /* check for recovery mode */
137 if (at91_is_recovery() == 1) {
138 struct spi_flash *flash;
139
140 puts("Recovery button pressed\n");
141 nand_init();
142 spl_nand_erase_one(0, 0);
143 flash = spi_flash_probe(CONFIG_SF_DEFAULT_BUS,
144 0,
145 CONFIG_SF_DEFAULT_SPEED,
146 CONFIG_SF_DEFAULT_MODE);
147 if (!flash) {
148 puts("no flash\n");
149 } else {
150 puts("erase spi flash sector 0\n");
151 spi_flash_erase(flash, 0,
152 CONFIG_SYS_NAND_U_BOOT_SIZE);
153 }
154 }
155 }
156
157 #define SDRAM_BASE_CONF (AT91_SDRAMC_NR_13 | AT91_SDRAMC_CAS_3 \
158 |AT91_SDRAMC_NB_4 | AT91_SDRAMC_DBW_32 \
159 | AT91_SDRAMC_TWR_VAL(3) | AT91_SDRAMC_TRC_VAL(9) \
160 | AT91_SDRAMC_TRP_VAL(3) | AT91_SDRAMC_TRCD_VAL(3) \
161 | AT91_SDRAMC_TRAS_VAL(6) | AT91_SDRAMC_TXSR_VAL(10))
162
sdramc_configure(unsigned int mask)163 void sdramc_configure(unsigned int mask)
164 {
165 struct at91_matrix *ma = (struct at91_matrix *)ATMEL_BASE_MATRIX;
166 struct sdramc_reg setting;
167
168 at91_sdram_hw_init();
169 setting.cr = SDRAM_BASE_CONF | mask;
170 setting.mdr = AT91_SDRAMC_MD_SDRAM;
171 setting.tr = (CONFIG_SYS_MASTER_CLOCK * 7) / 1000000;
172
173 writel(readl(&ma->ebicsa) | AT91_MATRIX_CS1A_SDRAMC |
174 AT91_MATRIX_VDDIOMSEL_3_3V | AT91_MATRIX_EBI_IOSR_SEL,
175 &ma->ebicsa);
176
177 sdramc_initialize(ATMEL_BASE_CS1, &setting);
178 }
179
mem_init(void)180 void mem_init(void)
181 {
182 unsigned int ram_size = 0;
183
184 /* Configure SDRAM for 128MB */
185 sdramc_configure(AT91_SDRAMC_NC_10);
186
187 /* Do memtest for 128MB */
188 ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
189 CONFIG_SYS_SDRAM_SIZE);
190
191 /*
192 * If 32MB or 16MB should be supported check also for
193 * expected mirroring at A16 and A17
194 * To find mirror addresses depends how the collumns are connected
195 * at RAM (internaly or externaly)
196 * If the collumns are not in inverted order the mirror size effect
197 * behaves like normal SRAM with A0,A1,A2,etc. connected incremantal
198 */
199
200 /* Mirrors at A15 on ATMEL G20 SDRAM Controller with 64MB*/
201 if (ram_size == 0x800) {
202 printf("\n\r 64MB\n");
203 sdramc_configure(AT91_SDRAMC_NC_9);
204 } else {
205 /* Size already initialized */
206 printf("\n\r 128MB\n");
207 }
208 }
209 #endif
210
211 #ifdef CONFIG_MACB
siemens_phy_reset(void)212 static void siemens_phy_reset(void)
213 {
214 /*
215 * we need to reset PHY for 200us
216 * because of bug in ATMEL G20 CPU (undefined initial state of GPIO)
217 */
218 if ((readl(AT91_ASM_RSTC_SR) & AT91_RSTC_RSTTYP) ==
219 AT91_RSTC_RSTTYP_GENERAL)
220 at91_set_gpio_value(AT91_PIN_PA25, 0); /* reset eth switch */
221 }
222
taurus_macb_hw_init(void)223 static void taurus_macb_hw_init(void)
224 {
225 /* Enable EMAC clock */
226 at91_periph_clk_enable(ATMEL_ID_EMAC0);
227
228 /*
229 * Disable pull-up on:
230 * RXDV (PA17) => PHY normal mode (not Test mode)
231 * ERX0 (PA14) => PHY ADDR0
232 * ERX1 (PA15) => PHY ADDR1
233 * ERX2 (PA25) => PHY ADDR2
234 * ERX3 (PA26) => PHY ADDR3
235 * ECRS (PA28) => PHY ADDR4 => PHYADDR = 0x0
236 *
237 * PHY has internal pull-down
238 */
239 at91_set_pio_pullup(AT91_PIO_PORTA, 14, 0);
240 at91_set_pio_pullup(AT91_PIO_PORTA, 15, 0);
241 at91_set_pio_pullup(AT91_PIO_PORTA, 17, 0);
242 at91_set_pio_pullup(AT91_PIO_PORTA, 25, 0);
243 at91_set_pio_pullup(AT91_PIO_PORTA, 26, 0);
244 at91_set_pio_pullup(AT91_PIO_PORTA, 28, 0);
245
246 siemens_phy_reset();
247
248 at91_phy_reset();
249
250 at91_set_gpio_input(AT91_PIN_PA25, 1); /* ERST tri-state */
251
252 /* Re-enable pull-up */
253 at91_set_pio_pullup(AT91_PIO_PORTA, 14, 1);
254 at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1);
255 at91_set_pio_pullup(AT91_PIO_PORTA, 17, 1);
256 at91_set_pio_pullup(AT91_PIO_PORTA, 25, 1);
257 at91_set_pio_pullup(AT91_PIO_PORTA, 26, 1);
258 at91_set_pio_pullup(AT91_PIO_PORTA, 28, 1);
259
260 /* Initialize EMAC=MACB hardware */
261 at91_macb_hw_init();
262 }
263 #endif
264
265 #ifdef CONFIG_GENERIC_ATMEL_MCI
board_mmc_init(bd_t * bd)266 int board_mmc_init(bd_t *bd)
267 {
268 at91_mci_hw_init();
269
270 return atmel_mci_init((void *)ATMEL_BASE_MCI);
271 }
272 #endif
273
board_early_init_f(void)274 int board_early_init_f(void)
275 {
276 /* Enable clocks for all PIOs */
277 at91_periph_clk_enable(ATMEL_ID_PIOA);
278 at91_periph_clk_enable(ATMEL_ID_PIOB);
279 at91_periph_clk_enable(ATMEL_ID_PIOC);
280
281 at91_seriald_hw_init();
282 taurus_request_gpio();
283
284 return 0;
285 }
286
287 #ifdef CONFIG_USB_GADGET_AT91
288 #include <linux/usb/at91_udc.h>
289
at91_udp_hw_init(void)290 void at91_udp_hw_init(void)
291 {
292 /* Enable PLLB */
293 at91_pllb_clk_enable(get_pllb_init());
294
295 /* Enable UDPCK clock, MCK is enabled in at91_clock_init() */
296 at91_periph_clk_enable(ATMEL_ID_UDP);
297
298 at91_system_clk_enable(AT91SAM926x_PMC_UDP);
299 }
300
301 struct at91_udc_data board_udc_data = {
302 .baseaddr = ATMEL_BASE_UDP0,
303 };
304 #endif
305
board_init(void)306 int board_init(void)
307 {
308 /* adress of boot parameters */
309 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
310
311 taurus_request_gpio();
312 #ifdef CONFIG_CMD_NAND
313 taurus_nand_hw_init();
314 #endif
315 #ifdef CONFIG_MACB
316 taurus_macb_hw_init();
317 #endif
318 at91_spi0_hw_init(TAURUS_SPI_MASK);
319 #ifdef CONFIG_USB_GADGET_AT91
320 at91_udp_hw_init();
321 at91_udc_probe(&board_udc_data);
322 #endif
323
324 return 0;
325 }
326
dram_init(void)327 int dram_init(void)
328 {
329 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
330 CONFIG_SYS_SDRAM_SIZE);
331 return 0;
332 }
333
334 #if !defined(CONFIG_SPL_BUILD)
335 #if defined(CONFIG_BOARD_AXM)
336 /*
337 * Booting the Fallback Image.
338 *
339 * The function is used to provide and
340 * boot the image with the fallback
341 * parameters, incase if the faulty image
342 * in upgraded over the base firmware.
343 *
344 */
upgrade_failure_fallback(void)345 static int upgrade_failure_fallback(void)
346 {
347 char *partitionset_active = NULL;
348 char *rootfs = NULL;
349 char *rootfs_fallback = NULL;
350 char *kern_off;
351 char *kern_off_fb;
352 char *kern_size;
353 char *kern_size_fb;
354
355 partitionset_active = env_get("partitionset_active");
356 if (partitionset_active) {
357 if (partitionset_active[0] == 'A')
358 env_set("partitionset_active", "B");
359 else
360 env_set("partitionset_active", "A");
361 } else {
362 printf("partitionset_active missing.\n");
363 return -ENOENT;
364 }
365
366 rootfs = env_get("rootfs");
367 rootfs_fallback = env_get("rootfs_fallback");
368 env_set("rootfs", rootfs_fallback);
369 env_set("rootfs_fallback", rootfs);
370
371 kern_size = env_get("kernel_size");
372 kern_size_fb = env_get("kernel_size_fallback");
373 env_set("kernel_size", kern_size_fb);
374 env_set("kernel_size_fallback", kern_size);
375
376 kern_off = env_get("kernel_Off");
377 kern_off_fb = env_get("kernel_Off_fallback");
378 env_set("kernel_Off", kern_off_fb);
379 env_set("kernel_Off_fallback", kern_off);
380
381 env_set("bootargs", '\0');
382 env_set("upgrade_available", '\0');
383 env_set("boot_retries", '\0');
384 env_save();
385
386 return 0;
387 }
388
do_upgrade_available(struct cmd_tbl * cmdtp,int flag,int argc,char * const argv[])389 static int do_upgrade_available(struct cmd_tbl *cmdtp, int flag, int argc,
390 char *const argv[])
391 {
392 unsigned long upgrade_available = 0;
393 unsigned long boot_retry = 0;
394 char boot_buf[10];
395
396 upgrade_available = simple_strtoul(env_get("upgrade_available"), NULL,
397 10);
398 if (upgrade_available) {
399 boot_retry = simple_strtoul(env_get("boot_retries"), NULL, 10);
400 boot_retry++;
401 sprintf(boot_buf, "%lx", boot_retry);
402 env_set("boot_retries", boot_buf);
403 env_save();
404
405 /*
406 * Here the boot_retries count is checked, and if the
407 * count becomes greater than 2 switch back to the
408 * fallback, and reset the board.
409 */
410
411 if (boot_retry > 2) {
412 if (upgrade_failure_fallback() == 0)
413 do_reset(NULL, 0, 0, NULL);
414 return -1;
415 }
416 }
417 return 0;
418 }
419
420 U_BOOT_CMD(
421 upgrade_available, 1, 1, do_upgrade_available,
422 "check Siemens update",
423 "no parameters"
424 );
425 #endif
426 #endif
427