1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. 4 * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com 5 * 6 */ 7 8 #ifndef __CONFIG_H 9 #define __CONFIG_H 10 11 #include <linux/stringify.h> 12 13 /* 14 * High Level Configuration Options 15 */ 16 #define CONFIG_E300 1 /* E300 family */ 17 18 #ifdef CONFIG_MMC 19 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR 20 #define CONFIG_SYS_FSL_ESDHC_USE_PIO 21 #endif 22 23 /* 24 * On-board devices 25 * 26 * TSEC1 is SoC TSEC 27 * TSEC2 is VSC switch 28 */ 29 #define CONFIG_TSEC1 30 #define CONFIG_VSC7385_ENET 31 32 /* 33 * SERDES 34 */ 35 #define CONFIG_FSL_SERDES 36 #define CONFIG_FSL_SERDES1 0xe3000 37 38 /* 39 * DDR Setup 40 */ 41 #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ 42 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 43 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 44 | DDRCDR_PZ_LOZ \ 45 | DDRCDR_NZ_LOZ \ 46 | DDRCDR_ODT \ 47 | DDRCDR_Q_DRN) 48 /* 0x7b880001 */ 49 /* 50 * Manually set up DDR parameters 51 * consist of two chips HY5PS12621BFP-C4 from HYNIX 52 */ 53 54 #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 55 56 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 57 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 58 | CSCONFIG_ODT_RD_NEVER \ 59 | CSCONFIG_ODT_WR_ONLY_CURRENT \ 60 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) 61 /* 0x80010102 */ 62 #define CONFIG_SYS_DDR_TIMING_3 0x00000000 63 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 64 | (0 << TIMING_CFG0_WRT_SHIFT) \ 65 | (0 << TIMING_CFG0_RRT_SHIFT) \ 66 | (0 << TIMING_CFG0_WWT_SHIFT) \ 67 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 68 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 69 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 70 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 71 /* 0x00220802 */ 72 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ 73 | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 74 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ 75 | (5 << TIMING_CFG1_CASLAT_SHIFT) \ 76 | (6 << TIMING_CFG1_REFREC_SHIFT) \ 77 | (2 << TIMING_CFG1_WRREC_SHIFT) \ 78 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 79 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 80 /* 0x27256222 */ 81 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ 82 | (4 << TIMING_CFG2_CPO_SHIFT) \ 83 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 84 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 85 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 86 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 87 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) 88 /* 0x121048c5 */ 89 #define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \ 90 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 91 /* 0x03600100 */ 92 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 93 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 94 | SDRAM_CFG_DBW_32) 95 /* 0x43080000 */ 96 97 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ 98 #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \ 99 | (0x0232 << SDRAM_MODE_SD_SHIFT)) 100 /* ODT 150ohm CL=3, AL=1 on SDRAM */ 101 #define CONFIG_SYS_DDR_MODE2 0x00000000 102 103 /* 104 * Memory test 105 */ 106 107 /* 108 * The reserved memory 109 */ 110 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 111 112 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ 113 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 114 115 /* 116 * Initial RAM Base Address Setup 117 */ 118 #define CONFIG_SYS_INIT_RAM_LOCK 1 119 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 120 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ 121 #define CONFIG_SYS_GBL_DATA_OFFSET \ 122 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 123 124 /* 125 * FLASH on the Local Bus 126 */ 127 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 128 129 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 130 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */ 131 132 133 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 134 /* 127 64KB sectors and 8 8KB top sectors per device */ 135 #define CONFIG_SYS_MAX_FLASH_SECT 135 136 137 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 138 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 139 140 /* 141 * NAND Flash on the Local Bus 142 */ 143 #define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */ 144 #define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) /* 0x00008000 */ 145 /* 0xFFFF8396 */ 146 147 #ifdef CONFIG_VSC7385_ENET 148 #define CONFIG_TSEC2 149 /* VSC7385 Base address on CS2 */ 150 #define CONFIG_SYS_VSC7385_BASE 0xF0000000 151 #define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */ 152 /* 0xFFFE09FF */ 153 /* The flash address and size of the VSC7385 firmware image */ 154 #define CONFIG_VSC7385_IMAGE 0xFE7FE000 155 #define CONFIG_VSC7385_IMAGE_SIZE 8192 156 #endif 157 /* 158 * Serial Port 159 */ 160 #define CONFIG_SYS_NS16550_SERIAL 161 #define CONFIG_SYS_NS16550_REG_SIZE 1 162 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 163 164 #define CONFIG_SYS_BAUDRATE_TABLE \ 165 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 166 167 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 168 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 169 170 /* I2C */ 171 #define CONFIG_SYS_I2C 172 #define CONFIG_SYS_I2C_FSL 173 #define CONFIG_SYS_FSL_I2C_SPEED 400000 174 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 175 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 176 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 177 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 178 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 179 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } 180 181 /* 182 * SPI on header J8 183 * 184 * WARNING: enabling this will break TSEC2 (connected to the Vitesse switch) 185 * due to a pinmux conflict between GPIO9 (SPI chip select )and the TSEC2 pins. 186 */ 187 #ifdef CONFIG_MPC8XXX_SPI 188 #define CONFIG_USE_SPIFLASH 189 #endif 190 191 /* 192 * Board info - revision and where boot from 193 */ 194 #define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39 195 196 /* 197 * Config on-board RTC 198 */ 199 #define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */ 200 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ 201 202 /* 203 * General PCI 204 * Addresses are mapped 1-1. 205 */ 206 #define CONFIG_SYS_PCIE1_BASE 0xA0000000 207 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 208 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 209 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 210 #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 211 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 212 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 213 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 214 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 215 216 /* enable PCIE clock */ 217 #define CONFIG_SYS_SCCR_PCIEXP1CM 1 218 219 #define CONFIG_PCI_INDIRECT_BRIDGE 220 #define CONFIG_PCIE 221 222 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 223 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1 224 225 /* 226 * TSEC 227 */ 228 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 229 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 230 #define CONFIG_SYS_TSEC2_OFFSET 0x25000 231 #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) 232 233 /* 234 * TSEC ethernet configuration 235 */ 236 #define CONFIG_TSEC1_NAME "eTSEC0" 237 #define CONFIG_TSEC2_NAME "eTSEC1" 238 #define TSEC1_PHY_ADDR 2 239 #define TSEC2_PHY_ADDR 1 240 #define TSEC1_PHYIDX 0 241 #define TSEC2_PHYIDX 0 242 #define TSEC1_FLAGS TSEC_GIGABIT 243 #define TSEC2_FLAGS TSEC_GIGABIT 244 245 /* Options are: eTSEC[0-1] */ 246 #define CONFIG_ETHPRIME "eTSEC0" 247 248 /* 249 * Environment 250 */ 251 252 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 253 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 254 255 /* 256 * BOOTP options 257 */ 258 #define CONFIG_BOOTP_BOOTFILESIZE 259 260 /* 261 * Miscellaneous configurable options 262 */ 263 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 264 265 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 266 267 /* Boot Argument Buffer Size */ 268 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 269 270 /* 271 * For booting Linux, the board info and command line data 272 * have to be in the first 256 MB of memory, since this is 273 * the maximum mapped by the Linux kernel during initialization. 274 */ 275 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ 276 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 277 278 /* 279 * Environment Configuration 280 */ 281 282 #define CONFIG_ENV_OVERWRITE 283 284 #if defined(CONFIG_TSEC_ENET) 285 #define CONFIG_HAS_ETH0 286 #define CONFIG_HAS_ETH1 287 #endif 288 289 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 290 291 292 #define CONFIG_EXTRA_ENV_SETTINGS \ 293 "netdev=eth0\0" \ 294 "consoledev=ttyS0\0" \ 295 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 296 "nfsroot=${serverip}:${rootpath}\0" \ 297 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 298 "addip=setenv bootargs ${bootargs} " \ 299 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 300 ":${hostname}:${netdev}:off panic=1\0" \ 301 "addtty=setenv bootargs ${bootargs}" \ 302 " console=${consoledev},${baudrate}\0" \ 303 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 304 "addmisc=setenv bootargs ${bootargs}\0" \ 305 "kernel_addr=FE080000\0" \ 306 "fdt_addr=FE280000\0" \ 307 "ramdisk_addr=FE290000\0" \ 308 "u-boot=mpc8308rdb/u-boot.bin\0" \ 309 "kernel_addr_r=1000000\0" \ 310 "fdt_addr_r=C00000\0" \ 311 "hostname=mpc8308rdb\0" \ 312 "bootfile=mpc8308rdb/uImage\0" \ 313 "fdtfile=mpc8308rdb/mpc8308rdb.dtb\0" \ 314 "rootpath=/opt/eldk-4.2/ppc_6xx\0" \ 315 "flash_self=run ramargs addip addtty addmtd addmisc;" \ 316 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ 317 "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ 318 "bootm ${kernel_addr} - ${fdt_addr}\0" \ 319 "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ 320 "tftp ${fdt_addr_r} ${fdtfile};" \ 321 "run nfsargs addip addtty addmtd addmisc;" \ 322 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ 323 "bootcmd=run flash_self\0" \ 324 "load=tftp ${loadaddr} ${u-boot}\0" \ 325 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ 326 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ 327 " +${filesize};cp.b ${fileaddr} " \ 328 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ 329 "upd=run load update\0" \ 330 331 #endif /* __CONFIG_H */ 332