1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc. 4 */ 5 6 /* 7 * mpc8572ds board configuration file 8 * 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #include <linux/stringify.h> 14 15 #include "../board/freescale/common/ics307_clk.h" 16 17 #ifndef CONFIG_RESET_VECTOR_ADDRESS 18 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 19 #endif 20 21 #ifndef CONFIG_SYS_MONITOR_BASE 22 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 23 #endif 24 25 /* High Level Configuration Options */ 26 27 #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ 28 #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ 29 #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */ 30 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ 31 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ 32 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ 33 34 #define CONFIG_ENV_OVERWRITE 35 36 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 37 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */ 38 #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ 39 40 /* 41 * These can be toggled for performance analysis, otherwise use default. 42 */ 43 #define CONFIG_L2_CACHE /* toggle L2 cache */ 44 #define CONFIG_BTB /* toggle branch predition */ 45 46 #define CONFIG_ENABLE_36BIT_PHYS 1 47 48 #ifdef CONFIG_PHYS_64BIT 49 #define CONFIG_ADDR_MAP 1 50 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 51 #endif 52 53 /* 54 * Config the L2 Cache as L2 SRAM 55 */ 56 #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 57 #ifdef CONFIG_PHYS_64BIT 58 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull 59 #else 60 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 61 #endif 62 #define CONFIG_SYS_L2_SIZE (512 << 10) 63 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 64 65 #define CONFIG_SYS_CCSRBAR 0xffe00000 66 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 67 68 #if defined(CONFIG_NAND_SPL) 69 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE 70 #endif 71 72 /* DDR Setup */ 73 #define CONFIG_VERY_BIG_RAM 74 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ 75 #define CONFIG_DDR_SPD 76 77 #define CONFIG_DDR_ECC 78 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 79 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef 80 81 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 82 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 83 84 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 85 #define CONFIG_CHIP_SELECTS_PER_CTRL 2 86 87 /* I2C addresses of SPD EEPROMs */ 88 #define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */ 89 #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ 90 #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */ 91 92 /* These are used when DDR doesn't use SPD. */ 93 #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ 94 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F 95 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ 96 #define CONFIG_SYS_DDR_TIMING_3 0x00020000 97 #define CONFIG_SYS_DDR_TIMING_0 0x00260802 98 #define CONFIG_SYS_DDR_TIMING_1 0x626b2634 99 #define CONFIG_SYS_DDR_TIMING_2 0x062874cf 100 #define CONFIG_SYS_DDR_MODE_1 0x00440462 101 #define CONFIG_SYS_DDR_MODE_2 0x00000000 102 #define CONFIG_SYS_DDR_INTERVAL 0x0c300100 103 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef 104 #define CONFIG_SYS_DDR_CLK_CTRL 0x00800000 105 #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 106 #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 107 #define CONFIG_SYS_DDR_CONTROL 0xc3000008 /* Type = DDR2 */ 108 #define CONFIG_SYS_DDR_CONTROL2 0x24400000 109 110 #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d 111 #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 112 #define CONFIG_SYS_DDR_SBE 0x00010000 113 114 /* 115 * Make sure required options are set 116 */ 117 #ifndef CONFIG_SPD_EEPROM 118 #error ("CONFIG_SPD_EEPROM is required") 119 #endif 120 121 #undef CONFIG_CLOCKS_IN_MHZ 122 123 /* 124 * Memory map 125 * 126 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable 127 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable 128 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable 129 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable 130 * 131 * Localbus cacheable (TBD) 132 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable 133 * 134 * Localbus non-cacheable 135 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable 136 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable 137 * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable 138 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 139 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 140 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 141 */ 142 143 /* 144 * Local Bus Definitions 145 */ 146 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ 147 #ifdef CONFIG_PHYS_64BIT 148 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 149 #else 150 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 151 #endif 152 153 #define CONFIG_FLASH_BR_PRELIM \ 154 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V) 155 #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 156 157 #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 158 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 159 160 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 161 #define CONFIG_SYS_FLASH_QUIET_TEST 162 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 163 164 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 165 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 166 #undef CONFIG_SYS_FLASH_CHECKSUM 167 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 168 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 169 170 #undef CONFIG_SYS_RAMBOOT 171 172 #define CONFIG_SYS_FLASH_EMPTY_INFO 173 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 174 175 #define CONFIG_HWCONFIG /* enable hwconfig */ 176 #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ 177 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 178 #ifdef CONFIG_PHYS_64BIT 179 #define PIXIS_BASE_PHYS 0xfffdf0000ull 180 #else 181 #define PIXIS_BASE_PHYS PIXIS_BASE 182 #endif 183 184 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 185 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 186 187 #define PIXIS_ID 0x0 /* Board ID at offset 0 */ 188 #define PIXIS_VER 0x1 /* Board version at offset 1 */ 189 #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ 190 #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ 191 #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ 192 #define PIXIS_PWR 0x5 /* PIXIS Power status register */ 193 #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ 194 #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ 195 #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ 196 #define PIXIS_VCTL 0x10 /* VELA Control Register */ 197 #define PIXIS_VSTAT 0x11 /* VELA Status Register */ 198 #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ 199 #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ 200 #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ 201 #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ 202 #define PIXIS_VBOOT_LBMAP 0xc0 /* VBOOT - CFG_LBMAP */ 203 #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ 204 #define PIXIS_VBOOT_LBMAP_PJET 0x01 /* cfg_lbmap - boot from projet */ 205 #define PIXIS_VBOOT_LBMAP_NAND 0x02 /* cfg_lbmap - boot from NAND */ 206 #define PIXIS_VBOOT_LBMAP_NOR1 0x03 /* cfg_lbmap - boot from NOR 1 */ 207 #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ 208 #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ 209 #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ 210 #define PIXIS_VSYSCLK0 0x1C /* VELA SYSCLK0 Register */ 211 #define PIXIS_VSYSCLK1 0x1D /* VELA SYSCLK1 Register */ 212 #define PIXIS_VSYSCLK2 0x1E /* VELA SYSCLK2 Register */ 213 #define PIXIS_VDDRCLK0 0x1F /* VELA DDRCLK0 Register */ 214 #define PIXIS_VDDRCLK1 0x20 /* VELA DDRCLK1 Register */ 215 #define PIXIS_VDDRCLK2 0x21 /* VELA DDRCLK2 Register */ 216 #define PIXIS_VWATCH 0x24 /* Watchdog Register */ 217 #define PIXIS_LED 0x25 /* LED Register */ 218 219 #define PIXIS_SPD_SYSCLK_MASK 0x7 /* SYSCLK option */ 220 221 /* old pixis referenced names */ 222 #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ 223 #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ 224 #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0 225 #define PIXIS_VSPEED2_TSEC1SER 0x8 226 #define PIXIS_VSPEED2_TSEC2SER 0x4 227 #define PIXIS_VSPEED2_TSEC3SER 0x2 228 #define PIXIS_VSPEED2_TSEC4SER 0x1 229 #define PIXIS_VCFGEN1_TSEC1SER 0x20 230 #define PIXIS_VCFGEN1_TSEC2SER 0x20 231 #define PIXIS_VCFGEN1_TSEC3SER 0x20 232 #define PIXIS_VCFGEN1_TSEC4SER 0x20 233 #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \ 234 | PIXIS_VSPEED2_TSEC2SER \ 235 | PIXIS_VSPEED2_TSEC3SER \ 236 | PIXIS_VSPEED2_TSEC4SER) 237 #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \ 238 | PIXIS_VCFGEN1_TSEC2SER \ 239 | PIXIS_VCFGEN1_TSEC3SER \ 240 | PIXIS_VCFGEN1_TSEC4SER) 241 242 #define CONFIG_SYS_INIT_RAM_LOCK 1 243 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 244 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 245 246 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 247 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 248 249 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 250 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 251 252 #ifndef CONFIG_NAND_SPL 253 #define CONFIG_SYS_NAND_BASE 0xffa00000 254 #ifdef CONFIG_PHYS_64BIT 255 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 256 #else 257 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 258 #endif 259 #else 260 #define CONFIG_SYS_NAND_BASE 0xfff00000 261 #ifdef CONFIG_PHYS_64BIT 262 #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull 263 #else 264 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 265 #endif 266 #endif 267 268 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ 269 CONFIG_SYS_NAND_BASE + 0x40000, \ 270 CONFIG_SYS_NAND_BASE + 0x80000,\ 271 CONFIG_SYS_NAND_BASE + 0xC0000} 272 #define CONFIG_SYS_MAX_NAND_DEVICE 4 273 #define CONFIG_NAND_FSL_ELBC 1 274 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 275 #define CONFIG_SYS_NAND_MAX_OOBFREE 5 276 #define CONFIG_SYS_NAND_MAX_ECCPOS 56 277 278 /* NAND boot: 4K NAND loader config */ 279 #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 280 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) 281 #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) 282 #define CONFIG_SYS_NAND_U_BOOT_START \ 283 (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) 284 #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) 285 #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) 286 #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) 287 288 /* NAND flash config */ 289 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 290 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 291 | BR_PS_8 /* Port Size = 8 bit */ \ 292 | BR_MS_FCM /* MSEL = FCM */ \ 293 | BR_V) /* valid */ 294 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 295 | OR_FCM_PGS /* Large Page*/ \ 296 | OR_FCM_CSCT \ 297 | OR_FCM_CST \ 298 | OR_FCM_CHT \ 299 | OR_FCM_SCY_1 \ 300 | OR_FCM_TRLX \ 301 | OR_FCM_EHTR) 302 303 #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ 304 #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ 305 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 306 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 307 #define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \ 308 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 309 | BR_PS_8 /* Port Size = 8 bit */ \ 310 | BR_MS_FCM /* MSEL = FCM */ \ 311 | BR_V) /* valid */ 312 #define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 313 #define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\ 314 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 315 | BR_PS_8 /* Port Size = 8 bit */ \ 316 | BR_MS_FCM /* MSEL = FCM */ \ 317 | BR_V) /* valid */ 318 #define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 319 320 #define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)\ 321 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 322 | BR_PS_8 /* Port Size = 8 bit */ \ 323 | BR_MS_FCM /* MSEL = FCM */ \ 324 | BR_V) /* valid */ 325 #define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 326 327 /* Serial Port - controlled on board with jumper J8 328 * open - index 2 329 * shorted - index 1 330 */ 331 #define CONFIG_SYS_NS16550_SERIAL 332 #define CONFIG_SYS_NS16550_REG_SIZE 1 333 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 334 #ifdef CONFIG_NAND_SPL 335 #define CONFIG_NS16550_MIN_FUNCTIONS 336 #endif 337 338 #define CONFIG_SYS_BAUDRATE_TABLE \ 339 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} 340 341 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 342 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 343 344 /* I2C */ 345 #define CONFIG_SYS_I2C 346 #define CONFIG_SYS_I2C_FSL 347 #define CONFIG_SYS_FSL_I2C_SPEED 400000 348 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 349 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 350 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 351 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 352 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 353 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} } 354 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 355 356 /* 357 * I2C2 EEPROM 358 */ 359 #define CONFIG_ID_EEPROM 360 #ifdef CONFIG_ID_EEPROM 361 #define CONFIG_SYS_I2C_EEPROM_NXID 362 #endif 363 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 364 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 365 #define CONFIG_SYS_EEPROM_BUS_NUM 1 366 367 /* 368 * General PCI 369 * Memory space is mapped 1-1, but I/O space must start from 0. 370 */ 371 372 /* controller 3, direct to uli, tgtid 3, Base address 8000 */ 373 #define CONFIG_SYS_PCIE3_NAME "ULI" 374 #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 375 #ifdef CONFIG_PHYS_64BIT 376 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 377 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull 378 #else 379 #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 380 #define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000 381 #endif 382 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 383 #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000 384 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 385 #ifdef CONFIG_PHYS_64BIT 386 #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull 387 #else 388 #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 389 #endif 390 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 391 392 /* controller 2, Slot 2, tgtid 2, Base address 9000 */ 393 #define CONFIG_SYS_PCIE2_NAME "Slot 1" 394 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 395 #ifdef CONFIG_PHYS_64BIT 396 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 397 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 398 #else 399 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 400 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 401 #endif 402 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 403 #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 404 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 405 #ifdef CONFIG_PHYS_64BIT 406 #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull 407 #else 408 #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 409 #endif 410 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 411 412 /* controller 1, Slot 1, tgtid 1, Base address a000 */ 413 #define CONFIG_SYS_PCIE1_NAME "Slot 2" 414 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 415 #ifdef CONFIG_PHYS_64BIT 416 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 417 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull 418 #else 419 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 420 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 421 #endif 422 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 423 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 424 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 425 #ifdef CONFIG_PHYS_64BIT 426 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull 427 #else 428 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 429 #endif 430 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 431 432 #if defined(CONFIG_PCI) 433 434 /*PCIE video card used*/ 435 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT 436 437 /* video */ 438 439 #if defined(CONFIG_VIDEO) 440 #define CONFIG_BIOSEMU 441 #define CONFIG_ATI_RADEON_FB 442 #define CONFIG_VIDEO_LOGO 443 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 444 #endif 445 446 #undef CONFIG_EEPRO100 447 #undef CONFIG_TULIP 448 449 #ifndef CONFIG_PCI_PNP 450 #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS 451 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS 452 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 453 #endif 454 455 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 456 457 #ifdef CONFIG_SCSI_AHCI 458 #define CONFIG_SATA_ULI5288 459 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 460 #define CONFIG_SYS_SCSI_MAX_LUN 1 461 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) 462 #endif /* SCSI */ 463 464 #endif /* CONFIG_PCI */ 465 466 #if defined(CONFIG_TSEC_ENET) 467 468 #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ 469 #define CONFIG_TSEC1 1 470 #define CONFIG_TSEC1_NAME "eTSEC1" 471 #define CONFIG_TSEC2 1 472 #define CONFIG_TSEC2_NAME "eTSEC2" 473 #define CONFIG_TSEC3 1 474 #define CONFIG_TSEC3_NAME "eTSEC3" 475 #define CONFIG_TSEC4 1 476 #define CONFIG_TSEC4_NAME "eTSEC4" 477 478 #define CONFIG_PIXIS_SGMII_CMD 479 #define CONFIG_FSL_SGMII_RISER 1 480 #define SGMII_RISER_PHY_OFFSET 0x1c 481 482 #ifdef CONFIG_FSL_SGMII_RISER 483 #define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */ 484 #endif 485 486 #define TSEC1_PHY_ADDR 0 487 #define TSEC2_PHY_ADDR 1 488 #define TSEC3_PHY_ADDR 2 489 #define TSEC4_PHY_ADDR 3 490 491 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 492 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 493 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 494 #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 495 496 #define TSEC1_PHYIDX 0 497 #define TSEC2_PHYIDX 0 498 #define TSEC3_PHYIDX 0 499 #define TSEC4_PHYIDX 0 500 501 #define CONFIG_ETHPRIME "eTSEC1" 502 #endif /* CONFIG_TSEC_ENET */ 503 504 /* 505 * Environment 506 */ 507 508 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 509 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 510 511 /* 512 * USB 513 */ 514 515 #ifdef CONFIG_USB_EHCI_HCD 516 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 517 #define CONFIG_PCI_EHCI_DEVICE 0 518 #endif 519 520 #undef CONFIG_WATCHDOG /* watchdog disabled */ 521 522 /* 523 * Miscellaneous configurable options 524 */ 525 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 526 527 /* 528 * For booting Linux, the board info and command line data 529 * have to be in the first 64 MB of memory, since this is 530 * the maximum mapped by the Linux kernel during initialization. 531 */ 532 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 533 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 534 535 #if defined(CONFIG_CMD_KGDB) 536 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 537 #endif 538 539 /* 540 * Environment Configuration 541 */ 542 #if defined(CONFIG_TSEC_ENET) 543 #define CONFIG_HAS_ETH0 544 #define CONFIG_HAS_ETH1 545 #define CONFIG_HAS_ETH2 546 #define CONFIG_HAS_ETH3 547 #endif 548 549 #define CONFIG_IPADDR 192.168.1.254 550 551 #define CONFIG_HOSTNAME "unknown" 552 #define CONFIG_ROOTPATH "/opt/nfsroot" 553 #define CONFIG_BOOTFILE "uImage" 554 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 555 556 #define CONFIG_SERVERIP 192.168.1.1 557 #define CONFIG_GATEWAYIP 192.168.1.1 558 #define CONFIG_NETMASK 255.255.255.0 559 560 /* default location for tftp and bootm */ 561 #define CONFIG_LOADADDR 1000000 562 563 #define CONFIG_EXTRA_ENV_SETTINGS \ 564 "hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1,ecc=off\0" \ 565 "netdev=eth0\0" \ 566 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 567 "tftpflash=tftpboot $loadaddr $uboot; " \ 568 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ 569 " +$filesize; " \ 570 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ 571 " +$filesize; " \ 572 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 573 " $filesize; " \ 574 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ 575 " +$filesize; " \ 576 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ 577 " $filesize\0" \ 578 "consoledev=ttyS0\0" \ 579 "ramdiskaddr=2000000\0" \ 580 "ramdiskfile=8572ds/ramdisk.uboot\0" \ 581 "fdtaddr=1e00000\0" \ 582 "fdtfile=8572ds/mpc8572ds.dtb\0" \ 583 "bdev=sda3\0" 584 585 #define CONFIG_HDBOOT \ 586 "setenv bootargs root=/dev/$bdev rw " \ 587 "console=$consoledev,$baudrate $othbootargs;" \ 588 "tftp $loadaddr $bootfile;" \ 589 "tftp $fdtaddr $fdtfile;" \ 590 "bootm $loadaddr - $fdtaddr" 591 592 #define CONFIG_NFSBOOTCOMMAND \ 593 "setenv bootargs root=/dev/nfs rw " \ 594 "nfsroot=$serverip:$rootpath " \ 595 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 596 "console=$consoledev,$baudrate $othbootargs;" \ 597 "tftp $loadaddr $bootfile;" \ 598 "tftp $fdtaddr $fdtfile;" \ 599 "bootm $loadaddr - $fdtaddr" 600 601 #define CONFIG_RAMBOOTCOMMAND \ 602 "setenv bootargs root=/dev/ram rw " \ 603 "console=$consoledev,$baudrate $othbootargs;" \ 604 "tftp $ramdiskaddr $ramdiskfile;" \ 605 "tftp $loadaddr $bootfile;" \ 606 "tftp $fdtaddr $fdtfile;" \ 607 "bootm $loadaddr $ramdiskaddr $fdtaddr" 608 609 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 610 611 #endif /* __CONFIG_H */ 612