1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2014 4 * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc 5 * 6 */ 7 8 #ifndef __CONFIG_H 9 #define __CONFIG_H 10 11 #include <linux/stringify.h> 12 13 /* 14 * High Level Configuration Options 15 */ 16 #define CONFIG_E300 1 /* E300 family */ 17 18 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR 19 20 /* 21 * SERDES 22 */ 23 #define CONFIG_FSL_SERDES 24 #define CONFIG_FSL_SERDES1 0xe3000 25 26 /* 27 * DDR Setup 28 */ 29 #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ 30 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 31 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ 32 | DDRCDR_PZ_LOZ \ 33 | DDRCDR_NZ_LOZ \ 34 | DDRCDR_ODT \ 35 | DDRCDR_Q_DRN) 36 /* 0x7b880001 */ 37 /* 38 * Manually set up DDR parameters 39 * consist of one chip NT5TU64M16HG from NANYA 40 */ 41 42 #define CONFIG_SYS_DDR_SIZE 128 /* MB */ 43 44 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 45 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ 46 | CSCONFIG_ODT_RD_NEVER \ 47 | CSCONFIG_ODT_WR_ONLY_CURRENT \ 48 | CSCONFIG_BANK_BIT_3 \ 49 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) 50 /* 0x80010102 */ 51 #define CONFIG_SYS_DDR_TIMING_3 0 52 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ 53 | (0 << TIMING_CFG0_WRT_SHIFT) \ 54 | (0 << TIMING_CFG0_RRT_SHIFT) \ 55 | (0 << TIMING_CFG0_WWT_SHIFT) \ 56 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ 57 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ 58 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ 59 | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) 60 /* 0x00260802 */ 61 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ 62 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \ 63 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ 64 | (7 << TIMING_CFG1_CASLAT_SHIFT) \ 65 | (9 << TIMING_CFG1_REFREC_SHIFT) \ 66 | (2 << TIMING_CFG1_WRREC_SHIFT) \ 67 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ 68 | (2 << TIMING_CFG1_WRTORD_SHIFT)) 69 /* 0x26279222 */ 70 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ 71 | (4 << TIMING_CFG2_CPO_SHIFT) \ 72 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ 73 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ 74 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ 75 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ 76 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) 77 /* 0x021848c5 */ 78 #define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \ 79 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) 80 /* 0x08240100 */ 81 #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ 82 | SDRAM_CFG_SDRAM_TYPE_DDR2 \ 83 | SDRAM_CFG_DBW_16) 84 /* 0x43100000 */ 85 86 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ 87 #define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \ 88 | (0x0242 << SDRAM_MODE_SD_SHIFT)) 89 /* ODT 150ohm CL=4, AL=0 on SDRAM */ 90 #define CONFIG_SYS_DDR_MODE2 0x00000000 91 92 /* 93 * Memory test 94 */ 95 96 /* 97 * The reserved memory 98 */ 99 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 100 101 #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ 102 #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ 103 104 /* 105 * Initial RAM Base Address Setup 106 */ 107 #define CONFIG_SYS_INIT_RAM_LOCK 1 108 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ 109 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ 110 #define CONFIG_SYS_GBL_DATA_OFFSET \ 111 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 112 113 /* 114 * FLASH on the Local Bus 115 */ 116 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 117 #define CONFIG_FLASH_CFI_LEGACY 118 #define CONFIG_SYS_FLASH_LEGACY_512Kx16 119 120 #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ 121 #define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is up to 8M */ 122 123 124 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 125 #define CONFIG_SYS_MAX_FLASH_SECT 135 126 127 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 128 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 129 130 #define CONFIG_SYS_FPGA_DONE(k) 0x0010 131 132 #define CONFIG_SYS_FPGA_COUNT 1 133 134 #define CONFIG_SYS_MCLINK_MAX 3 135 136 #define CONFIG_SYS_FPGA_PTR \ 137 { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL } 138 139 #define CONFIG_SYS_FPGA_NO_RFL_HI 140 141 /* 142 * Serial Port 143 */ 144 #define CONFIG_SYS_NS16550_SERIAL 145 #define CONFIG_SYS_NS16550_REG_SIZE 1 146 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 147 148 #define CONFIG_SYS_BAUDRATE_TABLE \ 149 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 150 151 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) 152 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) 153 154 /* Pass open firmware flat tree */ 155 156 /* I2C */ 157 #define CONFIG_SYS_I2C 158 #define CONFIG_SYS_I2C_FSL 159 #define CONFIG_SYS_FSL_I2C_SPEED 400000 160 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 161 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 162 163 #define CONFIG_PCA953X /* NXP PCA9554 */ 164 #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x24, 16}, {0x25, 16}, {0x26, 16}, \ 165 {0x3c, 8}, {0x3d, 8}, {0x3e, 8} } 166 167 #define CONFIG_PCA9698 /* NXP PCA9698 */ 168 169 #define CONFIG_SYS_I2C_IHS 170 #define CONFIG_SYS_I2C_IHS_CH0 171 #define CONFIG_SYS_I2C_IHS_SPEED_0 50000 172 #define CONFIG_SYS_I2C_IHS_SLAVE_0 0x7F 173 #define CONFIG_SYS_I2C_IHS_CH1 174 #define CONFIG_SYS_I2C_IHS_SPEED_1 50000 175 #define CONFIG_SYS_I2C_IHS_SLAVE_1 0x7F 176 #define CONFIG_SYS_I2C_IHS_CH2 177 #define CONFIG_SYS_I2C_IHS_SPEED_2 50000 178 #define CONFIG_SYS_I2C_IHS_SLAVE_2 0x7F 179 #define CONFIG_SYS_I2C_IHS_CH3 180 #define CONFIG_SYS_I2C_IHS_SPEED_3 50000 181 #define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F 182 183 #ifdef CONFIG_STRIDER_CON_DP 184 #define CONFIG_SYS_I2C_IHS_DUAL 185 #define CONFIG_SYS_I2C_IHS_CH0_1 186 #define CONFIG_SYS_I2C_IHS_SPEED_0_1 50000 187 #define CONFIG_SYS_I2C_IHS_SLAVE_0_1 0x7F 188 #define CONFIG_SYS_I2C_IHS_CH1_1 189 #define CONFIG_SYS_I2C_IHS_SPEED_1_1 50000 190 #define CONFIG_SYS_I2C_IHS_SLAVE_1_1 0x7F 191 #define CONFIG_SYS_I2C_IHS_CH2_1 192 #define CONFIG_SYS_I2C_IHS_SPEED_2_1 50000 193 #define CONFIG_SYS_I2C_IHS_SLAVE_2_1 0x7F 194 #define CONFIG_SYS_I2C_IHS_CH3_1 195 #define CONFIG_SYS_I2C_IHS_SPEED_3_1 50000 196 #define CONFIG_SYS_I2C_IHS_SLAVE_3_1 0x7F 197 #endif 198 199 /* 200 * Software (bit-bang) I2C driver configuration 201 */ 202 #define CONFIG_SYS_I2C_SOFT 203 #define CONFIG_SOFT_I2C_READ_REPEATED_START 204 #define CONFIG_SYS_I2C_SOFT_SPEED 50000 205 #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F 206 #define I2C_SOFT_DECLARATIONS2 207 #define CONFIG_SYS_I2C_SOFT_SPEED_2 50000 208 #define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x7F 209 #define I2C_SOFT_DECLARATIONS3 210 #define CONFIG_SYS_I2C_SOFT_SPEED_3 50000 211 #define CONFIG_SYS_I2C_SOFT_SLAVE_3 0x7F 212 #define I2C_SOFT_DECLARATIONS4 213 #define CONFIG_SYS_I2C_SOFT_SPEED_4 50000 214 #define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F 215 #if defined(CONFIG_STRIDER_CON) || defined(CONFIG_STRIDER_CON_DP) 216 #define I2C_SOFT_DECLARATIONS5 217 #define CONFIG_SYS_I2C_SOFT_SPEED_5 50000 218 #define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F 219 #define I2C_SOFT_DECLARATIONS6 220 #define CONFIG_SYS_I2C_SOFT_SPEED_6 50000 221 #define CONFIG_SYS_I2C_SOFT_SLAVE_6 0x7F 222 #define I2C_SOFT_DECLARATIONS7 223 #define CONFIG_SYS_I2C_SOFT_SPEED_7 50000 224 #define CONFIG_SYS_I2C_SOFT_SLAVE_7 0x7F 225 #define I2C_SOFT_DECLARATIONS8 226 #define CONFIG_SYS_I2C_SOFT_SPEED_8 50000 227 #define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F 228 #endif 229 #ifdef CONFIG_STRIDER_CON_DP 230 #define I2C_SOFT_DECLARATIONS9 231 #define CONFIG_SYS_I2C_SOFT_SPEED_9 50000 232 #define CONFIG_SYS_I2C_SOFT_SLAVE_9 0x7F 233 #define I2C_SOFT_DECLARATIONS10 234 #define CONFIG_SYS_I2C_SOFT_SPEED_10 50000 235 #define CONFIG_SYS_I2C_SOFT_SLAVE_10 0x7F 236 #define I2C_SOFT_DECLARATIONS11 237 #define CONFIG_SYS_I2C_SOFT_SPEED_11 50000 238 #define CONFIG_SYS_I2C_SOFT_SLAVE_11 0x7F 239 #define I2C_SOFT_DECLARATIONS12 240 #define CONFIG_SYS_I2C_SOFT_SPEED_12 50000 241 #define CONFIG_SYS_I2C_SOFT_SLAVE_12 0x7F 242 #endif 243 244 #ifdef CONFIG_STRIDER_CON 245 #define CONFIG_SYS_ICS8N3QV01_I2C {5, 6, 7, 8} 246 #define CONFIG_SYS_CH7301_I2C {5, 6, 7, 8} 247 #define CONFIG_SYS_ADV7611_I2C {5, 6, 7, 8} 248 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} 249 #define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \ 250 {12, 0x4c} } 251 #elif defined(CONFIG_STRIDER_CON_DP) 252 #define CONFIG_SYS_ICS8N3QV01_I2C {13, 14, 15, 16, 17, 18, 19, 20} 253 #define CONFIG_SYS_CH7301_I2C {1, 3, 5, 7} 254 #define CONFIG_SYS_ADV7611_I2C {1, 3, 5, 7} 255 #define CONFIG_SYS_DP501_I2C {1, 3, 5, 7, 2, 4, 6, 8} 256 #define CONFIG_STRIDER_FANS { {10, 0x4c}, {11, 0x4c}, \ 257 {12, 0x4c} } 258 #elif defined(CONFIG_STRIDER_CPU_DP) 259 #define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4} 260 #define CONFIG_SYS_ADV7611_I2C {1, 2, 3, 4} 261 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} 262 #define CONFIG_STRIDER_FANS { {6, 0x4c}, {7, 0x4c}, \ 263 {8, 0x4c} } 264 #else 265 #define CONFIG_SYS_CH7301_I2C {1, 2, 3, 4} 266 #define CONFIG_SYS_ADV7611_I2C {1, 2, 3, 4} 267 #define CONFIG_SYS_DP501_I2C {1, 2, 3, 4} 268 #define CONFIG_STRIDER_FANS { {2, 0x18}, {3, 0x18}, \ 269 {4, 0x18} } 270 #endif 271 272 #ifndef __ASSEMBLY__ 273 void fpga_gpio_set(unsigned int bus, int pin); 274 void fpga_gpio_clear(unsigned int bus, int pin); 275 int fpga_gpio_get(unsigned int bus, int pin); 276 void fpga_control_set(unsigned int bus, int pin); 277 void fpga_control_clear(unsigned int bus, int pin); 278 #endif 279 280 #ifdef CONFIG_STRIDER_CON 281 #define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0200 : 0x0040) 282 #define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0100 : 0x0020) 283 #define I2C_FPGA_IDX ((I2C_ADAP_HWNR > 3) ? \ 284 (I2C_ADAP_HWNR - 4) : I2C_ADAP_HWNR) 285 #elif defined(CONFIG_STRIDER_CON_DP) 286 #define I2C_SDA_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200) 287 #define I2C_SCL_GPIO ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100) 288 #define I2C_FPGA_IDX (I2C_ADAP_HWNR % 4) 289 #else 290 #define I2C_SDA_GPIO 0x0040 291 #define I2C_SCL_GPIO 0x0020 292 #define I2C_FPGA_IDX I2C_ADAP_HWNR 293 #endif 294 295 #ifdef CONFIG_STRIDER_CON_DP 296 #define I2C_ACTIVE \ 297 do { \ 298 if (I2C_ADAP_HWNR > 7) \ 299 fpga_control_set(I2C_FPGA_IDX, 0x0004); \ 300 else \ 301 fpga_control_clear(I2C_FPGA_IDX, 0x0004); \ 302 } while (0) 303 #else 304 #define I2C_ACTIVE { } 305 #endif 306 307 #define I2C_TRISTATE { } 308 #define I2C_READ \ 309 (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0) 310 #define I2C_SDA(bit) \ 311 do { \ 312 if (bit) \ 313 fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \ 314 else \ 315 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \ 316 } while (0) 317 #define I2C_SCL(bit) \ 318 do { \ 319 if (bit) \ 320 fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \ 321 else \ 322 fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \ 323 } while (0) 324 #define I2C_DELAY udelay(25) /* 1/4 I2C clock duration */ 325 326 /* 327 * Software (bit-bang) MII driver configuration 328 */ 329 #define CONFIG_BITBANGMII_MULTI 330 331 /* 332 * OSD Setup 333 */ 334 #define CONFIG_SYS_OSD_SCREENS 1 335 #define CONFIG_SYS_DP501_DIFFERENTIAL 336 #define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */ 337 338 #ifdef CONFIG_STRIDER_CON_DP 339 #define CONFIG_SYS_OSD_DH 340 #endif 341 342 /* 343 * General PCI 344 * Addresses are mapped 1-1. 345 */ 346 #define CONFIG_SYS_PCIE1_BASE 0xA0000000 347 #define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 348 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 349 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 350 #define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 351 #define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 352 #define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 353 #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 354 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 355 356 /* enable PCIE clock */ 357 #define CONFIG_SYS_SCCR_PCIEXP1CM 1 358 359 #define CONFIG_PCI_INDIRECT_BRIDGE 360 #define CONFIG_PCIE 361 362 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ 363 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1 364 365 /* 366 * TSEC 367 */ 368 #define CONFIG_SYS_TSEC1_OFFSET 0x24000 369 #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) 370 371 /* 372 * TSEC ethernet configuration 373 */ 374 #define CONFIG_TSEC1 375 #define CONFIG_TSEC1_NAME "eTSEC0" 376 #define TSEC1_PHY_ADDR 1 377 #define TSEC1_PHYIDX 0 378 #define TSEC1_FLAGS 0 379 380 /* Options are: eTSEC[0-1] */ 381 #define CONFIG_ETHPRIME "eTSEC0" 382 383 /* 384 * Environment 385 */ 386 387 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 388 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 389 390 /* 391 * Miscellaneous configurable options 392 */ 393 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 394 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 395 396 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 397 398 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 399 400 /* 401 * For booting Linux, the board info and command line data 402 * have to be in the first 256 MB of memory, since this is 403 * the maximum mapped by the Linux kernel during initialization. 404 */ 405 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ 406 407 /* 408 * Environment Configuration 409 */ 410 411 #define CONFIG_ENV_OVERWRITE 412 413 #if defined(CONFIG_TSEC_ENET) 414 #define CONFIG_HAS_ETH0 415 #endif 416 417 #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ 418 419 420 #define CONFIG_HOSTNAME "hrcon" 421 #define CONFIG_ROOTPATH "/opt/nfsroot" 422 #define CONFIG_BOOTFILE "uImage" 423 424 #define CONFIG_EXTRA_ENV_SETTINGS \ 425 "netdev=eth0\0" \ 426 "consoledev=ttyS1\0" \ 427 "u-boot=u-boot.bin\0" \ 428 "kernel_addr=1000000\0" \ 429 "fdt_addr=C00000\0" \ 430 "fdtfile=hrcon.dtb\0" \ 431 "load=tftp ${loadaddr} ${u-boot}\0" \ 432 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \ 433 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\ 434 " +${filesize};cp.b ${fileaddr} " \ 435 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ 436 "upd=run load update\0" \ 437 438 #define CONFIG_NFSBOOTCOMMAND \ 439 "setenv bootargs root=/dev/nfs rw " \ 440 "nfsroot=$serverip:$rootpath " \ 441 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 442 "console=$consoledev,$baudrate $othbootargs;" \ 443 "tftp ${kernel_addr} $bootfile;" \ 444 "tftp ${fdt_addr} $fdtfile;" \ 445 "bootm ${kernel_addr} - ${fdt_addr}" 446 447 #define CONFIG_MMCBOOTCOMMAND \ 448 "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \ 449 "console=$consoledev,$baudrate $othbootargs;" \ 450 "ext2load mmc 0:2 ${kernel_addr} $bootfile;" \ 451 "ext2load mmc 0:2 ${fdt_addr} $fdtfile;" \ 452 "bootm ${kernel_addr} - ${fdt_addr}" 453 454 #define CONFIG_BOOTCOMMAND CONFIG_MMCBOOTCOMMAND 455 456 #endif /* __CONFIG_H */ 457