1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3 * FSL SD/MMC Defines
4 *-------------------------------------------------------------------
5 *
6 * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc
7 * Copyright 2020 NXP
8 */
9
10 #ifndef __FSL_ESDHC_H__
11 #define __FSL_ESDHC_H__
12
13 #include <linux/errno.h>
14 #include <asm/byteorder.h>
15
16 /* needed for the mmc_cfg definition */
17 #include <mmc.h>
18
19 #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
20 #include "../board/freescale/common/qixis.h"
21 #endif
22
23 /* FSL eSDHC-specific constants */
24 #define SYSCTL 0x0002e02c
25 #define SYSCTL_INITA 0x08000000
26 #define SYSCTL_TIMEOUT_MASK 0x000f0000
27 #define SYSCTL_CLOCK_MASK 0x0000fff0
28 #define SYSCTL_CKEN 0x00000008
29 #define SYSCTL_PEREN 0x00000004
30 #define SYSCTL_HCKEN 0x00000002
31 #define SYSCTL_IPGEN 0x00000001
32 #define SYSCTL_RSTA 0x01000000
33 #define SYSCTL_RSTC 0x02000000
34 #define SYSCTL_RSTD 0x04000000
35
36 #define IRQSTAT 0x0002e030
37 #define IRQSTAT_DMAE (0x10000000)
38 #define IRQSTAT_AC12E (0x01000000)
39 #define IRQSTAT_DEBE (0x00400000)
40 #define IRQSTAT_DCE (0x00200000)
41 #define IRQSTAT_DTOE (0x00100000)
42 #define IRQSTAT_CIE (0x00080000)
43 #define IRQSTAT_CEBE (0x00040000)
44 #define IRQSTAT_CCE (0x00020000)
45 #define IRQSTAT_CTOE (0x00010000)
46 #define IRQSTAT_CINT (0x00000100)
47 #define IRQSTAT_CRM (0x00000080)
48 #define IRQSTAT_CINS (0x00000040)
49 #define IRQSTAT_BRR (0x00000020)
50 #define IRQSTAT_BWR (0x00000010)
51 #define IRQSTAT_DINT (0x00000008)
52 #define IRQSTAT_BGE (0x00000004)
53 #define IRQSTAT_TC (0x00000002)
54 #define IRQSTAT_CC (0x00000001)
55
56 #define CMD_ERR (IRQSTAT_CIE | IRQSTAT_CEBE | IRQSTAT_CCE)
57 #define DATA_ERR (IRQSTAT_DEBE | IRQSTAT_DCE | IRQSTAT_DTOE | \
58 IRQSTAT_DMAE)
59 #define DATA_COMPLETE (IRQSTAT_TC | IRQSTAT_DINT)
60
61 #define IRQSTATEN 0x0002e034
62 #define IRQSTATEN_DMAE (0x10000000)
63 #define IRQSTATEN_AC12E (0x01000000)
64 #define IRQSTATEN_DEBE (0x00400000)
65 #define IRQSTATEN_DCE (0x00200000)
66 #define IRQSTATEN_DTOE (0x00100000)
67 #define IRQSTATEN_CIE (0x00080000)
68 #define IRQSTATEN_CEBE (0x00040000)
69 #define IRQSTATEN_CCE (0x00020000)
70 #define IRQSTATEN_CTOE (0x00010000)
71 #define IRQSTATEN_CINT (0x00000100)
72 #define IRQSTATEN_CRM (0x00000080)
73 #define IRQSTATEN_CINS (0x00000040)
74 #define IRQSTATEN_BRR (0x00000020)
75 #define IRQSTATEN_BWR (0x00000010)
76 #define IRQSTATEN_DINT (0x00000008)
77 #define IRQSTATEN_BGE (0x00000004)
78 #define IRQSTATEN_TC (0x00000002)
79 #define IRQSTATEN_CC (0x00000001)
80
81 #define ESDHCCTL 0x0002e40c
82 #define ESDHCCTL_PCS (0x00080000)
83
84 #define PRSSTAT 0x0002e024
85 #define PRSSTAT_DAT0 (0x01000000)
86 #define PRSSTAT_CLSL (0x00800000)
87 #define PRSSTAT_WPSPL (0x00080000)
88 #define PRSSTAT_CDPL (0x00040000)
89 #define PRSSTAT_CINS (0x00010000)
90 #define PRSSTAT_BREN (0x00000800)
91 #define PRSSTAT_BWEN (0x00000400)
92 #define PRSSTAT_SDSTB (0X00000008)
93 #define PRSSTAT_DLA (0x00000004)
94 #define PRSSTAT_CICHB (0x00000002)
95 #define PRSSTAT_CIDHB (0x00000001)
96
97 #define PROCTL 0x0002e028
98 #define PROCTL_INIT 0x00000020
99 #define PROCTL_DTW_4 0x00000002
100 #define PROCTL_DTW_8 0x00000004
101 #define PROCTL_D3CD 0x00000008
102 #define PROCTL_VOLT_SEL 0x00000400
103
104 #define CMDARG 0x0002e008
105
106 #define XFERTYP 0x0002e00c
107 #define XFERTYP_CMD(x) ((x & 0x3f) << 24)
108 #define XFERTYP_CMDTYP_NORMAL 0x0
109 #define XFERTYP_CMDTYP_SUSPEND 0x00400000
110 #define XFERTYP_CMDTYP_RESUME 0x00800000
111 #define XFERTYP_CMDTYP_ABORT 0x00c00000
112 #define XFERTYP_DPSEL 0x00200000
113 #define XFERTYP_CICEN 0x00100000
114 #define XFERTYP_CCCEN 0x00080000
115 #define XFERTYP_RSPTYP_NONE 0
116 #define XFERTYP_RSPTYP_136 0x00010000
117 #define XFERTYP_RSPTYP_48 0x00020000
118 #define XFERTYP_RSPTYP_48_BUSY 0x00030000
119 #define XFERTYP_MSBSEL 0x00000020
120 #define XFERTYP_DTDSEL 0x00000010
121 #define XFERTYP_DDREN 0x00000008
122 #define XFERTYP_AC12EN 0x00000004
123 #define XFERTYP_BCEN 0x00000002
124 #define XFERTYP_DMAEN 0x00000001
125
126 #define CINS_TIMEOUT 1000
127 #define PIO_TIMEOUT 500
128
129 #define DSADDR 0x2e004
130
131 #define CMDRSP0 0x2e010
132 #define CMDRSP1 0x2e014
133 #define CMDRSP2 0x2e018
134 #define CMDRSP3 0x2e01c
135
136 #define DATPORT 0x2e020
137
138 #define WML 0x2e044
139 #define WML_WRITE 0x00010000
140 #ifdef CONFIG_FSL_SDHC_V2_3
141 #define WML_RD_WML_MAX 0x80
142 #define WML_WR_WML_MAX 0x80
143 #define WML_RD_WML_MAX_VAL 0x0
144 #define WML_WR_WML_MAX_VAL 0x0
145 #define WML_RD_WML_MASK 0x7f
146 #define WML_WR_WML_MASK 0x7f0000
147 #else
148 #define WML_RD_WML_MAX 0x10
149 #define WML_WR_WML_MAX 0x80
150 #define WML_RD_WML_MAX_VAL 0x10
151 #define WML_WR_WML_MAX_VAL 0x80
152 #define WML_RD_WML_MASK 0xff
153 #define WML_WR_WML_MASK 0xff0000
154 #endif
155
156 #define BLKATTR 0x2e004
157 #define BLKATTR_CNT(x) ((x & 0xffff) << 16)
158 #define BLKATTR_SIZE(x) (x & 0x1fff)
159 #define MAX_BLK_CNT 0x7fff /* so malloc will have enough room with 32M */
160
161 /* Host controller capabilities register */
162 #define HOSTCAPBLT_VS18 0x04000000
163 #define HOSTCAPBLT_VS30 0x02000000
164 #define HOSTCAPBLT_VS33 0x01000000
165 #define HOSTCAPBLT_SRS 0x00800000
166 #define HOSTCAPBLT_DMAS 0x00400000
167 #define HOSTCAPBLT_HSS 0x00200000
168
169 struct fsl_esdhc_cfg {
170 phys_addr_t esdhc_base;
171 u32 sdhc_clk;
172 u8 max_bus_width;
173 int vs18_enable; /* Use 1.8V if set to 1 */
174 struct mmc_config cfg;
175 };
176
177 /* Select the correct accessors depending on endianess */
178 #if defined CONFIG_SYS_FSL_ESDHC_LE
179 #define esdhc_read32 in_le32
180 #define esdhc_write32 out_le32
181 #define esdhc_clrsetbits32 clrsetbits_le32
182 #define esdhc_clrbits32 clrbits_le32
183 #define esdhc_setbits32 setbits_le32
184 #elif defined(CONFIG_SYS_FSL_ESDHC_BE)
185 #define esdhc_read32 in_be32
186 #define esdhc_write32 out_be32
187 #define esdhc_clrsetbits32 clrsetbits_be32
188 #define esdhc_clrbits32 clrbits_be32
189 #define esdhc_setbits32 setbits_be32
190 #elif __BYTE_ORDER == __LITTLE_ENDIAN
191 #define esdhc_read32 in_le32
192 #define esdhc_write32 out_le32
193 #define esdhc_clrsetbits32 clrsetbits_le32
194 #define esdhc_clrbits32 clrbits_le32
195 #define esdhc_setbits32 setbits_le32
196 #elif __BYTE_ORDER == __BIG_ENDIAN
197 #define esdhc_read32 in_be32
198 #define esdhc_write32 out_be32
199 #define esdhc_clrsetbits32 clrsetbits_be32
200 #define esdhc_clrbits32 clrbits_be32
201 #define esdhc_setbits32 setbits_be32
202 #else
203 #error "Endianess is not defined: please fix to continue"
204 #endif
205
206 #ifdef CONFIG_FSL_ESDHC
207 int fsl_esdhc_mmc_init(bd_t *bis);
208 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg);
209 void fdt_fixup_esdhc(void *blob, bd_t *bd);
210 #ifdef MMC_SUPPORTS_TUNING
fsl_esdhc_execute_tuning(struct udevice * dev,uint32_t opcode)211 static inline int fsl_esdhc_execute_tuning(struct udevice *dev,
212 uint32_t opcode) {return 0; }
213 #endif
214 #else
fsl_esdhc_mmc_init(bd_t * bis)215 static inline int fsl_esdhc_mmc_init(bd_t *bis) { return -ENOSYS; }
fdt_fixup_esdhc(void * blob,bd_t * bd)216 static inline void fdt_fixup_esdhc(void *blob, bd_t *bd) {}
217 #endif /* CONFIG_FSL_ESDHC */
218 void __noreturn mmc_boot(void);
219 void mmc_spl_load_image(uint32_t offs, unsigned int size, void *vdst);
220
221 #endif /* __FSL_ESDHC_H__ */
222