1 /* 2 * 3 * HW regs data for OMAP5 Soc 4 * 5 * (C) Copyright 2013 6 * Texas Instruments, <www.ti.com> 7 * 8 * Sricharan R <r.sricharan@ti.com> 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #include <asm/omap_common.h> 14 15 struct prcm_regs const omap5_es1_prcm = { 16 /* cm1.ckgen */ 17 .cm_clksel_core = 0x4a004100, 18 .cm_clksel_abe = 0x4a004108, 19 .cm_dll_ctrl = 0x4a004110, 20 .cm_clkmode_dpll_core = 0x4a004120, 21 .cm_idlest_dpll_core = 0x4a004124, 22 .cm_autoidle_dpll_core = 0x4a004128, 23 .cm_clksel_dpll_core = 0x4a00412c, 24 .cm_div_m2_dpll_core = 0x4a004130, 25 .cm_div_m3_dpll_core = 0x4a004134, 26 .cm_div_h11_dpll_core = 0x4a004138, 27 .cm_div_h12_dpll_core = 0x4a00413c, 28 .cm_div_h13_dpll_core = 0x4a004140, 29 .cm_div_h14_dpll_core = 0x4a004144, 30 .cm_ssc_deltamstep_dpll_core = 0x4a004148, 31 .cm_ssc_modfreqdiv_dpll_core = 0x4a00414c, 32 .cm_emu_override_dpll_core = 0x4a004150, 33 .cm_div_h22_dpllcore = 0x4a004154, 34 .cm_div_h23_dpll_core = 0x4a004158, 35 .cm_clkmode_dpll_mpu = 0x4a004160, 36 .cm_idlest_dpll_mpu = 0x4a004164, 37 .cm_autoidle_dpll_mpu = 0x4a004168, 38 .cm_clksel_dpll_mpu = 0x4a00416c, 39 .cm_div_m2_dpll_mpu = 0x4a004170, 40 .cm_ssc_deltamstep_dpll_mpu = 0x4a004188, 41 .cm_ssc_modfreqdiv_dpll_mpu = 0x4a00418c, 42 .cm_bypclk_dpll_mpu = 0x4a00419c, 43 .cm_clkmode_dpll_iva = 0x4a0041a0, 44 .cm_idlest_dpll_iva = 0x4a0041a4, 45 .cm_autoidle_dpll_iva = 0x4a0041a8, 46 .cm_clksel_dpll_iva = 0x4a0041ac, 47 .cm_div_h11_dpll_iva = 0x4a0041b8, 48 .cm_div_h12_dpll_iva = 0x4a0041bc, 49 .cm_ssc_deltamstep_dpll_iva = 0x4a0041c8, 50 .cm_ssc_modfreqdiv_dpll_iva = 0x4a0041cc, 51 .cm_bypclk_dpll_iva = 0x4a0041dc, 52 .cm_clkmode_dpll_abe = 0x4a0041e0, 53 .cm_idlest_dpll_abe = 0x4a0041e4, 54 .cm_autoidle_dpll_abe = 0x4a0041e8, 55 .cm_clksel_dpll_abe = 0x4a0041ec, 56 .cm_div_m2_dpll_abe = 0x4a0041f0, 57 .cm_div_m3_dpll_abe = 0x4a0041f4, 58 .cm_ssc_deltamstep_dpll_abe = 0x4a004208, 59 .cm_ssc_modfreqdiv_dpll_abe = 0x4a00420c, 60 .cm_clkmode_dpll_ddrphy = 0x4a004220, 61 .cm_idlest_dpll_ddrphy = 0x4a004224, 62 .cm_autoidle_dpll_ddrphy = 0x4a004228, 63 .cm_clksel_dpll_ddrphy = 0x4a00422c, 64 .cm_div_m2_dpll_ddrphy = 0x4a004230, 65 .cm_div_h11_dpll_ddrphy = 0x4a004238, 66 .cm_div_h12_dpll_ddrphy = 0x4a00423c, 67 .cm_div_h13_dpll_ddrphy = 0x4a004240, 68 .cm_ssc_deltamstep_dpll_ddrphy = 0x4a004248, 69 .cm_shadow_freq_config1 = 0x4a004260, 70 .cm_mpu_mpu_clkctrl = 0x4a004320, 71 72 /* cm1.dsp */ 73 .cm_dsp_clkstctrl = 0x4a004400, 74 .cm_dsp_dsp_clkctrl = 0x4a004420, 75 76 /* cm1.abe */ 77 .cm1_abe_clkstctrl = 0x4a004500, 78 .cm1_abe_l4abe_clkctrl = 0x4a004520, 79 .cm1_abe_aess_clkctrl = 0x4a004528, 80 .cm1_abe_pdm_clkctrl = 0x4a004530, 81 .cm1_abe_dmic_clkctrl = 0x4a004538, 82 .cm1_abe_mcasp_clkctrl = 0x4a004540, 83 .cm1_abe_mcbsp1_clkctrl = 0x4a004548, 84 .cm1_abe_mcbsp2_clkctrl = 0x4a004550, 85 .cm1_abe_mcbsp3_clkctrl = 0x4a004558, 86 .cm1_abe_slimbus_clkctrl = 0x4a004560, 87 .cm1_abe_timer5_clkctrl = 0x4a004568, 88 .cm1_abe_timer6_clkctrl = 0x4a004570, 89 .cm1_abe_timer7_clkctrl = 0x4a004578, 90 .cm1_abe_timer8_clkctrl = 0x4a004580, 91 .cm1_abe_wdt3_clkctrl = 0x4a004588, 92 93 /* cm2.ckgen */ 94 .cm_clksel_mpu_m3_iss_root = 0x4a008100, 95 .cm_clksel_usb_60mhz = 0x4a008104, 96 .cm_scale_fclk = 0x4a008108, 97 .cm_core_dvfs_perf1 = 0x4a008110, 98 .cm_core_dvfs_perf2 = 0x4a008114, 99 .cm_core_dvfs_perf3 = 0x4a008118, 100 .cm_core_dvfs_perf4 = 0x4a00811c, 101 .cm_core_dvfs_current = 0x4a008124, 102 .cm_iva_dvfs_perf_tesla = 0x4a008128, 103 .cm_iva_dvfs_perf_ivahd = 0x4a00812c, 104 .cm_iva_dvfs_perf_abe = 0x4a008130, 105 .cm_iva_dvfs_current = 0x4a008138, 106 .cm_clkmode_dpll_per = 0x4a008140, 107 .cm_idlest_dpll_per = 0x4a008144, 108 .cm_autoidle_dpll_per = 0x4a008148, 109 .cm_clksel_dpll_per = 0x4a00814c, 110 .cm_div_m2_dpll_per = 0x4a008150, 111 .cm_div_m3_dpll_per = 0x4a008154, 112 .cm_div_h11_dpll_per = 0x4a008158, 113 .cm_div_h12_dpll_per = 0x4a00815c, 114 .cm_div_h14_dpll_per = 0x4a008164, 115 .cm_ssc_deltamstep_dpll_per = 0x4a008168, 116 .cm_ssc_modfreqdiv_dpll_per = 0x4a00816c, 117 .cm_emu_override_dpll_per = 0x4a008170, 118 .cm_clkmode_dpll_usb = 0x4a008180, 119 .cm_idlest_dpll_usb = 0x4a008184, 120 .cm_autoidle_dpll_usb = 0x4a008188, 121 .cm_clksel_dpll_usb = 0x4a00818c, 122 .cm_div_m2_dpll_usb = 0x4a008190, 123 .cm_ssc_deltamstep_dpll_usb = 0x4a0081a8, 124 .cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac, 125 .cm_clkdcoldo_dpll_usb = 0x4a0081b4, 126 .cm_clkmode_dpll_unipro = 0x4a0081c0, 127 .cm_idlest_dpll_unipro = 0x4a0081c4, 128 .cm_autoidle_dpll_unipro = 0x4a0081c8, 129 .cm_clksel_dpll_unipro = 0x4a0081cc, 130 .cm_div_m2_dpll_unipro = 0x4a0081d0, 131 .cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8, 132 .cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec, 133 134 /* cm2.core */ 135 .cm_coreaon_bandgap_clkctrl = 0x4a008648, 136 .cm_coreaon_io_srcomp_clkctrl = 0x4a008650, 137 .cm_l3_1_clkstctrl = 0x4a008700, 138 .cm_l3_1_dynamicdep = 0x4a008708, 139 .cm_l3_1_l3_1_clkctrl = 0x4a008720, 140 .cm_l3_2_clkstctrl = 0x4a008800, 141 .cm_l3_2_dynamicdep = 0x4a008808, 142 .cm_l3_2_l3_2_clkctrl = 0x4a008820, 143 .cm_l3_gpmc_clkctrl = 0x4a008828, 144 .cm_l3_2_ocmc_ram_clkctrl = 0x4a008830, 145 .cm_mpu_m3_clkstctrl = 0x4a008900, 146 .cm_mpu_m3_staticdep = 0x4a008904, 147 .cm_mpu_m3_dynamicdep = 0x4a008908, 148 .cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920, 149 .cm_sdma_clkstctrl = 0x4a008a00, 150 .cm_sdma_staticdep = 0x4a008a04, 151 .cm_sdma_dynamicdep = 0x4a008a08, 152 .cm_sdma_sdma_clkctrl = 0x4a008a20, 153 .cm_memif_clkstctrl = 0x4a008b00, 154 .cm_memif_dmm_clkctrl = 0x4a008b20, 155 .cm_memif_emif_fw_clkctrl = 0x4a008b28, 156 .cm_memif_emif_1_clkctrl = 0x4a008b30, 157 .cm_memif_emif_2_clkctrl = 0x4a008b38, 158 .cm_memif_dll_clkctrl = 0x4a008b40, 159 .cm_memif_emif_h1_clkctrl = 0x4a008b50, 160 .cm_memif_emif_h2_clkctrl = 0x4a008b58, 161 .cm_memif_dll_h_clkctrl = 0x4a008b60, 162 .cm_c2c_clkstctrl = 0x4a008c00, 163 .cm_c2c_staticdep = 0x4a008c04, 164 .cm_c2c_dynamicdep = 0x4a008c08, 165 .cm_c2c_sad2d_clkctrl = 0x4a008c20, 166 .cm_c2c_modem_icr_clkctrl = 0x4a008c28, 167 .cm_c2c_sad2d_fw_clkctrl = 0x4a008c30, 168 .cm_l4cfg_clkstctrl = 0x4a008d00, 169 .cm_l4cfg_dynamicdep = 0x4a008d08, 170 .cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20, 171 .cm_l4cfg_hw_sem_clkctrl = 0x4a008d28, 172 .cm_l4cfg_mailbox_clkctrl = 0x4a008d30, 173 .cm_l4cfg_sar_rom_clkctrl = 0x4a008d38, 174 .cm_l3instr_clkstctrl = 0x4a008e00, 175 .cm_l3instr_l3_3_clkctrl = 0x4a008e20, 176 .cm_l3instr_l3_instr_clkctrl = 0x4a008e28, 177 .cm_l3instr_intrconn_wp1_clkctrl = 0x4a008e40, 178 179 /* cm2.ivahd */ 180 .cm_ivahd_clkstctrl = 0x4a008f00, 181 .cm_ivahd_ivahd_clkctrl = 0x4a008f20, 182 .cm_ivahd_sl2_clkctrl = 0x4a008f28, 183 184 /* cm2.cam */ 185 .cm_cam_clkstctrl = 0x4a009000, 186 .cm_cam_iss_clkctrl = 0x4a009020, 187 .cm_cam_fdif_clkctrl = 0x4a009028, 188 189 /* cm2.dss */ 190 .cm_dss_clkstctrl = 0x4a009100, 191 .cm_dss_dss_clkctrl = 0x4a009120, 192 193 /* cm2.sgx */ 194 .cm_sgx_clkstctrl = 0x4a009200, 195 .cm_sgx_sgx_clkctrl = 0x4a009220, 196 197 /* cm2.l3init */ 198 .cm_l3init_clkstctrl = 0x4a009300, 199 .cm_l3init_hsmmc1_clkctrl = 0x4a009328, 200 .cm_l3init_hsmmc2_clkctrl = 0x4a009330, 201 .cm_l3init_hsi_clkctrl = 0x4a009338, 202 .cm_l3init_hsusbhost_clkctrl = 0x4a009358, 203 .cm_l3init_hsusbotg_clkctrl = 0x4a009360, 204 .cm_l3init_hsusbtll_clkctrl = 0x4a009368, 205 .cm_l3init_p1500_clkctrl = 0x4a009378, 206 .cm_l3init_sata_clkctrl = 0x4a009388, 207 .cm_l3init_fsusb_clkctrl = 0x4a0093d0, 208 .cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0, 209 .cm_l3init_ocp2scp3_clkctrl = 0x4a0093e8, 210 211 /* cm2.l4per */ 212 .cm_l4per_clkstctrl = 0x4a009400, 213 .cm_l4per_dynamicdep = 0x4a009408, 214 .cm_l4per_adc_clkctrl = 0x4a009420, 215 .cm_l4per_gptimer10_clkctrl = 0x4a009428, 216 .cm_l4per_gptimer11_clkctrl = 0x4a009430, 217 .cm_l4per_gptimer2_clkctrl = 0x4a009438, 218 .cm_l4per_gptimer3_clkctrl = 0x4a009440, 219 .cm_l4per_gptimer4_clkctrl = 0x4a009448, 220 .cm_l4per_gptimer9_clkctrl = 0x4a009450, 221 .cm_l4per_elm_clkctrl = 0x4a009458, 222 .cm_l4per_gpio2_clkctrl = 0x4a009460, 223 .cm_l4per_gpio3_clkctrl = 0x4a009468, 224 .cm_l4per_gpio4_clkctrl = 0x4a009470, 225 .cm_l4per_gpio5_clkctrl = 0x4a009478, 226 .cm_l4per_gpio6_clkctrl = 0x4a009480, 227 .cm_l4per_hdq1w_clkctrl = 0x4a009488, 228 .cm_l4per_hecc1_clkctrl = 0x4a009490, 229 .cm_l4per_hecc2_clkctrl = 0x4a009498, 230 .cm_l4per_i2c1_clkctrl = 0x4a0094a0, 231 .cm_l4per_i2c2_clkctrl = 0x4a0094a8, 232 .cm_l4per_i2c3_clkctrl = 0x4a0094b0, 233 .cm_l4per_i2c4_clkctrl = 0x4a0094b8, 234 .cm_l4per_l4per_clkctrl = 0x4a0094c0, 235 .cm_l4per_mcasp2_clkctrl = 0x4a0094d0, 236 .cm_l4per_mcasp3_clkctrl = 0x4a0094d8, 237 .cm_l4per_mgate_clkctrl = 0x4a0094e8, 238 .cm_l4per_mcspi1_clkctrl = 0x4a0094f0, 239 .cm_l4per_mcspi2_clkctrl = 0x4a0094f8, 240 .cm_l4per_mcspi3_clkctrl = 0x4a009500, 241 .cm_l4per_mcspi4_clkctrl = 0x4a009508, 242 .cm_l4per_gpio7_clkctrl = 0x4a009510, 243 .cm_l4per_gpio8_clkctrl = 0x4a009518, 244 .cm_l4per_mmcsd3_clkctrl = 0x4a009520, 245 .cm_l4per_mmcsd4_clkctrl = 0x4a009528, 246 .cm_l4per_msprohg_clkctrl = 0x4a009530, 247 .cm_l4per_slimbus2_clkctrl = 0x4a009538, 248 .cm_l4per_uart1_clkctrl = 0x4a009540, 249 .cm_l4per_uart2_clkctrl = 0x4a009548, 250 .cm_l4per_uart3_clkctrl = 0x4a009550, 251 .cm_l4per_uart4_clkctrl = 0x4a009558, 252 .cm_l4per_mmcsd5_clkctrl = 0x4a009560, 253 .cm_l4per_i2c5_clkctrl = 0x4a009568, 254 .cm_l4per_uart5_clkctrl = 0x4a009570, 255 .cm_l4per_uart6_clkctrl = 0x4a009578, 256 .cm_l4sec_clkstctrl = 0x4a009580, 257 .cm_l4sec_staticdep = 0x4a009584, 258 .cm_l4sec_dynamicdep = 0x4a009588, 259 .cm_l4sec_aes1_clkctrl = 0x4a0095a0, 260 .cm_l4sec_aes2_clkctrl = 0x4a0095a8, 261 .cm_l4sec_des3des_clkctrl = 0x4a0095b0, 262 .cm_l4sec_pkaeip29_clkctrl = 0x4a0095b8, 263 .cm_l4sec_rng_clkctrl = 0x4a0095c0, 264 .cm_l4sec_sha2md51_clkctrl = 0x4a0095c8, 265 .cm_l4sec_cryptodma_clkctrl = 0x4a0095d8, 266 267 /* l4 wkup regs */ 268 .cm_abe_pll_ref_clksel = 0x4ae0610c, 269 .cm_sys_clksel = 0x4ae06110, 270 .cm_wkup_clkstctrl = 0x4ae07800, 271 .cm_wkup_l4wkup_clkctrl = 0x4ae07820, 272 .cm_wkup_wdtimer1_clkctrl = 0x4ae07828, 273 .cm_wkup_wdtimer2_clkctrl = 0x4ae07830, 274 .cm_wkup_gpio1_clkctrl = 0x4ae07838, 275 .cm_wkup_gptimer1_clkctrl = 0x4ae07840, 276 .cm_wkup_gptimer12_clkctrl = 0x4ae07848, 277 .cm_wkup_synctimer_clkctrl = 0x4ae07850, 278 .cm_wkup_usim_clkctrl = 0x4ae07858, 279 .cm_wkup_sarram_clkctrl = 0x4ae07860, 280 .cm_wkup_keyboard_clkctrl = 0x4ae07878, 281 .cm_wkup_rtc_clkctrl = 0x4ae07880, 282 .cm_wkup_bandgap_clkctrl = 0x4ae07888, 283 .cm_wkupaon_scrm_clkctrl = 0x4ae07890, 284 .cm_wkupaon_io_srcomp_clkctrl = 0x4ae07898, 285 .prm_rstctrl = 0x4ae07b00, 286 .prm_rstst = 0x4ae07b04, 287 .prm_rsttime = 0x4ae07b08, 288 .prm_vc_val_bypass = 0x4ae07ba0, 289 .prm_vc_cfg_i2c_mode = 0x4ae07bb4, 290 .prm_vc_cfg_i2c_clk = 0x4ae07bb8, 291 292 /* SCRM stuff, used by some boards */ 293 .scrm_auxclk0 = 0x4ae0a310, 294 .scrm_auxclk1 = 0x4ae0a314, 295 }; 296 297 struct omap_sys_ctrl_regs const omap5_ctrl = { 298 .control_status = 0x4A002134, 299 .control_std_fuse_opp_vdd_mpu_2 = 0x4A0021B4, 300 .control_phy_power_usb = 0x4A002370, 301 .control_phy_power_sata = 0x4A002374, 302 .control_padconf_core_base = 0x4A002800, 303 .control_paconf_global = 0x4A002DA0, 304 .control_paconf_mode = 0x4A002DA4, 305 .control_smart1io_padconf_0 = 0x4A002DA8, 306 .control_smart1io_padconf_1 = 0x4A002DAC, 307 .control_smart1io_padconf_2 = 0x4A002DB0, 308 .control_smart2io_padconf_0 = 0x4A002DB4, 309 .control_smart2io_padconf_1 = 0x4A002DB8, 310 .control_smart2io_padconf_2 = 0x4A002DBC, 311 .control_smart3io_padconf_0 = 0x4A002DC0, 312 .control_smart3io_padconf_1 = 0x4A002DC4, 313 .control_pbias = 0x4A002E00, 314 .control_i2c_0 = 0x4A002E04, 315 .control_camera_rx = 0x4A002E08, 316 .control_hdmi_tx_phy = 0x4A002E0C, 317 .control_uniportm = 0x4A002E10, 318 .control_dsiphy = 0x4A002E14, 319 .control_mcbsplp = 0x4A002E18, 320 .control_usb2phycore = 0x4A002E1C, 321 .control_hdmi_1 = 0x4A002E20, 322 .control_hsi = 0x4A002E24, 323 .control_ddr3ch1_0 = 0x4A002E30, 324 .control_ddr3ch2_0 = 0x4A002E34, 325 .control_ddrch1_0 = 0x4A002E38, 326 .control_ddrch1_1 = 0x4A002E3C, 327 .control_ddrch2_0 = 0x4A002E40, 328 .control_ddrch2_1 = 0x4A002E44, 329 .control_lpddr2ch1_0 = 0x4A002E48, 330 .control_lpddr2ch1_1 = 0x4A002E4C, 331 .control_ddrio_0 = 0x4A002E50, 332 .control_ddrio_1 = 0x4A002E54, 333 .control_ddrio_2 = 0x4A002E58, 334 .control_hyst_1 = 0x4A002E5C, 335 .control_usbb_hsic_control = 0x4A002E60, 336 .control_c2c = 0x4A002E64, 337 .control_core_control_spare_rw = 0x4A002E68, 338 .control_core_control_spare_r = 0x4A002E6C, 339 .control_core_control_spare_r_c0 = 0x4A002E70, 340 .control_srcomp_north_side = 0x4A002E74, 341 .control_srcomp_south_side = 0x4A002E78, 342 .control_srcomp_east_side = 0x4A002E7C, 343 .control_srcomp_west_side = 0x4A002E80, 344 .control_srcomp_code_latch = 0x4A002E84, 345 .control_port_emif1_sdram_config = 0x4AE0C110, 346 .control_port_emif1_lpddr2_nvm_config = 0x4AE0C114, 347 .control_port_emif2_sdram_config = 0x4AE0C118, 348 .control_emif1_sdram_config_ext = 0x4AE0C144, 349 .control_emif2_sdram_config_ext = 0x4AE0C148, 350 .control_wkup_ldovbb_mpu_voltage_ctrl = 0x4AE0C318, 351 .control_padconf_wkup_base = 0x4AE0C800, 352 .control_smart1nopmio_padconf_0 = 0x4AE0CDA0, 353 .control_smart1nopmio_padconf_1 = 0x4AE0CDA4, 354 .control_padconf_mode = 0x4AE0CDA8, 355 .control_xtal_oscillator = 0x4AE0CDAC, 356 .control_i2c_2 = 0x4AE0CDB0, 357 .control_ckobuffer = 0x4AE0CDB4, 358 .control_wkup_control_spare_rw = 0x4AE0CDB8, 359 .control_wkup_control_spare_r = 0x4AE0CDBC, 360 .control_wkup_control_spare_r_c0 = 0x4AE0CDC0, 361 .control_srcomp_east_side_wkup = 0x4AE0CDC4, 362 .control_efuse_1 = 0x4AE0CDC8, 363 .control_efuse_2 = 0x4AE0CDCC, 364 .control_efuse_3 = 0x4AE0CDD0, 365 .control_efuse_4 = 0x4AE0CDD4, 366 .control_efuse_5 = 0x4AE0CDD8, 367 .control_efuse_6 = 0x4AE0CDDC, 368 .control_efuse_7 = 0x4AE0CDE0, 369 .control_efuse_8 = 0x4AE0CDE4, 370 .control_efuse_9 = 0x4AE0CDE8, 371 .control_efuse_10 = 0x4AE0CDEC, 372 .control_efuse_11 = 0x4AE0CDF0, 373 .control_efuse_12 = 0x4AE0CDF4, 374 .control_efuse_13 = 0x4AE0CDF8, 375 }; 376 377 struct omap_sys_ctrl_regs const dra7xx_ctrl = { 378 .control_status = 0x4A002134, 379 .control_phy_power_usb = 0x4A002370, 380 .control_phy_power_sata = 0x4A002374, 381 .ctrl_core_sma_sw_0 = 0x4A0023FC, 382 .control_core_mac_id_0_lo = 0x4A002514, 383 .control_core_mac_id_0_hi = 0x4A002518, 384 .control_core_mac_id_1_lo = 0x4A00251C, 385 .control_core_mac_id_1_hi = 0x4A002520, 386 .control_core_mmr_lock1 = 0x4A002540, 387 .control_core_mmr_lock2 = 0x4A002544, 388 .control_core_mmr_lock3 = 0x4A002548, 389 .control_core_mmr_lock4 = 0x4A00254C, 390 .control_core_mmr_lock5 = 0x4A002550, 391 .control_core_control_io1 = 0x4A002554, 392 .control_core_control_io2 = 0x4A002558, 393 .control_paconf_global = 0x4A002DA0, 394 .control_paconf_mode = 0x4A002DA4, 395 .control_smart1io_padconf_0 = 0x4A002DA8, 396 .control_smart1io_padconf_1 = 0x4A002DAC, 397 .control_smart1io_padconf_2 = 0x4A002DB0, 398 .control_smart2io_padconf_0 = 0x4A002DB4, 399 .control_smart2io_padconf_1 = 0x4A002DB8, 400 .control_smart2io_padconf_2 = 0x4A002DBC, 401 .control_smart3io_padconf_0 = 0x4A002DC0, 402 .control_smart3io_padconf_1 = 0x4A002DC4, 403 .control_pbias = 0x4A002E00, 404 .control_i2c_0 = 0x4A002E04, 405 .control_camera_rx = 0x4A002E08, 406 .control_hdmi_tx_phy = 0x4A002E0C, 407 .control_uniportm = 0x4A002E10, 408 .control_dsiphy = 0x4A002E14, 409 .control_mcbsplp = 0x4A002E18, 410 .control_usb2phycore = 0x4A002E1C, 411 .control_hdmi_1 = 0x4A002E20, 412 .control_hsi = 0x4A002E24, 413 .control_ddr3ch1_0 = 0x4A002E30, 414 .control_ddr3ch2_0 = 0x4A002E34, 415 .control_ddrch1_0 = 0x4A002E38, 416 .control_ddrch1_1 = 0x4A002E3C, 417 .control_ddrch2_0 = 0x4A002E40, 418 .control_ddrch2_1 = 0x4A002E44, 419 .control_lpddr2ch1_0 = 0x4A002E48, 420 .control_lpddr2ch1_1 = 0x4A002E4C, 421 .control_ddrio_0 = 0x4A002E50, 422 .control_ddrio_1 = 0x4A002E54, 423 .control_ddrio_2 = 0x4A002E58, 424 .control_hyst_1 = 0x4A002E5C, 425 .control_usbb_hsic_control = 0x4A002E60, 426 .control_c2c = 0x4A002E64, 427 .control_core_control_spare_rw = 0x4A002E68, 428 .control_core_control_spare_r = 0x4A002E6C, 429 .control_core_control_spare_r_c0 = 0x4A002E70, 430 .control_srcomp_north_side = 0x4A002E74, 431 .control_srcomp_south_side = 0x4A002E78, 432 .control_srcomp_east_side = 0x4A002E7C, 433 .control_srcomp_west_side = 0x4A002E80, 434 .control_srcomp_code_latch = 0x4A002E84, 435 .control_ddr_control_ext_0 = 0x4A002E88, 436 .control_padconf_core_base = 0x4A003400, 437 .control_std_fuse_opp_vdd_mpu_2 = 0x4A003B20, 438 .control_port_emif1_sdram_config = 0x4AE0C110, 439 .control_port_emif1_lpddr2_nvm_config = 0x4AE0C114, 440 .control_port_emif2_sdram_config = 0x4AE0C118, 441 .control_emif1_sdram_config_ext = 0x4AE0C144, 442 .control_emif2_sdram_config_ext = 0x4AE0C148, 443 .control_wkup_ldovbb_mpu_voltage_ctrl = 0x4AE0C158, 444 .control_std_fuse_die_id_0 = 0x4AE0C200, 445 .control_std_fuse_die_id_1 = 0x4AE0C208, 446 .control_std_fuse_die_id_2 = 0x4AE0C20C, 447 .control_std_fuse_die_id_3 = 0x4AE0C210, 448 .control_padconf_mode = 0x4AE0C5A0, 449 .control_xtal_oscillator = 0x4AE0C5A4, 450 .control_i2c_2 = 0x4AE0C5A8, 451 .control_ckobuffer = 0x4AE0C5AC, 452 .control_wkup_control_spare_rw = 0x4AE0C5B0, 453 .control_wkup_control_spare_r = 0x4AE0C5B4, 454 .control_wkup_control_spare_r_c0 = 0x4AE0C5B8, 455 .control_srcomp_east_side_wkup = 0x4AE0C5BC, 456 .control_efuse_1 = 0x4AE0C5C8, 457 .control_efuse_2 = 0x4AE0C5CC, 458 .control_efuse_3 = 0x4AE0C5D0, 459 .control_efuse_4 = 0x4AE0C5D4, 460 .control_efuse_13 = 0x4AE0C5F0, 461 .iodelay_config_base = 0x4844A000, 462 }; 463 464 struct prcm_regs const omap5_es2_prcm = { 465 /* cm1.ckgen */ 466 .cm_clksel_core = 0x4a004100, 467 .cm_clksel_abe = 0x4a004108, 468 .cm_dll_ctrl = 0x4a004110, 469 .cm_clkmode_dpll_core = 0x4a004120, 470 .cm_idlest_dpll_core = 0x4a004124, 471 .cm_autoidle_dpll_core = 0x4a004128, 472 .cm_clksel_dpll_core = 0x4a00412c, 473 .cm_div_m2_dpll_core = 0x4a004130, 474 .cm_div_m3_dpll_core = 0x4a004134, 475 .cm_div_h11_dpll_core = 0x4a004138, 476 .cm_div_h12_dpll_core = 0x4a00413c, 477 .cm_div_h13_dpll_core = 0x4a004140, 478 .cm_div_h14_dpll_core = 0x4a004144, 479 .cm_ssc_deltamstep_dpll_core = 0x4a004148, 480 .cm_ssc_modfreqdiv_dpll_core = 0x4a00414c, 481 .cm_div_h21_dpll_core = 0x4a004150, 482 .cm_div_h22_dpllcore = 0x4a004154, 483 .cm_div_h23_dpll_core = 0x4a004158, 484 .cm_div_h24_dpll_core = 0x4a00415c, 485 .cm_clkmode_dpll_mpu = 0x4a004160, 486 .cm_idlest_dpll_mpu = 0x4a004164, 487 .cm_autoidle_dpll_mpu = 0x4a004168, 488 .cm_clksel_dpll_mpu = 0x4a00416c, 489 .cm_div_m2_dpll_mpu = 0x4a004170, 490 .cm_ssc_deltamstep_dpll_mpu = 0x4a004188, 491 .cm_ssc_modfreqdiv_dpll_mpu = 0x4a00418c, 492 .cm_bypclk_dpll_mpu = 0x4a00419c, 493 .cm_clkmode_dpll_iva = 0x4a0041a0, 494 .cm_idlest_dpll_iva = 0x4a0041a4, 495 .cm_autoidle_dpll_iva = 0x4a0041a8, 496 .cm_clksel_dpll_iva = 0x4a0041ac, 497 .cm_div_h11_dpll_iva = 0x4a0041b8, 498 .cm_div_h12_dpll_iva = 0x4a0041bc, 499 .cm_ssc_deltamstep_dpll_iva = 0x4a0041c8, 500 .cm_ssc_modfreqdiv_dpll_iva = 0x4a0041cc, 501 .cm_bypclk_dpll_iva = 0x4a0041dc, 502 .cm_clkmode_dpll_abe = 0x4a0041e0, 503 .cm_idlest_dpll_abe = 0x4a0041e4, 504 .cm_autoidle_dpll_abe = 0x4a0041e8, 505 .cm_clksel_dpll_abe = 0x4a0041ec, 506 .cm_div_m2_dpll_abe = 0x4a0041f0, 507 .cm_div_m3_dpll_abe = 0x4a0041f4, 508 .cm_ssc_deltamstep_dpll_abe = 0x4a004208, 509 .cm_ssc_modfreqdiv_dpll_abe = 0x4a00420c, 510 .cm_clkmode_dpll_ddrphy = 0x4a004220, 511 .cm_idlest_dpll_ddrphy = 0x4a004224, 512 .cm_autoidle_dpll_ddrphy = 0x4a004228, 513 .cm_clksel_dpll_ddrphy = 0x4a00422c, 514 .cm_div_m2_dpll_ddrphy = 0x4a004230, 515 .cm_div_h11_dpll_ddrphy = 0x4a004238, 516 .cm_div_h12_dpll_ddrphy = 0x4a00423c, 517 .cm_div_h13_dpll_ddrphy = 0x4a004240, 518 .cm_ssc_deltamstep_dpll_ddrphy = 0x4a004248, 519 .cm_shadow_freq_config1 = 0x4a004260, 520 .cm_mpu_mpu_clkctrl = 0x4a004320, 521 522 /* cm1.dsp */ 523 .cm_dsp_clkstctrl = 0x4a004400, 524 .cm_dsp_dsp_clkctrl = 0x4a004420, 525 526 /* cm1.abe */ 527 .cm1_abe_clkstctrl = 0x4a004500, 528 .cm1_abe_l4abe_clkctrl = 0x4a004520, 529 .cm1_abe_aess_clkctrl = 0x4a004528, 530 .cm1_abe_pdm_clkctrl = 0x4a004530, 531 .cm1_abe_dmic_clkctrl = 0x4a004538, 532 .cm1_abe_mcasp_clkctrl = 0x4a004540, 533 .cm1_abe_mcbsp1_clkctrl = 0x4a004548, 534 .cm1_abe_mcbsp2_clkctrl = 0x4a004550, 535 .cm1_abe_mcbsp3_clkctrl = 0x4a004558, 536 .cm1_abe_slimbus_clkctrl = 0x4a004560, 537 .cm1_abe_timer5_clkctrl = 0x4a004568, 538 .cm1_abe_timer6_clkctrl = 0x4a004570, 539 .cm1_abe_timer7_clkctrl = 0x4a004578, 540 .cm1_abe_timer8_clkctrl = 0x4a004580, 541 .cm1_abe_wdt3_clkctrl = 0x4a004588, 542 543 /* cm2.ckgen */ 544 .cm_clksel_mpu_m3_iss_root = 0x4a008100, 545 .cm_clksel_usb_60mhz = 0x4a008104, 546 .cm_scale_fclk = 0x4a008108, 547 .cm_core_dvfs_perf1 = 0x4a008110, 548 .cm_core_dvfs_perf2 = 0x4a008114, 549 .cm_core_dvfs_perf3 = 0x4a008118, 550 .cm_core_dvfs_perf4 = 0x4a00811c, 551 .cm_core_dvfs_current = 0x4a008124, 552 .cm_iva_dvfs_perf_tesla = 0x4a008128, 553 .cm_iva_dvfs_perf_ivahd = 0x4a00812c, 554 .cm_iva_dvfs_perf_abe = 0x4a008130, 555 .cm_iva_dvfs_current = 0x4a008138, 556 .cm_clkmode_dpll_per = 0x4a008140, 557 .cm_idlest_dpll_per = 0x4a008144, 558 .cm_autoidle_dpll_per = 0x4a008148, 559 .cm_clksel_dpll_per = 0x4a00814c, 560 .cm_div_m2_dpll_per = 0x4a008150, 561 .cm_div_m3_dpll_per = 0x4a008154, 562 .cm_div_h11_dpll_per = 0x4a008158, 563 .cm_div_h12_dpll_per = 0x4a00815c, 564 .cm_div_h13_dpll_per = 0x4a008160, 565 .cm_div_h14_dpll_per = 0x4a008164, 566 .cm_ssc_deltamstep_dpll_per = 0x4a008168, 567 .cm_ssc_modfreqdiv_dpll_per = 0x4a00816c, 568 .cm_emu_override_dpll_per = 0x4a008170, 569 .cm_clkmode_dpll_usb = 0x4a008180, 570 .cm_idlest_dpll_usb = 0x4a008184, 571 .cm_autoidle_dpll_usb = 0x4a008188, 572 .cm_clksel_dpll_usb = 0x4a00818c, 573 .cm_div_m2_dpll_usb = 0x4a008190, 574 .cm_ssc_deltamstep_dpll_usb = 0x4a0081a8, 575 .cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac, 576 .cm_clkdcoldo_dpll_usb = 0x4a0081b4, 577 .cm_clkmode_dpll_unipro = 0x4a0081c0, 578 .cm_idlest_dpll_unipro = 0x4a0081c4, 579 .cm_autoidle_dpll_unipro = 0x4a0081c8, 580 .cm_clksel_dpll_unipro = 0x4a0081cc, 581 .cm_div_m2_dpll_unipro = 0x4a0081d0, 582 .cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8, 583 .cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec, 584 .cm_coreaon_usb_phy1_core_clkctrl = 0x4A008640, 585 .cm_coreaon_bandgap_clkctrl = 0x4a008648, 586 .cm_coreaon_io_srcomp_clkctrl = 0x4a008650, 587 588 /* cm2.core */ 589 .cm_l3_1_clkstctrl = 0x4a008700, 590 .cm_l3_1_dynamicdep = 0x4a008708, 591 .cm_l3_1_l3_1_clkctrl = 0x4a008720, 592 .cm_l3_2_clkstctrl = 0x4a008800, 593 .cm_l3_2_dynamicdep = 0x4a008808, 594 .cm_l3_2_l3_2_clkctrl = 0x4a008820, 595 .cm_l3_gpmc_clkctrl = 0x4a008828, 596 .cm_l3_2_ocmc_ram_clkctrl = 0x4a008830, 597 .cm_mpu_m3_clkstctrl = 0x4a008900, 598 .cm_mpu_m3_staticdep = 0x4a008904, 599 .cm_mpu_m3_dynamicdep = 0x4a008908, 600 .cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920, 601 .cm_sdma_clkstctrl = 0x4a008a00, 602 .cm_sdma_staticdep = 0x4a008a04, 603 .cm_sdma_dynamicdep = 0x4a008a08, 604 .cm_sdma_sdma_clkctrl = 0x4a008a20, 605 .cm_memif_clkstctrl = 0x4a008b00, 606 .cm_memif_dmm_clkctrl = 0x4a008b20, 607 .cm_memif_emif_fw_clkctrl = 0x4a008b28, 608 .cm_memif_emif_1_clkctrl = 0x4a008b30, 609 .cm_memif_emif_2_clkctrl = 0x4a008b38, 610 .cm_memif_dll_clkctrl = 0x4a008b40, 611 .cm_memif_emif_h1_clkctrl = 0x4a008b50, 612 .cm_memif_emif_h2_clkctrl = 0x4a008b58, 613 .cm_memif_dll_h_clkctrl = 0x4a008b60, 614 .cm_c2c_clkstctrl = 0x4a008c00, 615 .cm_c2c_staticdep = 0x4a008c04, 616 .cm_c2c_dynamicdep = 0x4a008c08, 617 .cm_c2c_sad2d_clkctrl = 0x4a008c20, 618 .cm_c2c_modem_icr_clkctrl = 0x4a008c28, 619 .cm_c2c_sad2d_fw_clkctrl = 0x4a008c30, 620 .cm_l4cfg_clkstctrl = 0x4a008d00, 621 .cm_l4cfg_dynamicdep = 0x4a008d08, 622 .cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20, 623 .cm_l4cfg_hw_sem_clkctrl = 0x4a008d28, 624 .cm_l4cfg_mailbox_clkctrl = 0x4a008d30, 625 .cm_l4cfg_sar_rom_clkctrl = 0x4a008d38, 626 .cm_l3instr_clkstctrl = 0x4a008e00, 627 .cm_l3instr_l3_3_clkctrl = 0x4a008e20, 628 .cm_l3instr_l3_instr_clkctrl = 0x4a008e28, 629 .cm_l3instr_intrconn_wp1_clkctrl = 0x4a008e40, 630 .cm_l4per_clkstctrl = 0x4a009000, 631 .cm_l4per_dynamicdep = 0x4a009008, 632 .cm_l4per_adc_clkctrl = 0x4a009020, 633 .cm_l4per_gptimer10_clkctrl = 0x4a009028, 634 .cm_l4per_gptimer11_clkctrl = 0x4a009030, 635 .cm_l4per_gptimer2_clkctrl = 0x4a009038, 636 .cm_l4per_gptimer3_clkctrl = 0x4a009040, 637 .cm_l4per_gptimer4_clkctrl = 0x4a009048, 638 .cm_l4per_gptimer9_clkctrl = 0x4a009050, 639 .cm_l4per_elm_clkctrl = 0x4a009058, 640 .cm_l4per_gpio2_clkctrl = 0x4a009060, 641 .cm_l4per_gpio3_clkctrl = 0x4a009068, 642 .cm_l4per_gpio4_clkctrl = 0x4a009070, 643 .cm_l4per_gpio5_clkctrl = 0x4a009078, 644 .cm_l4per_gpio6_clkctrl = 0x4a009080, 645 .cm_l4per_hdq1w_clkctrl = 0x4a009088, 646 .cm_l4per_hecc1_clkctrl = 0x4a009090, 647 .cm_l4per_hecc2_clkctrl = 0x4a009098, 648 .cm_l4per_i2c1_clkctrl = 0x4a0090a0, 649 .cm_l4per_i2c2_clkctrl = 0x4a0090a8, 650 .cm_l4per_i2c3_clkctrl = 0x4a0090b0, 651 .cm_l4per_i2c4_clkctrl = 0x4a0090b8, 652 .cm_l4per_l4per_clkctrl = 0x4a0090c0, 653 .cm_l4per_mcasp2_clkctrl = 0x4a0090d0, 654 .cm_l4per_mcasp3_clkctrl = 0x4a0090d8, 655 .cm_l4per_mgate_clkctrl = 0x4a0090e8, 656 .cm_l4per_mcspi1_clkctrl = 0x4a0090f0, 657 .cm_l4per_mcspi2_clkctrl = 0x4a0090f8, 658 .cm_l4per_mcspi3_clkctrl = 0x4a009100, 659 .cm_l4per_mcspi4_clkctrl = 0x4a009108, 660 .cm_l4per_gpio7_clkctrl = 0x4a009110, 661 .cm_l4per_gpio8_clkctrl = 0x4a009118, 662 .cm_l4per_mmcsd3_clkctrl = 0x4a009120, 663 .cm_l4per_mmcsd4_clkctrl = 0x4a009128, 664 .cm_l4per_msprohg_clkctrl = 0x4a009130, 665 .cm_l4per_slimbus2_clkctrl = 0x4a009138, 666 .cm_l4per_uart1_clkctrl = 0x4a009140, 667 .cm_l4per_uart2_clkctrl = 0x4a009148, 668 .cm_l4per_uart3_clkctrl = 0x4a009150, 669 .cm_l4per_uart4_clkctrl = 0x4a009158, 670 .cm_l4per_mmcsd5_clkctrl = 0x4a009160, 671 .cm_l4per_i2c5_clkctrl = 0x4a009168, 672 .cm_l4per_uart5_clkctrl = 0x4a009170, 673 .cm_l4per_uart6_clkctrl = 0x4a009178, 674 .cm_l4sec_clkstctrl = 0x4a009180, 675 .cm_l4sec_staticdep = 0x4a009184, 676 .cm_l4sec_dynamicdep = 0x4a009188, 677 .cm_l4sec_aes1_clkctrl = 0x4a0091a0, 678 .cm_l4sec_aes2_clkctrl = 0x4a0091a8, 679 .cm_l4sec_des3des_clkctrl = 0x4a0091b0, 680 .cm_l4sec_pkaeip29_clkctrl = 0x4a0091b8, 681 .cm_l4sec_rng_clkctrl = 0x4a0091c0, 682 .cm_l4sec_sha2md51_clkctrl = 0x4a0091c8, 683 .cm_l4sec_cryptodma_clkctrl = 0x4a0091d8, 684 685 /* cm2.ivahd */ 686 .cm_ivahd_clkstctrl = 0x4a009200, 687 .cm_ivahd_ivahd_clkctrl = 0x4a009220, 688 .cm_ivahd_sl2_clkctrl = 0x4a009228, 689 690 /* cm2.cam */ 691 .cm_cam_clkstctrl = 0x4a009300, 692 .cm_cam_iss_clkctrl = 0x4a009320, 693 .cm_cam_fdif_clkctrl = 0x4a009328, 694 695 /* cm2.dss */ 696 .cm_dss_clkstctrl = 0x4a009400, 697 .cm_dss_dss_clkctrl = 0x4a009420, 698 699 /* cm2.sgx */ 700 .cm_sgx_clkstctrl = 0x4a009500, 701 .cm_sgx_sgx_clkctrl = 0x4a009520, 702 703 /* cm2.l3init */ 704 .cm_l3init_clkstctrl = 0x4a009600, 705 706 /* cm2.l3init */ 707 .cm_l3init_hsmmc1_clkctrl = 0x4a009628, 708 .cm_l3init_hsmmc2_clkctrl = 0x4a009630, 709 .cm_l3init_hsi_clkctrl = 0x4a009638, 710 .cm_l3init_hsusbhost_clkctrl = 0x4a009658, 711 .cm_l3init_hsusbotg_clkctrl = 0x4a009660, 712 .cm_l3init_hsusbtll_clkctrl = 0x4a009668, 713 .cm_l3init_p1500_clkctrl = 0x4a009678, 714 .cm_l3init_sata_clkctrl = 0x4a009688, 715 .cm_l3init_fsusb_clkctrl = 0x4a0096d0, 716 .cm_l3init_ocp2scp1_clkctrl = 0x4a0096e0, 717 .cm_l3init_ocp2scp3_clkctrl = 0x4a0096e8, 718 .cm_l3init_usb_otg_ss1_clkctrl = 0x4a0096f0, 719 720 /* prm irqstatus regs */ 721 .prm_irqstatus_mpu_2 = 0x4ae06014, 722 723 /* l4 wkup regs */ 724 .cm_abe_pll_ref_clksel = 0x4ae0610c, 725 .cm_sys_clksel = 0x4ae06110, 726 .cm_wkup_clkstctrl = 0x4ae07900, 727 .cm_wkup_l4wkup_clkctrl = 0x4ae07920, 728 .cm_wkup_wdtimer1_clkctrl = 0x4ae07928, 729 .cm_wkup_wdtimer2_clkctrl = 0x4ae07930, 730 .cm_wkup_gpio1_clkctrl = 0x4ae07938, 731 .cm_wkup_gptimer1_clkctrl = 0x4ae07940, 732 .cm_wkup_gptimer12_clkctrl = 0x4ae07948, 733 .cm_wkup_synctimer_clkctrl = 0x4ae07950, 734 .cm_wkup_usim_clkctrl = 0x4ae07958, 735 .cm_wkup_sarram_clkctrl = 0x4ae07960, 736 .cm_wkup_keyboard_clkctrl = 0x4ae07978, 737 .cm_wkup_rtc_clkctrl = 0x4ae07980, 738 .cm_wkup_bandgap_clkctrl = 0x4ae07988, 739 .cm_wkupaon_scrm_clkctrl = 0x4ae07990, 740 .cm_wkupaon_io_srcomp_clkctrl = 0x4ae07998, 741 .prm_rstctrl = 0x4ae07c00, 742 .prm_rstst = 0x4ae07c04, 743 .prm_rsttime = 0x4ae07c08, 744 .prm_vc_val_bypass = 0x4ae07ca0, 745 .prm_vc_cfg_i2c_mode = 0x4ae07cb4, 746 .prm_vc_cfg_i2c_clk = 0x4ae07cb8, 747 748 .prm_abbldo_mpu_setup = 0x4ae07cdc, 749 .prm_abbldo_mpu_ctrl = 0x4ae07ce0, 750 751 /* SCRM stuff, used by some boards */ 752 .scrm_auxclk0 = 0x4ae0a310, 753 .scrm_auxclk1 = 0x4ae0a314, 754 }; 755 756 struct prcm_regs const dra7xx_prcm = { 757 /* cm1.ckgen */ 758 .cm_clksel_core = 0x4a005100, 759 .cm_clksel_abe = 0x4a005108, 760 .cm_dll_ctrl = 0x4a005110, 761 .cm_clkmode_dpll_core = 0x4a005120, 762 .cm_idlest_dpll_core = 0x4a005124, 763 .cm_autoidle_dpll_core = 0x4a005128, 764 .cm_clksel_dpll_core = 0x4a00512c, 765 .cm_div_m2_dpll_core = 0x4a005130, 766 .cm_div_m3_dpll_core = 0x4a005134, 767 .cm_div_h11_dpll_core = 0x4a005138, 768 .cm_div_h12_dpll_core = 0x4a00513c, 769 .cm_div_h13_dpll_core = 0x4a005140, 770 .cm_div_h14_dpll_core = 0x4a005144, 771 .cm_ssc_deltamstep_dpll_core = 0x4a005148, 772 .cm_ssc_modfreqdiv_dpll_core = 0x4a00514c, 773 .cm_div_h21_dpll_core = 0x4a005150, 774 .cm_div_h22_dpllcore = 0x4a005154, 775 .cm_div_h23_dpll_core = 0x4a005158, 776 .cm_div_h24_dpll_core = 0x4a00515c, 777 .cm_clkmode_dpll_mpu = 0x4a005160, 778 .cm_idlest_dpll_mpu = 0x4a005164, 779 .cm_autoidle_dpll_mpu = 0x4a005168, 780 .cm_clksel_dpll_mpu = 0x4a00516c, 781 .cm_div_m2_dpll_mpu = 0x4a005170, 782 .cm_ssc_deltamstep_dpll_mpu = 0x4a005188, 783 .cm_ssc_modfreqdiv_dpll_mpu = 0x4a00518c, 784 .cm_bypclk_dpll_mpu = 0x4a00519c, 785 .cm_clkmode_dpll_iva = 0x4a0051a0, 786 .cm_idlest_dpll_iva = 0x4a0051a4, 787 .cm_autoidle_dpll_iva = 0x4a0051a8, 788 .cm_clksel_dpll_iva = 0x4a0051ac, 789 .cm_ssc_deltamstep_dpll_iva = 0x4a0051c8, 790 .cm_ssc_modfreqdiv_dpll_iva = 0x4a0051cc, 791 .cm_bypclk_dpll_iva = 0x4a0051dc, 792 .cm_clkmode_dpll_abe = 0x4a0051e0, 793 .cm_idlest_dpll_abe = 0x4a0051e4, 794 .cm_autoidle_dpll_abe = 0x4a0051e8, 795 .cm_clksel_dpll_abe = 0x4a0051ec, 796 .cm_div_m2_dpll_abe = 0x4a0051f0, 797 .cm_div_m3_dpll_abe = 0x4a0051f4, 798 .cm_ssc_deltamstep_dpll_abe = 0x4a005208, 799 .cm_ssc_modfreqdiv_dpll_abe = 0x4a00520c, 800 .cm_clkmode_dpll_ddrphy = 0x4a005210, 801 .cm_idlest_dpll_ddrphy = 0x4a005214, 802 .cm_autoidle_dpll_ddrphy = 0x4a005218, 803 .cm_clksel_dpll_ddrphy = 0x4a00521c, 804 .cm_div_m2_dpll_ddrphy = 0x4a005220, 805 .cm_div_h11_dpll_ddrphy = 0x4a005228, 806 .cm_ssc_deltamstep_dpll_ddrphy = 0x4a00522c, 807 .cm_clkmode_dpll_dsp = 0x4a005234, 808 .cm_shadow_freq_config1 = 0x4a005260, 809 .cm_clkmode_dpll_gmac = 0x4a0052a8, 810 .cm_coreaon_usb_phy1_core_clkctrl = 0x4a008640, 811 .cm_coreaon_usb_phy2_core_clkctrl = 0x4a008688, 812 813 /* cm1.mpu */ 814 .cm_mpu_mpu_clkctrl = 0x4a005320, 815 816 /* cm1.dsp */ 817 .cm_dsp_clkstctrl = 0x4a005400, 818 .cm_dsp_dsp_clkctrl = 0x4a005420, 819 820 /* cm IPU */ 821 .cm_ipu_clkstctrl = 0x4a005540, 822 .cm_ipu_i2c5_clkctrl = 0x4a005578, 823 824 /* prm irqstatus regs */ 825 .prm_irqstatus_mpu_2 = 0x4ae06014, 826 827 /* cm2.ckgen */ 828 .cm_clksel_usb_60mhz = 0x4a008104, 829 .cm_clkmode_dpll_per = 0x4a008140, 830 .cm_idlest_dpll_per = 0x4a008144, 831 .cm_autoidle_dpll_per = 0x4a008148, 832 .cm_clksel_dpll_per = 0x4a00814c, 833 .cm_div_m2_dpll_per = 0x4a008150, 834 .cm_div_m3_dpll_per = 0x4a008154, 835 .cm_div_h11_dpll_per = 0x4a008158, 836 .cm_div_h12_dpll_per = 0x4a00815c, 837 .cm_div_h13_dpll_per = 0x4a008160, 838 .cm_div_h14_dpll_per = 0x4a008164, 839 .cm_ssc_deltamstep_dpll_per = 0x4a008168, 840 .cm_ssc_modfreqdiv_dpll_per = 0x4a00816c, 841 .cm_clkmode_dpll_usb = 0x4a008180, 842 .cm_idlest_dpll_usb = 0x4a008184, 843 .cm_autoidle_dpll_usb = 0x4a008188, 844 .cm_clksel_dpll_usb = 0x4a00818c, 845 .cm_div_m2_dpll_usb = 0x4a008190, 846 .cm_ssc_deltamstep_dpll_usb = 0x4a0081a8, 847 .cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac, 848 .cm_clkdcoldo_dpll_usb = 0x4a0081b4, 849 .cm_clkmode_dpll_pcie_ref = 0x4a008200, 850 .cm_clkmode_apll_pcie = 0x4a00821c, 851 .cm_idlest_apll_pcie = 0x4a008220, 852 .cm_div_m2_apll_pcie = 0x4a008224, 853 .cm_clkvcoldo_apll_pcie = 0x4a008228, 854 855 /* cm2.core */ 856 .cm_l3_1_clkstctrl = 0x4a008700, 857 .cm_l3_1_dynamicdep = 0x4a008708, 858 .cm_l3_1_l3_1_clkctrl = 0x4a008720, 859 .cm_l3_gpmc_clkctrl = 0x4a008728, 860 .cm_mpu_m3_clkstctrl = 0x4a008900, 861 .cm_mpu_m3_staticdep = 0x4a008904, 862 .cm_mpu_m3_dynamicdep = 0x4a008908, 863 .cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920, 864 .cm_sdma_clkstctrl = 0x4a008a00, 865 .cm_sdma_staticdep = 0x4a008a04, 866 .cm_sdma_dynamicdep = 0x4a008a08, 867 .cm_sdma_sdma_clkctrl = 0x4a008a20, 868 .cm_memif_clkstctrl = 0x4a008b00, 869 .cm_memif_dmm_clkctrl = 0x4a008b20, 870 .cm_memif_emif_fw_clkctrl = 0x4a008b28, 871 .cm_memif_emif_1_clkctrl = 0x4a008b30, 872 .cm_memif_emif_2_clkctrl = 0x4a008b38, 873 .cm_memif_dll_clkctrl = 0x4a008b40, 874 .cm_l4cfg_clkstctrl = 0x4a008d00, 875 .cm_l4cfg_dynamicdep = 0x4a008d08, 876 .cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20, 877 .cm_l4cfg_hw_sem_clkctrl = 0x4a008d28, 878 .cm_l4cfg_mailbox_clkctrl = 0x4a008d30, 879 .cm_l4cfg_sar_rom_clkctrl = 0x4a008d38, 880 .cm_l3instr_clkstctrl = 0x4a008e00, 881 .cm_l3instr_l3_3_clkctrl = 0x4a008e20, 882 .cm_l3instr_l3_instr_clkctrl = 0x4a008e28, 883 .cm_l3instr_intrconn_wp1_clkctrl = 0x4a008e40, 884 885 /* cm2.ivahd */ 886 .cm_ivahd_clkstctrl = 0x4a008f00, 887 .cm_ivahd_ivahd_clkctrl = 0x4a008f20, 888 .cm_ivahd_sl2_clkctrl = 0x4a008f28, 889 890 /* cm2.cam */ 891 .cm_cam_clkstctrl = 0x4a009000, 892 .cm_cam_vip1_clkctrl = 0x4a009020, 893 .cm_cam_vip2_clkctrl = 0x4a009028, 894 .cm_cam_vip3_clkctrl = 0x4a009030, 895 .cm_cam_lvdsrx_clkctrl = 0x4a009038, 896 .cm_cam_csi1_clkctrl = 0x4a009040, 897 .cm_cam_csi2_clkctrl = 0x4a009048, 898 899 /* cm2.dss */ 900 .cm_dss_clkstctrl = 0x4a009100, 901 .cm_dss_dss_clkctrl = 0x4a009120, 902 903 /* cm2.sgx */ 904 .cm_sgx_clkstctrl = 0x4a009200, 905 .cm_sgx_sgx_clkctrl = 0x4a009220, 906 907 /* cm2.l3init */ 908 .cm_l3init_clkstctrl = 0x4a009300, 909 910 /* cm2.l3init */ 911 .cm_l3init_hsmmc1_clkctrl = 0x4a009328, 912 .cm_l3init_hsmmc2_clkctrl = 0x4a009330, 913 .cm_l3init_hsusbhost_clkctrl = 0x4a009340, 914 .cm_l3init_hsusbotg_clkctrl = 0x4a009348, 915 .cm_l3init_hsusbtll_clkctrl = 0x4a009350, 916 .cm_l3init_sata_clkctrl = 0x4a009388, 917 .cm_gmac_clkstctrl = 0x4a0093c0, 918 .cm_gmac_gmac_clkctrl = 0x4a0093d0, 919 .cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0, 920 .cm_l3init_ocp2scp3_clkctrl = 0x4a0093e8, 921 .cm_l3init_usb_otg_ss1_clkctrl = 0x4a0093f0, 922 923 /* cm2.l4per */ 924 .cm_l4per_clkstctrl = 0x4a009700, 925 .cm_l4per_dynamicdep = 0x4a009708, 926 .cm_l4per_gptimer10_clkctrl = 0x4a009728, 927 .cm_l4per_gptimer11_clkctrl = 0x4a009730, 928 .cm_l4per_gptimer2_clkctrl = 0x4a009738, 929 .cm_l4per_gptimer3_clkctrl = 0x4a009740, 930 .cm_l4per_gptimer4_clkctrl = 0x4a009748, 931 .cm_l4per_gptimer9_clkctrl = 0x4a009750, 932 .cm_l4per_elm_clkctrl = 0x4a009758, 933 .cm_l4per_gpio2_clkctrl = 0x4a009760, 934 .cm_l4per_gpio3_clkctrl = 0x4a009768, 935 .cm_l4per_gpio4_clkctrl = 0x4a009770, 936 .cm_l4per_gpio5_clkctrl = 0x4a009778, 937 .cm_l4per_gpio6_clkctrl = 0x4a009780, 938 .cm_l4per_hdq1w_clkctrl = 0x4a009788, 939 .cm_l4per_i2c1_clkctrl = 0x4a0097a0, 940 .cm_l4per_i2c2_clkctrl = 0x4a0097a8, 941 .cm_l4per_i2c3_clkctrl = 0x4a0097b0, 942 .cm_l4per_i2c4_clkctrl = 0x4a0097b8, 943 .cm_l4per_l4per_clkctrl = 0x4a0097c0, 944 .cm_l4per_mcspi1_clkctrl = 0x4a0097f0, 945 .cm_l4per_mcspi2_clkctrl = 0x4a0097f8, 946 .cm_l4per_mcspi3_clkctrl = 0x4a009800, 947 .cm_l4per_mcspi4_clkctrl = 0x4a009808, 948 .cm_l4per_gpio7_clkctrl = 0x4a009810, 949 .cm_l4per_gpio8_clkctrl = 0x4a009818, 950 .cm_l4per_mmcsd3_clkctrl = 0x4a009820, 951 .cm_l4per_mmcsd4_clkctrl = 0x4a009828, 952 .cm_l4per_qspi_clkctrl = 0x4a009838, 953 .cm_l4per_uart1_clkctrl = 0x4a009840, 954 .cm_l4per_uart2_clkctrl = 0x4a009848, 955 .cm_l4per_uart3_clkctrl = 0x4a009850, 956 .cm_l4per_uart4_clkctrl = 0x4a009858, 957 .cm_l4per_uart5_clkctrl = 0x4a009870, 958 .cm_l4sec_clkstctrl = 0x4a009880, 959 .cm_l4sec_staticdep = 0x4a009884, 960 .cm_l4sec_dynamicdep = 0x4a009888, 961 .cm_l4sec_aes1_clkctrl = 0x4a0098a0, 962 .cm_l4sec_aes2_clkctrl = 0x4a0098a8, 963 .cm_l4sec_des3des_clkctrl = 0x4a0098b0, 964 .cm_l4sec_rng_clkctrl = 0x4a0098c0, 965 .cm_l4sec_sha2md51_clkctrl = 0x4a0098c8, 966 .cm_l4sec_cryptodma_clkctrl = 0x4a0098d8, 967 968 /* l4 wkup regs */ 969 .cm_abe_pll_ref_clksel = 0x4ae0610c, 970 .cm_sys_clksel = 0x4ae06110, 971 .cm_abe_pll_sys_clksel = 0x4ae06118, 972 .cm_wkup_clkstctrl = 0x4ae07800, 973 .cm_wkup_l4wkup_clkctrl = 0x4ae07820, 974 .cm_wkup_wdtimer1_clkctrl = 0x4ae07828, 975 .cm_wkup_wdtimer2_clkctrl = 0x4ae07830, 976 .cm_wkup_gpio1_clkctrl = 0x4ae07838, 977 .cm_wkup_gptimer1_clkctrl = 0x4ae07840, 978 .cm_wkup_gptimer12_clkctrl = 0x4ae07848, 979 .cm_wkup_sarram_clkctrl = 0x4ae07860, 980 .cm_wkup_keyboard_clkctrl = 0x4ae07878, 981 .cm_wkupaon_scrm_clkctrl = 0x4ae07890, 982 .prm_rstctrl = 0x4ae07d00, 983 .prm_rstst = 0x4ae07d04, 984 .prm_rsttime = 0x4ae07d08, 985 .prm_io_pmctrl = 0x4ae07d20, 986 .prm_vc_val_bypass = 0x4ae07da0, 987 .prm_vc_cfg_i2c_mode = 0x4ae07db4, 988 .prm_vc_cfg_i2c_clk = 0x4ae07db8, 989 990 .prm_abbldo_mpu_setup = 0x4AE07DDC, 991 .prm_abbldo_mpu_ctrl = 0x4AE07DE0, 992 }; 993