1 /*
2 * (C) Copyright 2013
3 * David Feng <fenghua@phytium.com.cn>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8 #ifndef _ASM_ARMV8_MMU_H_
9 #define _ASM_ARMV8_MMU_H_
10
11 #ifdef __ASSEMBLY__
12 #define _AC(X, Y) X
13 #else
14 #define _AC(X, Y) (X##Y)
15 #endif
16
17 #define UL(x) _AC(x, UL)
18
19 /***************************************************************/
20 /*
21 * The following definitions are related each other, shoud be
22 * calculated specifically.
23 */
24 #define VA_BITS (42) /* 42 bits virtual address */
25
26 /* PAGE_SHIFT determines the page size */
27 #undef PAGE_SIZE
28 #define PAGE_SHIFT 16
29 #define PAGE_SIZE (1 << PAGE_SHIFT)
30 #define PAGE_MASK (~(PAGE_SIZE-1))
31
32 /*
33 * section address mask and size definitions.
34 */
35 #define SECTION_SHIFT 29
36 #define SECTION_SIZE (UL(1) << SECTION_SHIFT)
37 #define SECTION_MASK (~(SECTION_SIZE-1))
38 /***************************************************************/
39
40 /*
41 * Memory types
42 */
43 #define MT_DEVICE_NGNRNE 0
44 #define MT_DEVICE_NGNRE 1
45 #define MT_DEVICE_GRE 2
46 #define MT_NORMAL_NC 3
47 #define MT_NORMAL 4
48
49 #define MEMORY_ATTRIBUTES ((0x00 << (MT_DEVICE_NGNRNE*8)) | \
50 (0x04 << (MT_DEVICE_NGNRE*8)) | \
51 (0x0c << (MT_DEVICE_GRE*8)) | \
52 (0x44 << (MT_NORMAL_NC*8)) | \
53 (UL(0xff) << (MT_NORMAL*8)))
54
55 /*
56 * Hardware page table definitions.
57 *
58 * Level 2 descriptor (PMD).
59 */
60 #define PMD_TYPE_MASK (3 << 0)
61 #define PMD_TYPE_FAULT (0 << 0)
62 #define PMD_TYPE_TABLE (3 << 0)
63 #define PMD_TYPE_SECT (1 << 0)
64
65 /*
66 * Section
67 */
68 #define PMD_SECT_OUTER_SHARE (2 << 8)
69 #define PMD_SECT_INNER_SHARE (3 << 8)
70 #define PMD_SECT_AF (1 << 10)
71 #define PMD_SECT_NG (1 << 11)
72 #define PMD_SECT_PXN (UL(1) << 53)
73 #define PMD_SECT_UXN (UL(1) << 54)
74
75 /*
76 * AttrIndx[2:0]
77 */
78 #define PMD_ATTRINDX(t) ((t) << 2)
79 #define PMD_ATTRINDX_MASK (7 << 2)
80
81 /*
82 * TCR flags.
83 */
84 #define TCR_T0SZ(x) ((64 - (x)) << 0)
85 #define TCR_IRGN_NC (0 << 8)
86 #define TCR_IRGN_WBWA (1 << 8)
87 #define TCR_IRGN_WT (2 << 8)
88 #define TCR_IRGN_WBNWA (3 << 8)
89 #define TCR_IRGN_MASK (3 << 8)
90 #define TCR_ORGN_NC (0 << 10)
91 #define TCR_ORGN_WBWA (1 << 10)
92 #define TCR_ORGN_WT (2 << 10)
93 #define TCR_ORGN_WBNWA (3 << 10)
94 #define TCR_ORGN_MASK (3 << 10)
95 #define TCR_SHARED_NON (0 << 12)
96 #define TCR_SHARED_OUTER (1 << 12)
97 #define TCR_SHARED_INNER (2 << 12)
98 #define TCR_TG0_4K (0 << 14)
99 #define TCR_TG0_64K (1 << 14)
100 #define TCR_TG0_16K (2 << 14)
101 #define TCR_EL1_IPS_BITS (UL(3) << 32) /* 42 bits physical address */
102 #define TCR_EL2_IPS_BITS (3 << 16) /* 42 bits physical address */
103 #define TCR_EL3_IPS_BITS (3 << 16) /* 42 bits physical address */
104
105 /* PTWs cacheable, inner/outer WBWA and non-shareable */
106 #define TCR_FLAGS (TCR_TG0_64K | \
107 TCR_SHARED_NON | \
108 TCR_ORGN_WBWA | \
109 TCR_IRGN_WBWA | \
110 TCR_T0SZ(VA_BITS))
111
112 #ifndef __ASSEMBLY__
113 void set_pgtable_section(u64 *page_table, u64 index,
114 u64 section, u64 memory_type);
set_ttbr_tcr_mair(int el,u64 table,u64 tcr,u64 attr)115 static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr)
116 {
117 asm volatile("dsb sy");
118 if (el == 1) {
119 asm volatile("msr ttbr0_el1, %0" : : "r" (table) : "memory");
120 asm volatile("msr tcr_el1, %0" : : "r" (tcr) : "memory");
121 asm volatile("msr mair_el1, %0" : : "r" (attr) : "memory");
122 } else if (el == 2) {
123 asm volatile("msr ttbr0_el2, %0" : : "r" (table) : "memory");
124 asm volatile("msr tcr_el2, %0" : : "r" (tcr) : "memory");
125 asm volatile("msr mair_el2, %0" : : "r" (attr) : "memory");
126 } else if (el == 3) {
127 asm volatile("msr ttbr0_el3, %0" : : "r" (table) : "memory");
128 asm volatile("msr tcr_el3, %0" : : "r" (tcr) : "memory");
129 asm volatile("msr mair_el3, %0" : : "r" (attr) : "memory");
130 } else {
131 hang();
132 }
133 asm volatile("isb");
134 }
135 #endif
136 #endif /* _ASM_ARMV8_MMU_H_ */
137