1/* 2 * SPDX-License-Identifier: GPL-2.0 IBM-pibs 3 */ 4/*----------------------------------------------------------------------------- 5 * Function: ext_bus_cntlr_init 6 * Description: Initializes the External Bus Controller for the external 7 * peripherals. IMPORTANT: For pass1 this code must run from 8 * cache since you can not reliably change a peripheral banks 9 * timing register (pbxap) while running code from that bank. 10 * For ex., since we are running from ROM on bank 0, we can NOT 11 * execute the code that modifies bank 0 timings from ROM, so 12 * we run it from cache. 13 * Bank 0 - Flash or Multi Purpose Socket 14 * Bank 1 - Multi Purpose Socket or Flash (set in C-Code) 15 * Bank 2 - UART 1 (set in C-Code) 16 * Bank 3 - UART 2 (set in C-Code) 17 * Bank 4 - not used 18 * Bank 5 - not used 19 * Bank 6 - not used 20 * Bank 7 - PLD Register 21 *-----------------------------------------------------------------------------*/ 22 23#include <configs/MIP405.h> 24#include <ppc_asm.tmpl> 25#include <ppc_defs.h> 26 27#include <asm/cache.h> 28#include <asm/mmu.h> 29#include <asm/ppc4xx.h> 30#include "mip405.h" 31 32 33 .globl ext_bus_cntlr_init 34ext_bus_cntlr_init: 35 mflr r4 /* save link register */ 36 mfdcr r3,CPC0_PSR /* get strapping reg */ 37 andi. r0, r3, PSR_ROM_LOC /* mask out irrelevant bits */ 38 bnelr /* jump back if PCI boot */ 39 40 bl ..getAddr 41..getAddr: 42 mflr r3 /* get address of ..getAddr */ 43 mtlr r4 /* restore link register */ 44 addi r4,0,14 /* set ctr to 14; used to prefetch */ 45 mtctr r4 /* 14 cache lines to fit this function */ 46 /* in cache (gives us 8x14=112 instrctns) */ 47..ebcloop: 48 icbt r0,r3 /* prefetch cache line for addr in r3 */ 49 addi r3,r3,32 /* move to next cache line */ 50 bdnz ..ebcloop /* continue for 14 cache lines */ 51 52 /*------------------------------------------------------------------- 53 * Delay to ensure all accesses to ROM are complete before changing 54 * bank 0 timings. 55 *------------------------------------------------------------------- */ 56 addis r3,0,0x0 57 ori r3,r3,0xA000 58 mtctr r3 59..spinlp: 60 bdnz ..spinlp /* spin loop */ 61 62 /*----------------------------------------------------------------------- 63 * decide boot up mode 64 *----------------------------------------------------------------------- */ 65 addi r4,0,PB0CR 66 mtdcr EBC0_CFGADDR,r4 67 mfdcr r4,EBC0_CFGDATA 68 69 andi. r0, r4, 0x2000 /* mask out irrelevant bits */ 70 beq 0f /* jump if 8 bit bus width */ 71 72 /* setup 16 bit things 73 *----------------------------------------------------------------------- 74 * Memory Bank 0 (16 Bit Flash) initialization 75 *---------------------------------------------------------------------- */ 76 77 addi r4,0,PB1AP 78 mtdcr EBC0_CFGADDR,r4 79 addis r4,0,(FLASH_AP_B)@h 80 ori r4,r4,(FLASH_AP_B)@l 81 mtdcr EBC0_CFGDATA,r4 82 83 addi r4,0,PB0CR 84 mtdcr EBC0_CFGADDR,r4 85 /* BS=0x010(4MB),BU=0x3(R/W), */ 86 addis r4,0,(FLASH_CR_B)@h 87 ori r4,r4,(FLASH_CR_B)@l 88 mtdcr EBC0_CFGDATA,r4 89 b 1f 90 910: 92 93 /* 8Bit boot mode: */ 94 /*----------------------------------------------------------------------- 95 * Memory Bank 0 Multi Purpose Socket initialization 96 *----------------------------------------------------------------------- */ 97 /* 0x7F8FFE80 slowest boot */ 98 addi r4,0,PB1AP 99 mtdcr EBC0_CFGADDR,r4 100 addis r4,0,(MPS_AP_B)@h 101 ori r4,r4,(MPS_AP_B)@l 102 mtdcr EBC0_CFGDATA,r4 103 104 addi r4,0,PB0CR 105 mtdcr EBC0_CFGADDR,r4 106 /* BS=0x010(4MB),BU=0x3(R/W), */ 107 addis r4,0,(MPS_CR_B)@h 108 ori r4,r4,(MPS_CR_B)@l 109 110 mtdcr EBC0_CFGDATA,r4 111 112 1131: 114 /*----------------------------------------------------------------------- 115 * Memory Bank 2-3-4-5-6 (not used) initialization 116 *-----------------------------------------------------------------------*/ 117 addi r4,0,PB1CR 118 mtdcr EBC0_CFGADDR,r4 119 addis r4,0,0x0000 120 ori r4,r4,0x0000 121 mtdcr EBC0_CFGDATA,r4 122 123 addi r4,0,PB2CR 124 mtdcr EBC0_CFGADDR,r4 125 addis r4,0,0x0000 126 ori r4,r4,0x0000 127 mtdcr EBC0_CFGDATA,r4 128 129 addi r4,0,PB3CR 130 mtdcr EBC0_CFGADDR,r4 131 addis r4,0,0x0000 132 ori r4,r4,0x0000 133 mtdcr EBC0_CFGDATA,r4 134 135 addi r4,0,PB4CR 136 mtdcr EBC0_CFGADDR,r4 137 addis r4,0,0x0000 138 ori r4,r4,0x0000 139 mtdcr EBC0_CFGDATA,r4 140 141 addi r4,0,PB5CR 142 mtdcr EBC0_CFGADDR,r4 143 addis r4,0,0x0000 144 ori r4,r4,0x0000 145 mtdcr EBC0_CFGDATA,r4 146 147 addi r4,0,PB6CR 148 mtdcr EBC0_CFGADDR,r4 149 addis r4,0,0x0000 150 ori r4,r4,0x0000 151 mtdcr EBC0_CFGDATA,r4 152 153 addi r4,0,PB7CR 154 mtdcr EBC0_CFGADDR,r4 155 addis r4,0,0x0000 156 ori r4,r4,0x0000 157 mtdcr EBC0_CFGDATA,r4 158 nop /* pass2 DCR errata #8 */ 159 blr 160 161#if defined(CONFIG_BOOT_PCI) 162 .section .bootpg,"ax" 163 .globl _start_pci 164/******************************************* 165 */ 166 167_start_pci: 168 /* first handle errata #68 / PCI_18 */ 169 iccci r0, r0 /* invalidate I-cache */ 170 lis r31, 0 171 mticcr r31 /* ICCR = 0 (all uncachable) */ 172 isync 173 174 mfccr0 r28 /* set CCR0[24] = 1 */ 175 ori r28, r28, 0x0080 176 mtccr0 r28 177 178 /* setup PMM0MA (0xEF400004) and PMM0PCIHA (0xEF40000C) */ 179 lis r28, 0xEF40 180 addi r28, r28, 0x0004 181 stw r31, 0x0C(r28) /* clear PMM0PCIHA */ 182 lis r29, 0xFFF8 /* open 512 kByte */ 183 addi r29, r29, 0x0001/* and enable this region */ 184 stwbrx r29, r0, r28 /* write PMM0MA */ 185 186 lis r28, 0xEEC0 /* address of PCIC0_CFGADDR */ 187 addi r29, r28, 4 /* add 4 to r29 -> PCIC0_CFGDATA */ 188 189 lis r31, 0x8000 /* set en bit bus 0 */ 190 ori r31, r31, 0x304C/* device 6 func 0 reg 4C (XBCS register) */ 191 stwbrx r31, r0, r28 /* write it */ 192 193 lwbrx r31, r0, r29 /* load XBCS register */ 194 oris r31, r31, 0x02C4/* clear BIOSCS WPE, set lower, extended and 1M extended BIOS enable */ 195 stwbrx r31, r0, r29 /* write back XBCS register */ 196 197 nop 198 nop 199 b _start /* normal start */ 200#endif 201