1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* 3 * Cadence DDR Driver 4 * 5 * Copyright (C) 2012-2021 Cadence Design Systems, Inc. 6 * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/ 7 */ 8 9 #ifndef lpddr4_obj_if_h 10 #define lpddr4_obj_if_h 11 12 #include "lpddr4_if.h" 13 14 typedef struct lpddr4_obj_s { 15 u32 (*probe)(const lpddr4_config *config, u16 *configsize); 16 17 u32 (*init)(lpddr4_privatedata *pd, const lpddr4_config *cfg); 18 19 u32 (*start)(const lpddr4_privatedata *pd); 20 21 u32 (*readreg)(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 *regvalue); 22 23 u32 (*writereg)(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 regvalue); 24 25 u32 (*getmmrregister)(const lpddr4_privatedata *pd, u32 readmoderegval, u64 *mmrvalue, u8 *mmrstatus); 26 27 u32 (*setmmrregister)(const lpddr4_privatedata *pd, u32 writemoderegval, u8 *mrwstatus); 28 29 u32 (*writectlconfig)(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount); 30 31 u32 (*writephyconfig)(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount); 32 33 u32 (*writephyindepconfig)(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount); 34 35 u32 (*readctlconfig)(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount); 36 37 u32 (*readphyconfig)(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount); 38 39 u32 (*readphyindepconfig)(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount); 40 41 u32 (*getctlinterruptmask)(const lpddr4_privatedata *pd, u64 *mask); 42 43 u32 (*setctlinterruptmask)(const lpddr4_privatedata *pd, const u64 *mask); 44 45 u32 (*checkctlinterrupt)(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr, bool *irqstatus); 46 47 u32 (*ackctlinterrupt)(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr); 48 49 u32 (*getphyindepinterruptmask)(const lpddr4_privatedata *pd, u32 *mask); 50 51 u32 (*setphyindepinterruptmask)(const lpddr4_privatedata *pd, const u32 *mask); 52 53 u32 (*checkphyindepinterrupt)(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt intr, bool *irqstatus); 54 55 u32 (*ackphyindepinterrupt)(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt intr); 56 57 u32 (*getdebuginitinfo)(const lpddr4_privatedata *pd, lpddr4_debuginfo *debuginfo); 58 59 u32 (*getlpiwakeuptime)(const lpddr4_privatedata *pd, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, u32 *cycles); 60 61 u32 (*setlpiwakeuptime)(const lpddr4_privatedata *pd, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, const u32 *cycles); 62 63 u32 (*geteccenable)(const lpddr4_privatedata *pd, lpddr4_eccenable *eccparam); 64 65 u32 (*seteccenable)(const lpddr4_privatedata *pd, const lpddr4_eccenable *eccparam); 66 67 u32 (*getreducmode)(const lpddr4_privatedata *pd, lpddr4_reducmode *mode); 68 69 u32 (*setreducmode)(const lpddr4_privatedata *pd, const lpddr4_reducmode *mode); 70 71 u32 (*getdbireadmode)(const lpddr4_privatedata *pd, bool *on_off); 72 73 u32 (*getdbiwritemode)(const lpddr4_privatedata *pd, bool *on_off); 74 75 u32 (*setdbimode)(const lpddr4_privatedata *pd, const lpddr4_dbimode *mode); 76 77 u32 (*getrefreshrate)(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, u32 *tref, u32 *tras_max); 78 79 u32 (*setrefreshrate)(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref, const u32 *tras_max); 80 81 u32 (*refreshperchipselect)(const lpddr4_privatedata *pd, const u32 trefinterval); 82 } lpddr4_obj; 83 84 extern lpddr4_obj *lpddr4_getinstance(void); 85 86 #endif /* lpddr4_obj_if_h */ 87