1 /** @file
2 Private Header file for Usb Host Controller PEIM
3 
4 Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>
5 
6 This program and the accompanying materials
7 are licensed and made available under the terms and conditions
8 of the BSD License which accompanies this distribution.  The
9 full text of the license may be found at
10 http://opensource.org/licenses/bsd-license.php
11 
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
14 
15 **/
16 
17 #ifndef _RECOVERY_EHC_H_
18 #define _RECOVERY_EHC_H_
19 
20 #include <PiPei.h>
21 
22 #include <Ppi/UsbController.h>
23 #include <Ppi/Usb2HostController.h>
24 
25 #include <Library/DebugLib.h>
26 #include <Library/PeimEntryPoint.h>
27 #include <Library/PeiServicesLib.h>
28 #include <Library/BaseMemoryLib.h>
29 #include <Library/TimerLib.h>
30 #include <Library/IoLib.h>
31 
32 typedef struct _PEI_USB2_HC_DEV PEI_USB2_HC_DEV;
33 
34 #define EFI_LIST_ENTRY LIST_ENTRY
35 
36 #include "UsbHcMem.h"
37 #include "EhciReg.h"
38 #include "EhciUrb.h"
39 #include "EhciSched.h"
40 
41 #define EFI_USB_SPEED_FULL 0x0000
42 #define EFI_USB_SPEED_LOW  0x0001
43 #define EFI_USB_SPEED_HIGH 0x0002
44 
45 #define PAGESIZE           4096
46 
47 #define EHC_1_MICROSECOND            1
48 #define EHC_1_MILLISECOND            (1000 * EHC_1_MICROSECOND)
49 #define EHC_1_SECOND                 (1000 * EHC_1_MILLISECOND)
50 
51 //
52 // EHCI register operation timeout, set by experience
53 //
54 #define EHC_RESET_TIMEOUT            (1 * EHC_1_SECOND)
55 #define EHC_GENERIC_TIMEOUT          (10 * EHC_1_MILLISECOND)
56 
57 
58 //
59 // Wait for roothub port power stable, refers to Spec[EHCI1.0-2.3.9]
60 //
61 #define EHC_ROOT_PORT_RECOVERY_STALL (20 * EHC_1_MILLISECOND)
62 
63 //
64 // Sync and Async transfer polling interval, set by experience,
65 // and the unit of Async is 100us, means 50ms as interval.
66 //
67 #define EHC_SYNC_POLL_INTERVAL       (6 * EHC_1_MILLISECOND)
68 
69 #define EHC_ASYNC_POLL_INTERVAL      (50 * 10000U)
70 
71 //
72 //Iterate through the doule linked list. NOT delete safe
73 //
74 #define EFI_LIST_FOR_EACH(Entry, ListHead)    \
75   for(Entry = (ListHead)->ForwardLink; Entry != (ListHead); Entry = Entry->ForwardLink)
76 
77 //
78 //Iterate through the doule linked list. This is delete-safe.
79 //Don't touch NextEntry
80 //
81 #define EFI_LIST_FOR_EACH_SAFE(Entry, NextEntry, ListHead)            \
82   for(Entry = (ListHead)->ForwardLink, NextEntry = Entry->ForwardLink;\
83       Entry != (ListHead); Entry = NextEntry, NextEntry = Entry->ForwardLink)
84 
85 #define EFI_LIST_CONTAINER(Entry, Type, Field) BASE_CR(Entry, Type, Field)
86 
87 
88 #define EHC_LOW_32BIT(Addr64)     ((UINT32)(((UINTN)(Addr64)) & 0XFFFFFFFF))
89 #define EHC_HIGH_32BIT(Addr64)    ((UINT32)(RShiftU64((UINTN)(Addr64), 32) & 0XFFFFFFFF))
90 #define EHC_BIT_IS_SET(Data, Bit) ((BOOLEAN)(((Data) & (Bit)) == (Bit)))
91 
92 #define EHC_REG_BIT_IS_SET(Ehc, Offset, Bit) \
93           (EHC_BIT_IS_SET(EhcReadOpReg ((Ehc), (Offset)), (Bit)))
94 
95 #define USB2_HC_DEV_SIGNATURE  SIGNATURE_32 ('e', 'h', 'c', 'i')
96 
97 struct _PEI_USB2_HC_DEV {
98   UINTN                               Signature;
99   PEI_USB2_HOST_CONTROLLER_PPI        Usb2HostControllerPpi;
100   EFI_PEI_PPI_DESCRIPTOR              PpiDescriptor;
101   UINT32                              UsbHostControllerBaseAddress;
102   PEI_URB                             *Urb;
103   USBHC_MEM_POOL                      *MemPool;
104 
105   //
106   // Schedule data shared between asynchronous and periodic
107   // transfers:
108   // ShortReadStop, as its name indicates, is used to terminate
109   // the short read except the control transfer. EHCI follows
110   // the alternative next QTD point when a short read happens.
111   // For control transfer, even the short read happens, try the
112   // status stage.
113   //
114   PEI_EHC_QTD                         *ShortReadStop;
115   EFI_EVENT                           PollTimer;
116 
117   //
118   // Asynchronous(bulk and control) transfer schedule data:
119   // ReclaimHead is used as the head of the asynchronous transfer
120   // list. It acts as the reclamation header.
121   //
122   PEI_EHC_QH                          *ReclaimHead;
123 
124   //
125   // Peroidic (interrupt) transfer schedule data:
126   //
127   VOID                                *PeriodFrame;     // Mapped as common buffer
128   VOID                                *PeriodFrameHost;
129   VOID                                *PeriodFrameMap;
130 
131   PEI_EHC_QH                          *PeriodOne;
132   EFI_LIST_ENTRY                      AsyncIntTransfers;
133 
134   //
135   // EHCI configuration data
136   //
137   UINT32                              HcStructParams; // Cache of HC structure parameter, EHC_HCSPARAMS_OFFSET
138   UINT32                              HcCapParams;    // Cache of HC capability parameter, HCCPARAMS
139   UINT32                              CapLen;         // Capability length
140   UINT32                              High32bitAddr;
141 };
142 
143 #define PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS(a)  CR (a, PEI_USB2_HC_DEV, Usb2HostControllerPpi, USB2_HC_DEV_SIGNATURE)
144 
145 /**
146   @param  EhcDev                 EHCI Device.
147 
148   @retval EFI_SUCCESS            EHCI successfully initialized.
149   @retval EFI_ABORTED            EHCI was failed to be initialized.
150 
151 **/
152 EFI_STATUS
153 InitializeUsbHC (
154   IN PEI_USB2_HC_DEV      *EhcDev
155   );
156 
157 /**
158   Initialize the memory management pool for the host controller.
159 
160   @param  Ehc                   The EHCI device.
161   @param  Check4G               Whether the host controller requires allocated memory
162                                 from one 4G address space.
163   @param  Which4G               The 4G memory area each memory allocated should be from.
164 
165   @retval EFI_SUCCESS           The memory pool is initialized.
166   @retval EFI_OUT_OF_RESOURCE   Fail to init the memory pool.
167 
168 **/
169 USBHC_MEM_POOL *
170 UsbHcInitMemPool (
171   IN PEI_USB2_HC_DEV      *Ehc,
172   IN BOOLEAN              Check4G,
173   IN UINT32               Which4G
174   )
175 ;
176 
177 /**
178   Release the memory management pool.
179 
180   @param  Pool                  The USB memory pool to free.
181 
182   @retval EFI_DEVICE_ERROR      Fail to free the memory pool.
183   @retval EFI_SUCCESS           The memory pool is freed.
184 
185 **/
186 EFI_STATUS
187 UsbHcFreeMemPool (
188   IN USBHC_MEM_POOL       *Pool
189   )
190 ;
191 
192 /**
193   Allocate some memory from the host controller's memory pool
194   which can be used to communicate with host controller.
195 
196   @param  Ehc       The EHCI device.
197   @param  Pool      The host controller's memory pool.
198   @param  Size      Size of the memory to allocate.
199 
200   @return The allocated memory or NULL.
201 
202 **/
203 VOID *
204 UsbHcAllocateMem (
205   IN PEI_USB2_HC_DEV      *Ehc,
206   IN  USBHC_MEM_POOL      *Pool,
207   IN  UINTN               Size
208   )
209 ;
210 
211 /**
212   Free the allocated memory back to the memory pool.
213 
214   @param  Pool           The memory pool of the host controller.
215   @param  Mem            The memory to free.
216   @param  Size           The size of the memory to free.
217 
218 **/
219 VOID
220 UsbHcFreeMem (
221   IN USBHC_MEM_POOL       *Pool,
222   IN VOID                 *Mem,
223   IN UINTN                Size
224   )
225 ;
226 
227 #endif
228