1 /** @file 2 Private Header file for Usb Host Controller PEIM 3 4 Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.<BR> 5 Copyright (c) Microsoft Corporation.<BR> 6 7 SPDX-License-Identifier: BSD-2-Clause-Patent 8 9 **/ 10 11 #ifndef _RECOVERY_EHC_H_ 12 #define _RECOVERY_EHC_H_ 13 14 #include <PiPei.h> 15 16 #include <Ppi/UsbController.h> 17 #include <Ppi/Usb2HostController.h> 18 #include <Ppi/IoMmu.h> 19 #include <Ppi/EndOfPeiPhase.h> 20 21 #include <Library/BaseLib.h> 22 #include <Library/DebugLib.h> 23 #include <Library/PeimEntryPoint.h> 24 #include <Library/PeiServicesLib.h> 25 #include <Library/BaseMemoryLib.h> 26 #include <Library/TimerLib.h> 27 #include <Library/IoLib.h> 28 29 typedef struct _PEI_USB2_HC_DEV PEI_USB2_HC_DEV; 30 31 #define EFI_LIST_ENTRY LIST_ENTRY 32 33 #include "UsbHcMem.h" 34 #include "EhciReg.h" 35 #include "EhciUrb.h" 36 #include "EhciSched.h" 37 38 #define EFI_USB_SPEED_FULL 0x0000 39 #define EFI_USB_SPEED_LOW 0x0001 40 #define EFI_USB_SPEED_HIGH 0x0002 41 42 #define PAGESIZE 4096 43 44 #define EHC_1_MICROSECOND 1 45 #define EHC_1_MILLISECOND (1000 * EHC_1_MICROSECOND) 46 #define EHC_1_SECOND (1000 * EHC_1_MILLISECOND) 47 48 // 49 // EHCI register operation timeout, set by experience 50 // 51 #define EHC_RESET_TIMEOUT (1 * EHC_1_SECOND) 52 #define EHC_GENERIC_TIMEOUT (10 * EHC_1_MILLISECOND) 53 54 55 // 56 // Wait for roothub port power stable, refers to Spec[EHCI1.0-2.3.9] 57 // 58 #define EHC_ROOT_PORT_RECOVERY_STALL (20 * EHC_1_MILLISECOND) 59 60 // 61 // Sync transfer polling interval, set by experience. 62 // 63 #define EHC_SYNC_POLL_INTERVAL (6 * EHC_1_MILLISECOND) 64 65 #define EFI_LIST_CONTAINER(Entry, Type, Field) BASE_CR(Entry, Type, Field) 66 67 68 #define EHC_LOW_32BIT(Addr64) ((UINT32)(((UINTN)(Addr64)) & 0XFFFFFFFF)) 69 #define EHC_HIGH_32BIT(Addr64) ((UINT32)(RShiftU64((UINTN)(Addr64), 32) & 0XFFFFFFFF)) 70 #define EHC_BIT_IS_SET(Data, Bit) ((BOOLEAN)(((Data) & (Bit)) == (Bit))) 71 72 #define EHC_REG_BIT_IS_SET(Ehc, Offset, Bit) \ 73 (EHC_BIT_IS_SET(EhcReadOpReg ((Ehc), (Offset)), (Bit))) 74 75 #define USB2_HC_DEV_SIGNATURE SIGNATURE_32 ('e', 'h', 'c', 'i') 76 77 struct _PEI_USB2_HC_DEV { 78 UINTN Signature; 79 PEI_USB2_HOST_CONTROLLER_PPI Usb2HostControllerPpi; 80 EDKII_IOMMU_PPI *IoMmu; 81 EFI_PEI_PPI_DESCRIPTOR PpiDescriptor; 82 // 83 // EndOfPei callback is used to stop the EHC DMA operation 84 // after exit PEI phase. 85 // 86 EFI_PEI_NOTIFY_DESCRIPTOR EndOfPeiNotifyList; 87 UINT32 UsbHostControllerBaseAddress; 88 PEI_URB *Urb; 89 USBHC_MEM_POOL *MemPool; 90 91 // 92 // Schedule data shared between asynchronous and periodic 93 // transfers: 94 // ShortReadStop, as its name indicates, is used to terminate 95 // the short read except the control transfer. EHCI follows 96 // the alternative next QTD point when a short read happens. 97 // For control transfer, even the short read happens, try the 98 // status stage. 99 // 100 PEI_EHC_QTD *ShortReadStop; 101 EFI_EVENT PollTimer; 102 103 // 104 // Asynchronous(bulk and control) transfer schedule data: 105 // ReclaimHead is used as the head of the asynchronous transfer 106 // list. It acts as the reclamation header. 107 // 108 PEI_EHC_QH *ReclaimHead; 109 110 // 111 // Periodic (interrupt) transfer schedule data: 112 // 113 VOID *PeriodFrame; // Mapped as common buffer 114 VOID *PeriodFrameMap; 115 116 PEI_EHC_QH *PeriodOne; 117 EFI_LIST_ENTRY AsyncIntTransfers; 118 119 // 120 // EHCI configuration data 121 // 122 UINT32 HcStructParams; // Cache of HC structure parameter, EHC_HCSPARAMS_OFFSET 123 UINT32 HcCapParams; // Cache of HC capability parameter, HCCPARAMS 124 UINT32 CapLen; // Capability length 125 UINT32 High32bitAddr; 126 }; 127 128 #define PEI_RECOVERY_USB_EHC_DEV_FROM_EHCI_THIS(a) CR (a, PEI_USB2_HC_DEV, Usb2HostControllerPpi, USB2_HC_DEV_SIGNATURE) 129 #define PEI_RECOVERY_USB_EHC_DEV_FROM_THIS_NOTIFY(a) CR (a, PEI_USB2_HC_DEV, EndOfPeiNotifyList, USB2_HC_DEV_SIGNATURE) 130 131 /** 132 @param EhcDev EHCI Device. 133 134 @retval EFI_SUCCESS EHCI successfully initialized. 135 @retval EFI_ABORTED EHCI was failed to be initialized. 136 137 **/ 138 EFI_STATUS 139 InitializeUsbHC ( 140 IN PEI_USB2_HC_DEV *EhcDev 141 ); 142 143 /** 144 Initialize the memory management pool for the host controller. 145 146 @param Ehc The EHCI device. 147 @param Check4G Whether the host controller requires allocated memory 148 from one 4G address space. 149 @param Which4G The 4G memory area each memory allocated should be from. 150 151 @retval EFI_SUCCESS The memory pool is initialized. 152 @retval EFI_OUT_OF_RESOURCE Fail to init the memory pool. 153 154 **/ 155 USBHC_MEM_POOL * 156 UsbHcInitMemPool ( 157 IN PEI_USB2_HC_DEV *Ehc, 158 IN BOOLEAN Check4G, 159 IN UINT32 Which4G 160 ) 161 ; 162 163 /** 164 Release the memory management pool. 165 166 @param Ehc The EHCI device. 167 @param Pool The USB memory pool to free. 168 169 @retval EFI_DEVICE_ERROR Fail to free the memory pool. 170 @retval EFI_SUCCESS The memory pool is freed. 171 172 **/ 173 EFI_STATUS 174 UsbHcFreeMemPool ( 175 IN PEI_USB2_HC_DEV *Ehc, 176 IN USBHC_MEM_POOL *Pool 177 ) 178 ; 179 180 /** 181 Allocate some memory from the host controller's memory pool 182 which can be used to communicate with host controller. 183 184 @param Ehc The EHCI device. 185 @param Pool The host controller's memory pool. 186 @param Size Size of the memory to allocate. 187 188 @return The allocated memory or NULL. 189 190 **/ 191 VOID * 192 UsbHcAllocateMem ( 193 IN PEI_USB2_HC_DEV *Ehc, 194 IN USBHC_MEM_POOL *Pool, 195 IN UINTN Size 196 ) 197 ; 198 199 /** 200 Free the allocated memory back to the memory pool. 201 202 @param Ehc The EHCI device. 203 @param Pool The memory pool of the host controller. 204 @param Mem The memory to free. 205 @param Size The size of the memory to free. 206 207 **/ 208 VOID 209 UsbHcFreeMem ( 210 IN PEI_USB2_HC_DEV *Ehc, 211 IN USBHC_MEM_POOL *Pool, 212 IN VOID *Mem, 213 IN UINTN Size 214 ) 215 ; 216 217 /** 218 Provides the controller-specific addresses required to access system memory from a 219 DMA bus master. 220 221 @param IoMmu Pointer to IOMMU PPI. 222 @param Operation Indicates if the bus master is going to read or write to system memory. 223 @param HostAddress The system memory address to map to the PCI controller. 224 @param NumberOfBytes On input the number of bytes to map. On output the number of bytes 225 that were mapped. 226 @param DeviceAddress The resulting map address for the bus master PCI controller to use to 227 access the hosts HostAddress. 228 @param Mapping A resulting value to pass to Unmap(). 229 230 @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes. 231 @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer. 232 @retval EFI_INVALID_PARAMETER One or more parameters are invalid. 233 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources. 234 @retval EFI_DEVICE_ERROR The system hardware could not map the requested address. 235 236 **/ 237 EFI_STATUS 238 IoMmuMap ( 239 IN EDKII_IOMMU_PPI *IoMmu, 240 IN EDKII_IOMMU_OPERATION Operation, 241 IN VOID *HostAddress, 242 IN OUT UINTN *NumberOfBytes, 243 OUT EFI_PHYSICAL_ADDRESS *DeviceAddress, 244 OUT VOID **Mapping 245 ); 246 247 /** 248 Completes the Map() operation and releases any corresponding resources. 249 250 @param IoMmu Pointer to IOMMU PPI. 251 @param Mapping The mapping value returned from Map(). 252 253 **/ 254 VOID 255 IoMmuUnmap ( 256 IN EDKII_IOMMU_PPI *IoMmu, 257 IN VOID *Mapping 258 ); 259 260 /** 261 Allocates pages that are suitable for an OperationBusMasterCommonBuffer or 262 OperationBusMasterCommonBuffer64 mapping. 263 264 @param IoMmu Pointer to IOMMU PPI. 265 @param Pages The number of pages to allocate. 266 @param HostAddress A pointer to store the base system memory address of the 267 allocated range. 268 @param DeviceAddress The resulting map address for the bus master PCI controller to use to 269 access the hosts HostAddress. 270 @param Mapping A resulting value to pass to Unmap(). 271 272 @retval EFI_SUCCESS The requested memory pages were allocated. 273 @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are 274 MEMORY_WRITE_COMBINE and MEMORY_CACHED. 275 @retval EFI_INVALID_PARAMETER One or more parameters are invalid. 276 @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated. 277 278 **/ 279 EFI_STATUS 280 IoMmuAllocateBuffer ( 281 IN EDKII_IOMMU_PPI *IoMmu, 282 IN UINTN Pages, 283 OUT VOID **HostAddress, 284 OUT EFI_PHYSICAL_ADDRESS *DeviceAddress, 285 OUT VOID **Mapping 286 ); 287 288 /** 289 Frees memory that was allocated with AllocateBuffer(). 290 291 @param IoMmu Pointer to IOMMU PPI. 292 @param Pages The number of pages to free. 293 @param HostAddress The base system memory address of the allocated range. 294 @param Mapping The mapping value returned from Map(). 295 296 **/ 297 VOID 298 IoMmuFreeBuffer ( 299 IN EDKII_IOMMU_PPI *IoMmu, 300 IN UINTN Pages, 301 IN VOID *HostAddress, 302 IN VOID *Mapping 303 ); 304 305 /** 306 Initialize IOMMU. 307 308 @param IoMmu Pointer to pointer to IOMMU PPI. 309 310 **/ 311 VOID 312 IoMmuInit ( 313 OUT EDKII_IOMMU_PPI **IoMmu 314 ); 315 316 #endif 317