1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
2 // RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
3 // RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
4
5 #include <arm_mve.h>
6
7 // CHECK-LABEL: @test_vcaddq_rot90_u8(
8 // CHECK-NEXT: entry:
9 // CHECK-NEXT: [[TMP0:%.*]] = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 1, i32 0, <16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]])
10 // CHECK-NEXT: ret <16 x i8> [[TMP0]]
11 //
test_vcaddq_rot90_u8(uint8x16_t a,uint8x16_t b)12 uint8x16_t test_vcaddq_rot90_u8(uint8x16_t a, uint8x16_t b)
13 {
14 #ifdef POLYMORPHIC
15 return vcaddq_rot90(a, b);
16 #else
17 return vcaddq_rot90_u8(a, b);
18 #endif
19 }
20
21 // CHECK-LABEL: @test_vcaddq_rot90_u16(
22 // CHECK-NEXT: entry:
23 // CHECK-NEXT: [[TMP0:%.*]] = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 1, i32 0, <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]])
24 // CHECK-NEXT: ret <8 x i16> [[TMP0]]
25 //
test_vcaddq_rot90_u16(uint16x8_t a,uint16x8_t b)26 uint16x8_t test_vcaddq_rot90_u16(uint16x8_t a, uint16x8_t b)
27 {
28 #ifdef POLYMORPHIC
29 return vcaddq_rot90(a, b);
30 #else
31 return vcaddq_rot90_u16(a, b);
32 #endif
33 }
34
35 // CHECK-LABEL: @test_vcaddq_rot90_u32(
36 // CHECK-NEXT: entry:
37 // CHECK-NEXT: [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 1, i32 0, <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]])
38 // CHECK-NEXT: ret <4 x i32> [[TMP0]]
39 //
test_vcaddq_rot90_u32(uint32x4_t a,uint32x4_t b)40 uint32x4_t test_vcaddq_rot90_u32(uint32x4_t a, uint32x4_t b)
41 {
42 #ifdef POLYMORPHIC
43 return vcaddq_rot90(a, b);
44 #else
45 return vcaddq_rot90_u32(a, b);
46 #endif
47 }
48
49 // CHECK-LABEL: @test_vcaddq_rot90_s8(
50 // CHECK-NEXT: entry:
51 // CHECK-NEXT: [[TMP0:%.*]] = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 1, i32 0, <16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]])
52 // CHECK-NEXT: ret <16 x i8> [[TMP0]]
53 //
test_vcaddq_rot90_s8(int8x16_t a,int8x16_t b)54 int8x16_t test_vcaddq_rot90_s8(int8x16_t a, int8x16_t b)
55 {
56 #ifdef POLYMORPHIC
57 return vcaddq_rot90(a, b);
58 #else
59 return vcaddq_rot90_s8(a, b);
60 #endif
61 }
62
63 // CHECK-LABEL: @test_vcaddq_rot90_s16(
64 // CHECK-NEXT: entry:
65 // CHECK-NEXT: [[TMP0:%.*]] = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 1, i32 0, <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]])
66 // CHECK-NEXT: ret <8 x i16> [[TMP0]]
67 //
test_vcaddq_rot90_s16(int16x8_t a,int16x8_t b)68 int16x8_t test_vcaddq_rot90_s16(int16x8_t a, int16x8_t b)
69 {
70 #ifdef POLYMORPHIC
71 return vcaddq_rot90(a, b);
72 #else
73 return vcaddq_rot90_s16(a, b);
74 #endif
75 }
76
77 // CHECK-LABEL: @test_vcaddq_rot90_s32(
78 // CHECK-NEXT: entry:
79 // CHECK-NEXT: [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 1, i32 0, <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]])
80 // CHECK-NEXT: ret <4 x i32> [[TMP0]]
81 //
test_vcaddq_rot90_s32(int32x4_t a,int32x4_t b)82 int32x4_t test_vcaddq_rot90_s32(int32x4_t a, int32x4_t b)
83 {
84 #ifdef POLYMORPHIC
85 return vcaddq_rot90(a, b);
86 #else
87 return vcaddq_rot90_s32(a, b);
88 #endif
89 }
90
91 // CHECK-LABEL: @test_vcaddq_rot90_f16(
92 // CHECK-NEXT: entry:
93 // CHECK-NEXT: [[TMP0:%.*]] = call <8 x half> @llvm.arm.mve.vcaddq.v8f16(i32 1, i32 0, <8 x half> [[A:%.*]], <8 x half> [[B:%.*]])
94 // CHECK-NEXT: ret <8 x half> [[TMP0]]
95 //
test_vcaddq_rot90_f16(float16x8_t a,float16x8_t b)96 float16x8_t test_vcaddq_rot90_f16(float16x8_t a, float16x8_t b)
97 {
98 #ifdef POLYMORPHIC
99 return vcaddq_rot90(a, b);
100 #else
101 return vcaddq_rot90_f16(a, b);
102 #endif
103 }
104
105 // CHECK-LABEL: @test_vcaddq_rot90_f32(
106 // CHECK-NEXT: entry:
107 // CHECK-NEXT: [[TMP0:%.*]] = call <4 x float> @llvm.arm.mve.vcaddq.v4f32(i32 1, i32 0, <4 x float> [[A:%.*]], <4 x float> [[B:%.*]])
108 // CHECK-NEXT: ret <4 x float> [[TMP0]]
109 //
test_vcaddq_rot90_f32(float32x4_t a,float32x4_t b)110 float32x4_t test_vcaddq_rot90_f32(float32x4_t a, float32x4_t b)
111 {
112 #ifdef POLYMORPHIC
113 return vcaddq_rot90(a, b);
114 #else
115 return vcaddq_rot90_f32(a, b);
116 #endif
117 }
118
119 // CHECK-LABEL: @test_vcaddq_rot270_u8(
120 // CHECK-NEXT: entry:
121 // CHECK-NEXT: [[TMP0:%.*]] = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 1, i32 1, <16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]])
122 // CHECK-NEXT: ret <16 x i8> [[TMP0]]
123 //
test_vcaddq_rot270_u8(uint8x16_t a,uint8x16_t b)124 uint8x16_t test_vcaddq_rot270_u8(uint8x16_t a, uint8x16_t b)
125 {
126 #ifdef POLYMORPHIC
127 return vcaddq_rot270(a, b);
128 #else
129 return vcaddq_rot270_u8(a, b);
130 #endif
131 }
132
133 // CHECK-LABEL: @test_vcaddq_rot270_u16(
134 // CHECK-NEXT: entry:
135 // CHECK-NEXT: [[TMP0:%.*]] = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 1, i32 1, <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]])
136 // CHECK-NEXT: ret <8 x i16> [[TMP0]]
137 //
test_vcaddq_rot270_u16(uint16x8_t a,uint16x8_t b)138 uint16x8_t test_vcaddq_rot270_u16(uint16x8_t a, uint16x8_t b)
139 {
140 #ifdef POLYMORPHIC
141 return vcaddq_rot270(a, b);
142 #else
143 return vcaddq_rot270_u16(a, b);
144 #endif
145 }
146
147 // CHECK-LABEL: @test_vcaddq_rot270_u32(
148 // CHECK-NEXT: entry:
149 // CHECK-NEXT: [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 1, i32 1, <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]])
150 // CHECK-NEXT: ret <4 x i32> [[TMP0]]
151 //
test_vcaddq_rot270_u32(uint32x4_t a,uint32x4_t b)152 uint32x4_t test_vcaddq_rot270_u32(uint32x4_t a, uint32x4_t b)
153 {
154 #ifdef POLYMORPHIC
155 return vcaddq_rot270(a, b);
156 #else
157 return vcaddq_rot270_u32(a, b);
158 #endif
159 }
160
161 // CHECK-LABEL: @test_vcaddq_rot270_s8(
162 // CHECK-NEXT: entry:
163 // CHECK-NEXT: [[TMP0:%.*]] = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 1, i32 1, <16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]])
164 // CHECK-NEXT: ret <16 x i8> [[TMP0]]
165 //
test_vcaddq_rot270_s8(int8x16_t a,int8x16_t b)166 int8x16_t test_vcaddq_rot270_s8(int8x16_t a, int8x16_t b)
167 {
168 #ifdef POLYMORPHIC
169 return vcaddq_rot270(a, b);
170 #else
171 return vcaddq_rot270_s8(a, b);
172 #endif
173 }
174
175 // CHECK-LABEL: @test_vcaddq_rot270_s16(
176 // CHECK-NEXT: entry:
177 // CHECK-NEXT: [[TMP0:%.*]] = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 1, i32 1, <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]])
178 // CHECK-NEXT: ret <8 x i16> [[TMP0]]
179 //
test_vcaddq_rot270_s16(int16x8_t a,int16x8_t b)180 int16x8_t test_vcaddq_rot270_s16(int16x8_t a, int16x8_t b)
181 {
182 #ifdef POLYMORPHIC
183 return vcaddq_rot270(a, b);
184 #else
185 return vcaddq_rot270_s16(a, b);
186 #endif
187 }
188
189 // CHECK-LABEL: @test_vcaddq_rot270_s32(
190 // CHECK-NEXT: entry:
191 // CHECK-NEXT: [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 1, i32 1, <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]])
192 // CHECK-NEXT: ret <4 x i32> [[TMP0]]
193 //
test_vcaddq_rot270_s32(int32x4_t a,int32x4_t b)194 int32x4_t test_vcaddq_rot270_s32(int32x4_t a, int32x4_t b)
195 {
196 #ifdef POLYMORPHIC
197 return vcaddq_rot270(a, b);
198 #else
199 return vcaddq_rot270_s32(a, b);
200 #endif
201 }
202
203 // CHECK-LABEL: @test_vcaddq_rot270_f16(
204 // CHECK-NEXT: entry:
205 // CHECK-NEXT: [[TMP0:%.*]] = call <8 x half> @llvm.arm.mve.vcaddq.v8f16(i32 1, i32 1, <8 x half> [[A:%.*]], <8 x half> [[B:%.*]])
206 // CHECK-NEXT: ret <8 x half> [[TMP0]]
207 //
test_vcaddq_rot270_f16(float16x8_t a,float16x8_t b)208 float16x8_t test_vcaddq_rot270_f16(float16x8_t a, float16x8_t b)
209 {
210 #ifdef POLYMORPHIC
211 return vcaddq_rot270(a, b);
212 #else
213 return vcaddq_rot270_f16(a, b);
214 #endif
215 }
216
217 // CHECK-LABEL: @test_vcaddq_rot270_f32(
218 // CHECK-NEXT: entry:
219 // CHECK-NEXT: [[TMP0:%.*]] = call <4 x float> @llvm.arm.mve.vcaddq.v4f32(i32 1, i32 1, <4 x float> [[A:%.*]], <4 x float> [[B:%.*]])
220 // CHECK-NEXT: ret <4 x float> [[TMP0]]
221 //
test_vcaddq_rot270_f32(float32x4_t a,float32x4_t b)222 float32x4_t test_vcaddq_rot270_f32(float32x4_t a, float32x4_t b)
223 {
224 #ifdef POLYMORPHIC
225 return vcaddq_rot270(a, b);
226 #else
227 return vcaddq_rot270_f32(a, b);
228 #endif
229 }
230
231
232 // CHECK-LABEL: @test_vcaddq_rot90_m_u8(
233 // CHECK-NEXT: entry:
234 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
235 // CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])
236 // CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 1, i32 0, <16 x i8> [[INACTIVE:%.*]], <16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], <16 x i1> [[TMP1]])
237 // CHECK-NEXT: ret <16 x i8> [[TMP2]]
238 //
test_vcaddq_rot90_m_u8(uint8x16_t inactive,uint8x16_t a,uint8x16_t b,mve_pred16_t p)239 uint8x16_t test_vcaddq_rot90_m_u8(uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
240 {
241 #ifdef POLYMORPHIC
242 return vcaddq_rot90_m(inactive, a, b, p);
243 #else
244 return vcaddq_rot90_m_u8(inactive, a, b, p);
245 #endif
246 }
247
248 // CHECK-LABEL: @test_vcaddq_rot90_m_u16(
249 // CHECK-NEXT: entry:
250 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
251 // CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
252 // CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 1, i32 0, <8 x i16> [[INACTIVE:%.*]], <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], <8 x i1> [[TMP1]])
253 // CHECK-NEXT: ret <8 x i16> [[TMP2]]
254 //
test_vcaddq_rot90_m_u16(uint16x8_t inactive,uint16x8_t a,uint16x8_t b,mve_pred16_t p)255 uint16x8_t test_vcaddq_rot90_m_u16(uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
256 {
257 #ifdef POLYMORPHIC
258 return vcaddq_rot90_m(inactive, a, b, p);
259 #else
260 return vcaddq_rot90_m_u16(inactive, a, b, p);
261 #endif
262 }
263
264 // CHECK-LABEL: @test_vcaddq_rot90_m_u32(
265 // CHECK-NEXT: entry:
266 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
267 // CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
268 // CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 1, i32 0, <4 x i32> [[INACTIVE:%.*]], <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i1> [[TMP1]])
269 // CHECK-NEXT: ret <4 x i32> [[TMP2]]
270 //
test_vcaddq_rot90_m_u32(uint32x4_t inactive,uint32x4_t a,uint32x4_t b,mve_pred16_t p)271 uint32x4_t test_vcaddq_rot90_m_u32(uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
272 {
273 #ifdef POLYMORPHIC
274 return vcaddq_rot90_m(inactive, a, b, p);
275 #else
276 return vcaddq_rot90_m_u32(inactive, a, b, p);
277 #endif
278 }
279
280 // CHECK-LABEL: @test_vcaddq_rot90_m_s8(
281 // CHECK-NEXT: entry:
282 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
283 // CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])
284 // CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 1, i32 0, <16 x i8> [[INACTIVE:%.*]], <16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], <16 x i1> [[TMP1]])
285 // CHECK-NEXT: ret <16 x i8> [[TMP2]]
286 //
test_vcaddq_rot90_m_s8(int8x16_t inactive,int8x16_t a,int8x16_t b,mve_pred16_t p)287 int8x16_t test_vcaddq_rot90_m_s8(int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
288 {
289 #ifdef POLYMORPHIC
290 return vcaddq_rot90_m(inactive, a, b, p);
291 #else
292 return vcaddq_rot90_m_s8(inactive, a, b, p);
293 #endif
294 }
295
296 // CHECK-LABEL: @test_vcaddq_rot90_m_s16(
297 // CHECK-NEXT: entry:
298 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
299 // CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
300 // CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 1, i32 0, <8 x i16> [[INACTIVE:%.*]], <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], <8 x i1> [[TMP1]])
301 // CHECK-NEXT: ret <8 x i16> [[TMP2]]
302 //
test_vcaddq_rot90_m_s16(int16x8_t inactive,int16x8_t a,int16x8_t b,mve_pred16_t p)303 int16x8_t test_vcaddq_rot90_m_s16(int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
304 {
305 #ifdef POLYMORPHIC
306 return vcaddq_rot90_m(inactive, a, b, p);
307 #else
308 return vcaddq_rot90_m_s16(inactive, a, b, p);
309 #endif
310 }
311
312 // CHECK-LABEL: @test_vcaddq_rot90_m_s32(
313 // CHECK-NEXT: entry:
314 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
315 // CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
316 // CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 1, i32 0, <4 x i32> [[INACTIVE:%.*]], <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i1> [[TMP1]])
317 // CHECK-NEXT: ret <4 x i32> [[TMP2]]
318 //
test_vcaddq_rot90_m_s32(int32x4_t inactive,int32x4_t a,int32x4_t b,mve_pred16_t p)319 int32x4_t test_vcaddq_rot90_m_s32(int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
320 {
321 #ifdef POLYMORPHIC
322 return vcaddq_rot90_m(inactive, a, b, p);
323 #else
324 return vcaddq_rot90_m_s32(inactive, a, b, p);
325 #endif
326 }
327
328 // CHECK-LABEL: @test_vcaddq_rot90_m_f16(
329 // CHECK-NEXT: entry:
330 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
331 // CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
332 // CHECK-NEXT: [[TMP2:%.*]] = call <8 x half> @llvm.arm.mve.vcaddq.predicated.v8f16.v8i1(i32 1, i32 0, <8 x half> [[INACTIVE:%.*]], <8 x half> [[A:%.*]], <8 x half> [[B:%.*]], <8 x i1> [[TMP1]])
333 // CHECK-NEXT: ret <8 x half> [[TMP2]]
334 //
test_vcaddq_rot90_m_f16(float16x8_t inactive,float16x8_t a,float16x8_t b,mve_pred16_t p)335 float16x8_t test_vcaddq_rot90_m_f16(float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
336 {
337 #ifdef POLYMORPHIC
338 return vcaddq_rot90_m(inactive, a, b, p);
339 #else
340 return vcaddq_rot90_m_f16(inactive, a, b, p);
341 #endif
342 }
343
344 // CHECK-LABEL: @test_vcaddq_rot90_m_f32(
345 // CHECK-NEXT: entry:
346 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
347 // CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
348 // CHECK-NEXT: [[TMP2:%.*]] = call <4 x float> @llvm.arm.mve.vcaddq.predicated.v4f32.v4i1(i32 1, i32 0, <4 x float> [[INACTIVE:%.*]], <4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x i1> [[TMP1]])
349 // CHECK-NEXT: ret <4 x float> [[TMP2]]
350 //
test_vcaddq_rot90_m_f32(float32x4_t inactive,float32x4_t a,float32x4_t b,mve_pred16_t p)351 float32x4_t test_vcaddq_rot90_m_f32(float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
352 {
353 #ifdef POLYMORPHIC
354 return vcaddq_rot90_m(inactive, a, b, p);
355 #else
356 return vcaddq_rot90_m_f32(inactive, a, b, p);
357 #endif
358 }
359
360 // CHECK-LABEL: @test_vcaddq_rot270_m_u8(
361 // CHECK-NEXT: entry:
362 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
363 // CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])
364 // CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 1, i32 1, <16 x i8> [[INACTIVE:%.*]], <16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], <16 x i1> [[TMP1]])
365 // CHECK-NEXT: ret <16 x i8> [[TMP2]]
366 //
test_vcaddq_rot270_m_u8(uint8x16_t inactive,uint8x16_t a,uint8x16_t b,mve_pred16_t p)367 uint8x16_t test_vcaddq_rot270_m_u8(uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
368 {
369 #ifdef POLYMORPHIC
370 return vcaddq_rot270_m(inactive, a, b, p);
371 #else
372 return vcaddq_rot270_m_u8(inactive, a, b, p);
373 #endif
374 }
375
376 // CHECK-LABEL: @test_vcaddq_rot270_m_u16(
377 // CHECK-NEXT: entry:
378 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
379 // CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
380 // CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 1, i32 1, <8 x i16> [[INACTIVE:%.*]], <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], <8 x i1> [[TMP1]])
381 // CHECK-NEXT: ret <8 x i16> [[TMP2]]
382 //
test_vcaddq_rot270_m_u16(uint16x8_t inactive,uint16x8_t a,uint16x8_t b,mve_pred16_t p)383 uint16x8_t test_vcaddq_rot270_m_u16(uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
384 {
385 #ifdef POLYMORPHIC
386 return vcaddq_rot270_m(inactive, a, b, p);
387 #else
388 return vcaddq_rot270_m_u16(inactive, a, b, p);
389 #endif
390 }
391
392 // CHECK-LABEL: @test_vcaddq_rot270_m_u32(
393 // CHECK-NEXT: entry:
394 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
395 // CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
396 // CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 1, i32 1, <4 x i32> [[INACTIVE:%.*]], <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i1> [[TMP1]])
397 // CHECK-NEXT: ret <4 x i32> [[TMP2]]
398 //
test_vcaddq_rot270_m_u32(uint32x4_t inactive,uint32x4_t a,uint32x4_t b,mve_pred16_t p)399 uint32x4_t test_vcaddq_rot270_m_u32(uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
400 {
401 #ifdef POLYMORPHIC
402 return vcaddq_rot270_m(inactive, a, b, p);
403 #else
404 return vcaddq_rot270_m_u32(inactive, a, b, p);
405 #endif
406 }
407
408 // CHECK-LABEL: @test_vcaddq_rot270_m_s8(
409 // CHECK-NEXT: entry:
410 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
411 // CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])
412 // CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 1, i32 1, <16 x i8> [[INACTIVE:%.*]], <16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], <16 x i1> [[TMP1]])
413 // CHECK-NEXT: ret <16 x i8> [[TMP2]]
414 //
test_vcaddq_rot270_m_s8(int8x16_t inactive,int8x16_t a,int8x16_t b,mve_pred16_t p)415 int8x16_t test_vcaddq_rot270_m_s8(int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
416 {
417 #ifdef POLYMORPHIC
418 return vcaddq_rot270_m(inactive, a, b, p);
419 #else
420 return vcaddq_rot270_m_s8(inactive, a, b, p);
421 #endif
422 }
423
424 // CHECK-LABEL: @test_vcaddq_rot270_m_s16(
425 // CHECK-NEXT: entry:
426 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
427 // CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
428 // CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 1, i32 1, <8 x i16> [[INACTIVE:%.*]], <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], <8 x i1> [[TMP1]])
429 // CHECK-NEXT: ret <8 x i16> [[TMP2]]
430 //
test_vcaddq_rot270_m_s16(int16x8_t inactive,int16x8_t a,int16x8_t b,mve_pred16_t p)431 int16x8_t test_vcaddq_rot270_m_s16(int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
432 {
433 #ifdef POLYMORPHIC
434 return vcaddq_rot270_m(inactive, a, b, p);
435 #else
436 return vcaddq_rot270_m_s16(inactive, a, b, p);
437 #endif
438 }
439
440 // CHECK-LABEL: @test_vcaddq_rot270_m_s32(
441 // CHECK-NEXT: entry:
442 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
443 // CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
444 // CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 1, i32 1, <4 x i32> [[INACTIVE:%.*]], <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i1> [[TMP1]])
445 // CHECK-NEXT: ret <4 x i32> [[TMP2]]
446 //
test_vcaddq_rot270_m_s32(int32x4_t inactive,int32x4_t a,int32x4_t b,mve_pred16_t p)447 int32x4_t test_vcaddq_rot270_m_s32(int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
448 {
449 #ifdef POLYMORPHIC
450 return vcaddq_rot270_m(inactive, a, b, p);
451 #else
452 return vcaddq_rot270_m_s32(inactive, a, b, p);
453 #endif
454 }
455
456 // CHECK-LABEL: @test_vcaddq_rot270_m_f16(
457 // CHECK-NEXT: entry:
458 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
459 // CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
460 // CHECK-NEXT: [[TMP2:%.*]] = call <8 x half> @llvm.arm.mve.vcaddq.predicated.v8f16.v8i1(i32 1, i32 1, <8 x half> [[INACTIVE:%.*]], <8 x half> [[A:%.*]], <8 x half> [[B:%.*]], <8 x i1> [[TMP1]])
461 // CHECK-NEXT: ret <8 x half> [[TMP2]]
462 //
test_vcaddq_rot270_m_f16(float16x8_t inactive,float16x8_t a,float16x8_t b,mve_pred16_t p)463 float16x8_t test_vcaddq_rot270_m_f16(float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
464 {
465 #ifdef POLYMORPHIC
466 return vcaddq_rot270_m(inactive, a, b, p);
467 #else
468 return vcaddq_rot270_m_f16(inactive, a, b, p);
469 #endif
470 }
471
472 // CHECK-LABEL: @test_vcaddq_rot270_m_f32(
473 // CHECK-NEXT: entry:
474 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
475 // CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
476 // CHECK-NEXT: [[TMP2:%.*]] = call <4 x float> @llvm.arm.mve.vcaddq.predicated.v4f32.v4i1(i32 1, i32 1, <4 x float> [[INACTIVE:%.*]], <4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x i1> [[TMP1]])
477 // CHECK-NEXT: ret <4 x float> [[TMP2]]
478 //
test_vcaddq_rot270_m_f32(float32x4_t inactive,float32x4_t a,float32x4_t b,mve_pred16_t p)479 float32x4_t test_vcaddq_rot270_m_f32(float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
480 {
481 #ifdef POLYMORPHIC
482 return vcaddq_rot270_m(inactive, a, b, p);
483 #else
484 return vcaddq_rot270_m_f32(inactive, a, b, p);
485 #endif
486 }
487
488 // CHECK-LABEL: @test_vcaddq_rot90_x_u8(
489 // CHECK-NEXT: entry:
490 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
491 // CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])
492 // CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 1, i32 0, <16 x i8> undef, <16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], <16 x i1> [[TMP1]])
493 // CHECK-NEXT: ret <16 x i8> [[TMP2]]
494 //
test_vcaddq_rot90_x_u8(uint8x16_t a,uint8x16_t b,mve_pred16_t p)495 uint8x16_t test_vcaddq_rot90_x_u8(uint8x16_t a, uint8x16_t b, mve_pred16_t p)
496 {
497 #ifdef POLYMORPHIC
498 return vcaddq_rot90_x(a, b, p);
499 #else
500 return vcaddq_rot90_x_u8(a, b, p);
501 #endif
502 }
503
504 // CHECK-LABEL: @test_vcaddq_rot90_x_u16(
505 // CHECK-NEXT: entry:
506 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
507 // CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
508 // CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 1, i32 0, <8 x i16> undef, <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], <8 x i1> [[TMP1]])
509 // CHECK-NEXT: ret <8 x i16> [[TMP2]]
510 //
test_vcaddq_rot90_x_u16(uint16x8_t a,uint16x8_t b,mve_pred16_t p)511 uint16x8_t test_vcaddq_rot90_x_u16(uint16x8_t a, uint16x8_t b, mve_pred16_t p)
512 {
513 #ifdef POLYMORPHIC
514 return vcaddq_rot90_x(a, b, p);
515 #else
516 return vcaddq_rot90_x_u16(a, b, p);
517 #endif
518 }
519
520 // CHECK-LABEL: @test_vcaddq_rot90_x_u32(
521 // CHECK-NEXT: entry:
522 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
523 // CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
524 // CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 1, i32 0, <4 x i32> undef, <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i1> [[TMP1]])
525 // CHECK-NEXT: ret <4 x i32> [[TMP2]]
526 //
test_vcaddq_rot90_x_u32(uint32x4_t a,uint32x4_t b,mve_pred16_t p)527 uint32x4_t test_vcaddq_rot90_x_u32(uint32x4_t a, uint32x4_t b, mve_pred16_t p)
528 {
529 #ifdef POLYMORPHIC
530 return vcaddq_rot90_x(a, b, p);
531 #else
532 return vcaddq_rot90_x_u32(a, b, p);
533 #endif
534 }
535
536 // CHECK-LABEL: @test_vcaddq_rot90_x_s8(
537 // CHECK-NEXT: entry:
538 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
539 // CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])
540 // CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 1, i32 0, <16 x i8> undef, <16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], <16 x i1> [[TMP1]])
541 // CHECK-NEXT: ret <16 x i8> [[TMP2]]
542 //
test_vcaddq_rot90_x_s8(int8x16_t a,int8x16_t b,mve_pred16_t p)543 int8x16_t test_vcaddq_rot90_x_s8(int8x16_t a, int8x16_t b, mve_pred16_t p)
544 {
545 #ifdef POLYMORPHIC
546 return vcaddq_rot90_x(a, b, p);
547 #else
548 return vcaddq_rot90_x_s8(a, b, p);
549 #endif
550 }
551
552 // CHECK-LABEL: @test_vcaddq_rot90_x_s16(
553 // CHECK-NEXT: entry:
554 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
555 // CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
556 // CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 1, i32 0, <8 x i16> undef, <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], <8 x i1> [[TMP1]])
557 // CHECK-NEXT: ret <8 x i16> [[TMP2]]
558 //
test_vcaddq_rot90_x_s16(int16x8_t a,int16x8_t b,mve_pred16_t p)559 int16x8_t test_vcaddq_rot90_x_s16(int16x8_t a, int16x8_t b, mve_pred16_t p)
560 {
561 #ifdef POLYMORPHIC
562 return vcaddq_rot90_x(a, b, p);
563 #else
564 return vcaddq_rot90_x_s16(a, b, p);
565 #endif
566 }
567
568 // CHECK-LABEL: @test_vcaddq_rot90_x_s32(
569 // CHECK-NEXT: entry:
570 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
571 // CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
572 // CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 1, i32 0, <4 x i32> undef, <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i1> [[TMP1]])
573 // CHECK-NEXT: ret <4 x i32> [[TMP2]]
574 //
test_vcaddq_rot90_x_s32(int32x4_t a,int32x4_t b,mve_pred16_t p)575 int32x4_t test_vcaddq_rot90_x_s32(int32x4_t a, int32x4_t b, mve_pred16_t p)
576 {
577 #ifdef POLYMORPHIC
578 return vcaddq_rot90_x(a, b, p);
579 #else
580 return vcaddq_rot90_x_s32(a, b, p);
581 #endif
582 }
583
584 // CHECK-LABEL: @test_vcaddq_rot90_x_f16(
585 // CHECK-NEXT: entry:
586 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
587 // CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
588 // CHECK-NEXT: [[TMP2:%.*]] = call <8 x half> @llvm.arm.mve.vcaddq.predicated.v8f16.v8i1(i32 1, i32 0, <8 x half> undef, <8 x half> [[A:%.*]], <8 x half> [[B:%.*]], <8 x i1> [[TMP1]])
589 // CHECK-NEXT: ret <8 x half> [[TMP2]]
590 //
test_vcaddq_rot90_x_f16(float16x8_t a,float16x8_t b,mve_pred16_t p)591 float16x8_t test_vcaddq_rot90_x_f16(float16x8_t a, float16x8_t b, mve_pred16_t p)
592 {
593 #ifdef POLYMORPHIC
594 return vcaddq_rot90_x(a, b, p);
595 #else
596 return vcaddq_rot90_x_f16(a, b, p);
597 #endif
598 }
599
600 // CHECK-LABEL: @test_vcaddq_rot90_x_f32(
601 // CHECK-NEXT: entry:
602 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
603 // CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
604 // CHECK-NEXT: [[TMP2:%.*]] = call <4 x float> @llvm.arm.mve.vcaddq.predicated.v4f32.v4i1(i32 1, i32 0, <4 x float> undef, <4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x i1> [[TMP1]])
605 // CHECK-NEXT: ret <4 x float> [[TMP2]]
606 //
test_vcaddq_rot90_x_f32(float32x4_t a,float32x4_t b,mve_pred16_t p)607 float32x4_t test_vcaddq_rot90_x_f32(float32x4_t a, float32x4_t b, mve_pred16_t p)
608 {
609 #ifdef POLYMORPHIC
610 return vcaddq_rot90_x(a, b, p);
611 #else
612 return vcaddq_rot90_x_f32(a, b, p);
613 #endif
614 }
615
616 // CHECK-LABEL: @test_vcaddq_rot270_x_u8(
617 // CHECK-NEXT: entry:
618 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
619 // CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])
620 // CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 1, i32 1, <16 x i8> undef, <16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], <16 x i1> [[TMP1]])
621 // CHECK-NEXT: ret <16 x i8> [[TMP2]]
622 //
test_vcaddq_rot270_x_u8(uint8x16_t a,uint8x16_t b,mve_pred16_t p)623 uint8x16_t test_vcaddq_rot270_x_u8(uint8x16_t a, uint8x16_t b, mve_pred16_t p)
624 {
625 #ifdef POLYMORPHIC
626 return vcaddq_rot270_x(a, b, p);
627 #else
628 return vcaddq_rot270_x_u8(a, b, p);
629 #endif
630 }
631
632 // CHECK-LABEL: @test_vcaddq_rot270_x_u16(
633 // CHECK-NEXT: entry:
634 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
635 // CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
636 // CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 1, i32 1, <8 x i16> undef, <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], <8 x i1> [[TMP1]])
637 // CHECK-NEXT: ret <8 x i16> [[TMP2]]
638 //
test_vcaddq_rot270_x_u16(uint16x8_t a,uint16x8_t b,mve_pred16_t p)639 uint16x8_t test_vcaddq_rot270_x_u16(uint16x8_t a, uint16x8_t b, mve_pred16_t p)
640 {
641 #ifdef POLYMORPHIC
642 return vcaddq_rot270_x(a, b, p);
643 #else
644 return vcaddq_rot270_x_u16(a, b, p);
645 #endif
646 }
647
648 // CHECK-LABEL: @test_vcaddq_rot270_x_u32(
649 // CHECK-NEXT: entry:
650 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
651 // CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
652 // CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 1, i32 1, <4 x i32> undef, <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i1> [[TMP1]])
653 // CHECK-NEXT: ret <4 x i32> [[TMP2]]
654 //
test_vcaddq_rot270_x_u32(uint32x4_t a,uint32x4_t b,mve_pred16_t p)655 uint32x4_t test_vcaddq_rot270_x_u32(uint32x4_t a, uint32x4_t b, mve_pred16_t p)
656 {
657 #ifdef POLYMORPHIC
658 return vcaddq_rot270_x(a, b, p);
659 #else
660 return vcaddq_rot270_x_u32(a, b, p);
661 #endif
662 }
663
664 // CHECK-LABEL: @test_vcaddq_rot270_x_s8(
665 // CHECK-NEXT: entry:
666 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
667 // CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])
668 // CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 1, i32 1, <16 x i8> undef, <16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], <16 x i1> [[TMP1]])
669 // CHECK-NEXT: ret <16 x i8> [[TMP2]]
670 //
test_vcaddq_rot270_x_s8(int8x16_t a,int8x16_t b,mve_pred16_t p)671 int8x16_t test_vcaddq_rot270_x_s8(int8x16_t a, int8x16_t b, mve_pred16_t p)
672 {
673 #ifdef POLYMORPHIC
674 return vcaddq_rot270_x(a, b, p);
675 #else
676 return vcaddq_rot270_x_s8(a, b, p);
677 #endif
678 }
679
680 // CHECK-LABEL: @test_vcaddq_rot270_x_s16(
681 // CHECK-NEXT: entry:
682 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
683 // CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
684 // CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 1, i32 1, <8 x i16> undef, <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], <8 x i1> [[TMP1]])
685 // CHECK-NEXT: ret <8 x i16> [[TMP2]]
686 //
test_vcaddq_rot270_x_s16(int16x8_t a,int16x8_t b,mve_pred16_t p)687 int16x8_t test_vcaddq_rot270_x_s16(int16x8_t a, int16x8_t b, mve_pred16_t p)
688 {
689 #ifdef POLYMORPHIC
690 return vcaddq_rot270_x(a, b, p);
691 #else
692 return vcaddq_rot270_x_s16(a, b, p);
693 #endif
694 }
695
696 // CHECK-LABEL: @test_vcaddq_rot270_x_s32(
697 // CHECK-NEXT: entry:
698 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
699 // CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
700 // CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 1, i32 1, <4 x i32> undef, <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i1> [[TMP1]])
701 // CHECK-NEXT: ret <4 x i32> [[TMP2]]
702 //
test_vcaddq_rot270_x_s32(int32x4_t a,int32x4_t b,mve_pred16_t p)703 int32x4_t test_vcaddq_rot270_x_s32(int32x4_t a, int32x4_t b, mve_pred16_t p)
704 {
705 #ifdef POLYMORPHIC
706 return vcaddq_rot270_x(a, b, p);
707 #else
708 return vcaddq_rot270_x_s32(a, b, p);
709 #endif
710 }
711
712 // CHECK-LABEL: @test_vcaddq_rot270_x_f16(
713 // CHECK-NEXT: entry:
714 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
715 // CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
716 // CHECK-NEXT: [[TMP2:%.*]] = call <8 x half> @llvm.arm.mve.vcaddq.predicated.v8f16.v8i1(i32 1, i32 1, <8 x half> undef, <8 x half> [[A:%.*]], <8 x half> [[B:%.*]], <8 x i1> [[TMP1]])
717 // CHECK-NEXT: ret <8 x half> [[TMP2]]
718 //
test_vcaddq_rot270_x_f16(float16x8_t a,float16x8_t b,mve_pred16_t p)719 float16x8_t test_vcaddq_rot270_x_f16(float16x8_t a, float16x8_t b, mve_pred16_t p)
720 {
721 #ifdef POLYMORPHIC
722 return vcaddq_rot270_x(a, b, p);
723 #else
724 return vcaddq_rot270_x_f16(a, b, p);
725 #endif
726 }
727
728 // CHECK-LABEL: @test_vcaddq_rot270_x_f32(
729 // CHECK-NEXT: entry:
730 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
731 // CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
732 // CHECK-NEXT: [[TMP2:%.*]] = call <4 x float> @llvm.arm.mve.vcaddq.predicated.v4f32.v4i1(i32 1, i32 1, <4 x float> undef, <4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x i1> [[TMP1]])
733 // CHECK-NEXT: ret <4 x float> [[TMP2]]
734 //
test_vcaddq_rot270_x_f32(float32x4_t a,float32x4_t b,mve_pred16_t p)735 float32x4_t test_vcaddq_rot270_x_f32(float32x4_t a, float32x4_t b, mve_pred16_t p)
736 {
737 #ifdef POLYMORPHIC
738 return vcaddq_rot270_x(a, b, p);
739 #else
740 return vcaddq_rot270_x_f32(a, b, p);
741 #endif
742 }
743