1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
2 // RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
3 // RUN: %clang_cc1 -DPOLYMORPHIC -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
4
5 #include <arm_mve.h>
6
7 // CHECK-LABEL: @test_vcvtaq_s16_f16(
8 // CHECK-NEXT: entry:
9 // CHECK-NEXT: [[TMP0:%.*]] = call <8 x i16> @llvm.arm.mve.vcvta.v8i16.v8f16(i32 0, <8 x half> [[A:%.*]])
10 // CHECK-NEXT: ret <8 x i16> [[TMP0]]
11 //
test_vcvtaq_s16_f16(float16x8_t a)12 int16x8_t test_vcvtaq_s16_f16(float16x8_t a)
13 {
14 return vcvtaq_s16_f16(a);
15 }
16
17 // CHECK-LABEL: @test_vcvtaq_s32_f32(
18 // CHECK-NEXT: entry:
19 // CHECK-NEXT: [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vcvta.v4i32.v4f32(i32 0, <4 x float> [[A:%.*]])
20 // CHECK-NEXT: ret <4 x i32> [[TMP0]]
21 //
test_vcvtaq_s32_f32(float32x4_t a)22 int32x4_t test_vcvtaq_s32_f32(float32x4_t a)
23 {
24 return vcvtaq_s32_f32(a);
25 }
26
27 // CHECK-LABEL: @test_vcvtaq_u16_f16(
28 // CHECK-NEXT: entry:
29 // CHECK-NEXT: [[TMP0:%.*]] = call <8 x i16> @llvm.arm.mve.vcvta.v8i16.v8f16(i32 1, <8 x half> [[A:%.*]])
30 // CHECK-NEXT: ret <8 x i16> [[TMP0]]
31 //
test_vcvtaq_u16_f16(float16x8_t a)32 uint16x8_t test_vcvtaq_u16_f16(float16x8_t a)
33 {
34 return vcvtaq_u16_f16(a);
35 }
36
37 // CHECK-LABEL: @test_vcvtaq_u32_f32(
38 // CHECK-NEXT: entry:
39 // CHECK-NEXT: [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vcvta.v4i32.v4f32(i32 1, <4 x float> [[A:%.*]])
40 // CHECK-NEXT: ret <4 x i32> [[TMP0]]
41 //
test_vcvtaq_u32_f32(float32x4_t a)42 uint32x4_t test_vcvtaq_u32_f32(float32x4_t a)
43 {
44 return vcvtaq_u32_f32(a);
45 }
46
47 // CHECK-LABEL: @test_vcvtmq_s16_f16(
48 // CHECK-NEXT: entry:
49 // CHECK-NEXT: [[TMP0:%.*]] = call <8 x i16> @llvm.arm.mve.vcvtm.v8i16.v8f16(i32 0, <8 x half> [[A:%.*]])
50 // CHECK-NEXT: ret <8 x i16> [[TMP0]]
51 //
test_vcvtmq_s16_f16(float16x8_t a)52 int16x8_t test_vcvtmq_s16_f16(float16x8_t a)
53 {
54 return vcvtmq_s16_f16(a);
55 }
56
57 // CHECK-LABEL: @test_vcvtmq_s32_f32(
58 // CHECK-NEXT: entry:
59 // CHECK-NEXT: [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vcvtm.v4i32.v4f32(i32 0, <4 x float> [[A:%.*]])
60 // CHECK-NEXT: ret <4 x i32> [[TMP0]]
61 //
test_vcvtmq_s32_f32(float32x4_t a)62 int32x4_t test_vcvtmq_s32_f32(float32x4_t a)
63 {
64 return vcvtmq_s32_f32(a);
65 }
66
67 // CHECK-LABEL: @test_vcvtmq_u16_f16(
68 // CHECK-NEXT: entry:
69 // CHECK-NEXT: [[TMP0:%.*]] = call <8 x i16> @llvm.arm.mve.vcvtm.v8i16.v8f16(i32 1, <8 x half> [[A:%.*]])
70 // CHECK-NEXT: ret <8 x i16> [[TMP0]]
71 //
test_vcvtmq_u16_f16(float16x8_t a)72 uint16x8_t test_vcvtmq_u16_f16(float16x8_t a)
73 {
74 return vcvtmq_u16_f16(a);
75 }
76
77 // CHECK-LABEL: @test_vcvtmq_u32_f32(
78 // CHECK-NEXT: entry:
79 // CHECK-NEXT: [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vcvtm.v4i32.v4f32(i32 1, <4 x float> [[A:%.*]])
80 // CHECK-NEXT: ret <4 x i32> [[TMP0]]
81 //
test_vcvtmq_u32_f32(float32x4_t a)82 uint32x4_t test_vcvtmq_u32_f32(float32x4_t a)
83 {
84 return vcvtmq_u32_f32(a);
85 }
86
87 // CHECK-LABEL: @test_vcvtnq_s16_f16(
88 // CHECK-NEXT: entry:
89 // CHECK-NEXT: [[TMP0:%.*]] = call <8 x i16> @llvm.arm.mve.vcvtn.v8i16.v8f16(i32 0, <8 x half> [[A:%.*]])
90 // CHECK-NEXT: ret <8 x i16> [[TMP0]]
91 //
test_vcvtnq_s16_f16(float16x8_t a)92 int16x8_t test_vcvtnq_s16_f16(float16x8_t a)
93 {
94 return vcvtnq_s16_f16(a);
95 }
96
97 // CHECK-LABEL: @test_vcvtnq_s32_f32(
98 // CHECK-NEXT: entry:
99 // CHECK-NEXT: [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vcvtn.v4i32.v4f32(i32 0, <4 x float> [[A:%.*]])
100 // CHECK-NEXT: ret <4 x i32> [[TMP0]]
101 //
test_vcvtnq_s32_f32(float32x4_t a)102 int32x4_t test_vcvtnq_s32_f32(float32x4_t a)
103 {
104 return vcvtnq_s32_f32(a);
105 }
106
107 // CHECK-LABEL: @test_vcvtnq_u16_f16(
108 // CHECK-NEXT: entry:
109 // CHECK-NEXT: [[TMP0:%.*]] = call <8 x i16> @llvm.arm.mve.vcvtn.v8i16.v8f16(i32 1, <8 x half> [[A:%.*]])
110 // CHECK-NEXT: ret <8 x i16> [[TMP0]]
111 //
test_vcvtnq_u16_f16(float16x8_t a)112 uint16x8_t test_vcvtnq_u16_f16(float16x8_t a)
113 {
114 return vcvtnq_u16_f16(a);
115 }
116
117 // CHECK-LABEL: @test_vcvtnq_u32_f32(
118 // CHECK-NEXT: entry:
119 // CHECK-NEXT: [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vcvtn.v4i32.v4f32(i32 1, <4 x float> [[A:%.*]])
120 // CHECK-NEXT: ret <4 x i32> [[TMP0]]
121 //
test_vcvtnq_u32_f32(float32x4_t a)122 uint32x4_t test_vcvtnq_u32_f32(float32x4_t a)
123 {
124 return vcvtnq_u32_f32(a);
125 }
126
127 // CHECK-LABEL: @test_vcvtpq_s16_f16(
128 // CHECK-NEXT: entry:
129 // CHECK-NEXT: [[TMP0:%.*]] = call <8 x i16> @llvm.arm.mve.vcvtp.v8i16.v8f16(i32 0, <8 x half> [[A:%.*]])
130 // CHECK-NEXT: ret <8 x i16> [[TMP0]]
131 //
test_vcvtpq_s16_f16(float16x8_t a)132 int16x8_t test_vcvtpq_s16_f16(float16x8_t a)
133 {
134 return vcvtpq_s16_f16(a);
135 }
136
137 // CHECK-LABEL: @test_vcvtpq_s32_f32(
138 // CHECK-NEXT: entry:
139 // CHECK-NEXT: [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vcvtp.v4i32.v4f32(i32 0, <4 x float> [[A:%.*]])
140 // CHECK-NEXT: ret <4 x i32> [[TMP0]]
141 //
test_vcvtpq_s32_f32(float32x4_t a)142 int32x4_t test_vcvtpq_s32_f32(float32x4_t a)
143 {
144 return vcvtpq_s32_f32(a);
145 }
146
147 // CHECK-LABEL: @test_vcvtpq_u16_f16(
148 // CHECK-NEXT: entry:
149 // CHECK-NEXT: [[TMP0:%.*]] = call <8 x i16> @llvm.arm.mve.vcvtp.v8i16.v8f16(i32 1, <8 x half> [[A:%.*]])
150 // CHECK-NEXT: ret <8 x i16> [[TMP0]]
151 //
test_vcvtpq_u16_f16(float16x8_t a)152 uint16x8_t test_vcvtpq_u16_f16(float16x8_t a)
153 {
154 return vcvtpq_u16_f16(a);
155 }
156
157 // CHECK-LABEL: @test_vcvtpq_u32_f32(
158 // CHECK-NEXT: entry:
159 // CHECK-NEXT: [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vcvtp.v4i32.v4f32(i32 1, <4 x float> [[A:%.*]])
160 // CHECK-NEXT: ret <4 x i32> [[TMP0]]
161 //
test_vcvtpq_u32_f32(float32x4_t a)162 uint32x4_t test_vcvtpq_u32_f32(float32x4_t a)
163 {
164 return vcvtpq_u32_f32(a);
165 }
166
167 // CHECK-LABEL: @test_vcvtaq_m_s16_f16(
168 // CHECK-NEXT: entry:
169 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
170 // CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
171 // CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vcvta.predicated.v8i16.v8f16.v8i1(i32 0, <8 x i16> [[INACTIVE:%.*]], <8 x half> [[A:%.*]], <8 x i1> [[TMP1]])
172 // CHECK-NEXT: ret <8 x i16> [[TMP2]]
173 //
test_vcvtaq_m_s16_f16(int16x8_t inactive,float16x8_t a,mve_pred16_t p)174 int16x8_t test_vcvtaq_m_s16_f16(int16x8_t inactive, float16x8_t a, mve_pred16_t p)
175 {
176 #ifdef POLYMORPHIC
177 return vcvtaq_m(inactive, a, p);
178 #else /* POLYMORPHIC */
179 return vcvtaq_m_s16_f16(inactive, a, p);
180 #endif /* POLYMORPHIC */
181 }
182
183 // CHECK-LABEL: @test_vcvtaq_m_s32_f32(
184 // CHECK-NEXT: entry:
185 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
186 // CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
187 // CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vcvta.predicated.v4i32.v4f32.v4i1(i32 0, <4 x i32> [[INACTIVE:%.*]], <4 x float> [[A:%.*]], <4 x i1> [[TMP1]])
188 // CHECK-NEXT: ret <4 x i32> [[TMP2]]
189 //
test_vcvtaq_m_s32_f32(int32x4_t inactive,float32x4_t a,mve_pred16_t p)190 int32x4_t test_vcvtaq_m_s32_f32(int32x4_t inactive, float32x4_t a, mve_pred16_t p)
191 {
192 #ifdef POLYMORPHIC
193 return vcvtaq_m(inactive, a, p);
194 #else /* POLYMORPHIC */
195 return vcvtaq_m_s32_f32(inactive, a, p);
196 #endif /* POLYMORPHIC */
197 }
198
199 // CHECK-LABEL: @test_vcvtaq_m_u16_f16(
200 // CHECK-NEXT: entry:
201 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
202 // CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
203 // CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vcvta.predicated.v8i16.v8f16.v8i1(i32 1, <8 x i16> [[INACTIVE:%.*]], <8 x half> [[A:%.*]], <8 x i1> [[TMP1]])
204 // CHECK-NEXT: ret <8 x i16> [[TMP2]]
205 //
test_vcvtaq_m_u16_f16(uint16x8_t inactive,float16x8_t a,mve_pred16_t p)206 uint16x8_t test_vcvtaq_m_u16_f16(uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
207 {
208 #ifdef POLYMORPHIC
209 return vcvtaq_m(inactive, a, p);
210 #else /* POLYMORPHIC */
211 return vcvtaq_m_u16_f16(inactive, a, p);
212 #endif /* POLYMORPHIC */
213 }
214
215 // CHECK-LABEL: @test_vcvtaq_m_u32_f32(
216 // CHECK-NEXT: entry:
217 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
218 // CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
219 // CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vcvta.predicated.v4i32.v4f32.v4i1(i32 1, <4 x i32> [[INACTIVE:%.*]], <4 x float> [[A:%.*]], <4 x i1> [[TMP1]])
220 // CHECK-NEXT: ret <4 x i32> [[TMP2]]
221 //
test_vcvtaq_m_u32_f32(uint32x4_t inactive,float32x4_t a,mve_pred16_t p)222 uint32x4_t test_vcvtaq_m_u32_f32(uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
223 {
224 #ifdef POLYMORPHIC
225 return vcvtaq_m(inactive, a, p);
226 #else /* POLYMORPHIC */
227 return vcvtaq_m_u32_f32(inactive, a, p);
228 #endif /* POLYMORPHIC */
229 }
230
231 // CHECK-LABEL: @test_vcvtmq_m_s16_f16(
232 // CHECK-NEXT: entry:
233 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
234 // CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
235 // CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vcvtm.predicated.v8i16.v8f16.v8i1(i32 0, <8 x i16> [[INACTIVE:%.*]], <8 x half> [[A:%.*]], <8 x i1> [[TMP1]])
236 // CHECK-NEXT: ret <8 x i16> [[TMP2]]
237 //
test_vcvtmq_m_s16_f16(int16x8_t inactive,float16x8_t a,mve_pred16_t p)238 int16x8_t test_vcvtmq_m_s16_f16(int16x8_t inactive, float16x8_t a, mve_pred16_t p)
239 {
240 #ifdef POLYMORPHIC
241 return vcvtmq_m(inactive, a, p);
242 #else /* POLYMORPHIC */
243 return vcvtmq_m_s16_f16(inactive, a, p);
244 #endif /* POLYMORPHIC */
245 }
246
247 // CHECK-LABEL: @test_vcvtmq_m_s32_f32(
248 // CHECK-NEXT: entry:
249 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
250 // CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
251 // CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vcvtm.predicated.v4i32.v4f32.v4i1(i32 0, <4 x i32> [[INACTIVE:%.*]], <4 x float> [[A:%.*]], <4 x i1> [[TMP1]])
252 // CHECK-NEXT: ret <4 x i32> [[TMP2]]
253 //
test_vcvtmq_m_s32_f32(int32x4_t inactive,float32x4_t a,mve_pred16_t p)254 int32x4_t test_vcvtmq_m_s32_f32(int32x4_t inactive, float32x4_t a, mve_pred16_t p)
255 {
256 #ifdef POLYMORPHIC
257 return vcvtmq_m(inactive, a, p);
258 #else /* POLYMORPHIC */
259 return vcvtmq_m_s32_f32(inactive, a, p);
260 #endif /* POLYMORPHIC */
261 }
262
263 // CHECK-LABEL: @test_vcvtmq_m_u16_f16(
264 // CHECK-NEXT: entry:
265 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
266 // CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
267 // CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vcvtm.predicated.v8i16.v8f16.v8i1(i32 1, <8 x i16> [[INACTIVE:%.*]], <8 x half> [[A:%.*]], <8 x i1> [[TMP1]])
268 // CHECK-NEXT: ret <8 x i16> [[TMP2]]
269 //
test_vcvtmq_m_u16_f16(uint16x8_t inactive,float16x8_t a,mve_pred16_t p)270 uint16x8_t test_vcvtmq_m_u16_f16(uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
271 {
272 #ifdef POLYMORPHIC
273 return vcvtmq_m(inactive, a, p);
274 #else /* POLYMORPHIC */
275 return vcvtmq_m_u16_f16(inactive, a, p);
276 #endif /* POLYMORPHIC */
277 }
278
279 // CHECK-LABEL: @test_vcvtmq_m_u32_f32(
280 // CHECK-NEXT: entry:
281 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
282 // CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
283 // CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vcvtm.predicated.v4i32.v4f32.v4i1(i32 1, <4 x i32> [[INACTIVE:%.*]], <4 x float> [[A:%.*]], <4 x i1> [[TMP1]])
284 // CHECK-NEXT: ret <4 x i32> [[TMP2]]
285 //
test_vcvtmq_m_u32_f32(uint32x4_t inactive,float32x4_t a,mve_pred16_t p)286 uint32x4_t test_vcvtmq_m_u32_f32(uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
287 {
288 #ifdef POLYMORPHIC
289 return vcvtmq_m(inactive, a, p);
290 #else /* POLYMORPHIC */
291 return vcvtmq_m_u32_f32(inactive, a, p);
292 #endif /* POLYMORPHIC */
293 }
294
295 // CHECK-LABEL: @test_vcvtnq_m_s16_f16(
296 // CHECK-NEXT: entry:
297 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
298 // CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
299 // CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vcvtn.predicated.v8i16.v8f16.v8i1(i32 0, <8 x i16> [[INACTIVE:%.*]], <8 x half> [[A:%.*]], <8 x i1> [[TMP1]])
300 // CHECK-NEXT: ret <8 x i16> [[TMP2]]
301 //
test_vcvtnq_m_s16_f16(int16x8_t inactive,float16x8_t a,mve_pred16_t p)302 int16x8_t test_vcvtnq_m_s16_f16(int16x8_t inactive, float16x8_t a, mve_pred16_t p)
303 {
304 #ifdef POLYMORPHIC
305 return vcvtnq_m(inactive, a, p);
306 #else /* POLYMORPHIC */
307 return vcvtnq_m_s16_f16(inactive, a, p);
308 #endif /* POLYMORPHIC */
309 }
310
311 // CHECK-LABEL: @test_vcvtnq_m_s32_f32(
312 // CHECK-NEXT: entry:
313 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
314 // CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
315 // CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vcvtn.predicated.v4i32.v4f32.v4i1(i32 0, <4 x i32> [[INACTIVE:%.*]], <4 x float> [[A:%.*]], <4 x i1> [[TMP1]])
316 // CHECK-NEXT: ret <4 x i32> [[TMP2]]
317 //
test_vcvtnq_m_s32_f32(int32x4_t inactive,float32x4_t a,mve_pred16_t p)318 int32x4_t test_vcvtnq_m_s32_f32(int32x4_t inactive, float32x4_t a, mve_pred16_t p)
319 {
320 #ifdef POLYMORPHIC
321 return vcvtnq_m(inactive, a, p);
322 #else /* POLYMORPHIC */
323 return vcvtnq_m_s32_f32(inactive, a, p);
324 #endif /* POLYMORPHIC */
325 }
326
327 // CHECK-LABEL: @test_vcvtnq_m_u16_f16(
328 // CHECK-NEXT: entry:
329 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
330 // CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
331 // CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vcvtn.predicated.v8i16.v8f16.v8i1(i32 1, <8 x i16> [[INACTIVE:%.*]], <8 x half> [[A:%.*]], <8 x i1> [[TMP1]])
332 // CHECK-NEXT: ret <8 x i16> [[TMP2]]
333 //
test_vcvtnq_m_u16_f16(uint16x8_t inactive,float16x8_t a,mve_pred16_t p)334 uint16x8_t test_vcvtnq_m_u16_f16(uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
335 {
336 #ifdef POLYMORPHIC
337 return vcvtnq_m(inactive, a, p);
338 #else /* POLYMORPHIC */
339 return vcvtnq_m_u16_f16(inactive, a, p);
340 #endif /* POLYMORPHIC */
341 }
342
343 // CHECK-LABEL: @test_vcvtnq_m_u32_f32(
344 // CHECK-NEXT: entry:
345 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
346 // CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
347 // CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vcvtn.predicated.v4i32.v4f32.v4i1(i32 1, <4 x i32> [[INACTIVE:%.*]], <4 x float> [[A:%.*]], <4 x i1> [[TMP1]])
348 // CHECK-NEXT: ret <4 x i32> [[TMP2]]
349 //
test_vcvtnq_m_u32_f32(uint32x4_t inactive,float32x4_t a,mve_pred16_t p)350 uint32x4_t test_vcvtnq_m_u32_f32(uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
351 {
352 #ifdef POLYMORPHIC
353 return vcvtnq_m(inactive, a, p);
354 #else /* POLYMORPHIC */
355 return vcvtnq_m_u32_f32(inactive, a, p);
356 #endif /* POLYMORPHIC */
357 }
358
359 // CHECK-LABEL: @test_vcvtpq_m_s16_f16(
360 // CHECK-NEXT: entry:
361 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
362 // CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
363 // CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vcvtp.predicated.v8i16.v8f16.v8i1(i32 0, <8 x i16> [[INACTIVE:%.*]], <8 x half> [[A:%.*]], <8 x i1> [[TMP1]])
364 // CHECK-NEXT: ret <8 x i16> [[TMP2]]
365 //
test_vcvtpq_m_s16_f16(int16x8_t inactive,float16x8_t a,mve_pred16_t p)366 int16x8_t test_vcvtpq_m_s16_f16(int16x8_t inactive, float16x8_t a, mve_pred16_t p)
367 {
368 #ifdef POLYMORPHIC
369 return vcvtpq_m(inactive, a, p);
370 #else /* POLYMORPHIC */
371 return vcvtpq_m_s16_f16(inactive, a, p);
372 #endif /* POLYMORPHIC */
373 }
374
375 // CHECK-LABEL: @test_vcvtpq_m_s32_f32(
376 // CHECK-NEXT: entry:
377 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
378 // CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
379 // CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vcvtp.predicated.v4i32.v4f32.v4i1(i32 0, <4 x i32> [[INACTIVE:%.*]], <4 x float> [[A:%.*]], <4 x i1> [[TMP1]])
380 // CHECK-NEXT: ret <4 x i32> [[TMP2]]
381 //
test_vcvtpq_m_s32_f32(int32x4_t inactive,float32x4_t a,mve_pred16_t p)382 int32x4_t test_vcvtpq_m_s32_f32(int32x4_t inactive, float32x4_t a, mve_pred16_t p)
383 {
384 #ifdef POLYMORPHIC
385 return vcvtpq_m(inactive, a, p);
386 #else /* POLYMORPHIC */
387 return vcvtpq_m_s32_f32(inactive, a, p);
388 #endif /* POLYMORPHIC */
389 }
390
391 // CHECK-LABEL: @test_vcvtpq_m_u16_f16(
392 // CHECK-NEXT: entry:
393 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
394 // CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
395 // CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vcvtp.predicated.v8i16.v8f16.v8i1(i32 1, <8 x i16> [[INACTIVE:%.*]], <8 x half> [[A:%.*]], <8 x i1> [[TMP1]])
396 // CHECK-NEXT: ret <8 x i16> [[TMP2]]
397 //
test_vcvtpq_m_u16_f16(uint16x8_t inactive,float16x8_t a,mve_pred16_t p)398 uint16x8_t test_vcvtpq_m_u16_f16(uint16x8_t inactive, float16x8_t a, mve_pred16_t p)
399 {
400 #ifdef POLYMORPHIC
401 return vcvtpq_m(inactive, a, p);
402 #else /* POLYMORPHIC */
403 return vcvtpq_m_u16_f16(inactive, a, p);
404 #endif /* POLYMORPHIC */
405 }
406
407 // CHECK-LABEL: @test_vcvtpq_m_u32_f32(
408 // CHECK-NEXT: entry:
409 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
410 // CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
411 // CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vcvtp.predicated.v4i32.v4f32.v4i1(i32 1, <4 x i32> [[INACTIVE:%.*]], <4 x float> [[A:%.*]], <4 x i1> [[TMP1]])
412 // CHECK-NEXT: ret <4 x i32> [[TMP2]]
413 //
test_vcvtpq_m_u32_f32(uint32x4_t inactive,float32x4_t a,mve_pred16_t p)414 uint32x4_t test_vcvtpq_m_u32_f32(uint32x4_t inactive, float32x4_t a, mve_pred16_t p)
415 {
416 #ifdef POLYMORPHIC
417 return vcvtpq_m(inactive, a, p);
418 #else /* POLYMORPHIC */
419 return vcvtpq_m_u32_f32(inactive, a, p);
420 #endif /* POLYMORPHIC */
421 }
422
423 // CHECK-LABEL: @test_vcvtaq_x_s16_f16(
424 // CHECK-NEXT: entry:
425 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
426 // CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
427 // CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vcvta.predicated.v8i16.v8f16.v8i1(i32 0, <8 x i16> undef, <8 x half> [[A:%.*]], <8 x i1> [[TMP1]])
428 // CHECK-NEXT: ret <8 x i16> [[TMP2]]
429 //
test_vcvtaq_x_s16_f16(float16x8_t a,mve_pred16_t p)430 int16x8_t test_vcvtaq_x_s16_f16(float16x8_t a, mve_pred16_t p)
431 {
432 return vcvtaq_x_s16_f16(a, p);
433 }
434
435 // CHECK-LABEL: @test_vcvtaq_x_s32_f32(
436 // CHECK-NEXT: entry:
437 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
438 // CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
439 // CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vcvta.predicated.v4i32.v4f32.v4i1(i32 0, <4 x i32> undef, <4 x float> [[A:%.*]], <4 x i1> [[TMP1]])
440 // CHECK-NEXT: ret <4 x i32> [[TMP2]]
441 //
test_vcvtaq_x_s32_f32(float32x4_t a,mve_pred16_t p)442 int32x4_t test_vcvtaq_x_s32_f32(float32x4_t a, mve_pred16_t p)
443 {
444 return vcvtaq_x_s32_f32(a, p);
445 }
446
447 // CHECK-LABEL: @test_vcvtaq_x_u16_f16(
448 // CHECK-NEXT: entry:
449 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
450 // CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
451 // CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vcvta.predicated.v8i16.v8f16.v8i1(i32 1, <8 x i16> undef, <8 x half> [[A:%.*]], <8 x i1> [[TMP1]])
452 // CHECK-NEXT: ret <8 x i16> [[TMP2]]
453 //
test_vcvtaq_x_u16_f16(float16x8_t a,mve_pred16_t p)454 uint16x8_t test_vcvtaq_x_u16_f16(float16x8_t a, mve_pred16_t p)
455 {
456 return vcvtaq_x_u16_f16(a, p);
457 }
458
459 // CHECK-LABEL: @test_vcvtaq_x_u32_f32(
460 // CHECK-NEXT: entry:
461 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
462 // CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
463 // CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vcvta.predicated.v4i32.v4f32.v4i1(i32 1, <4 x i32> undef, <4 x float> [[A:%.*]], <4 x i1> [[TMP1]])
464 // CHECK-NEXT: ret <4 x i32> [[TMP2]]
465 //
test_vcvtaq_x_u32_f32(float32x4_t a,mve_pred16_t p)466 uint32x4_t test_vcvtaq_x_u32_f32(float32x4_t a, mve_pred16_t p)
467 {
468 return vcvtaq_x_u32_f32(a, p);
469 }
470
471 // CHECK-LABEL: @test_vcvtmq_x_s16_f16(
472 // CHECK-NEXT: entry:
473 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
474 // CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
475 // CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vcvtm.predicated.v8i16.v8f16.v8i1(i32 0, <8 x i16> undef, <8 x half> [[A:%.*]], <8 x i1> [[TMP1]])
476 // CHECK-NEXT: ret <8 x i16> [[TMP2]]
477 //
test_vcvtmq_x_s16_f16(float16x8_t a,mve_pred16_t p)478 int16x8_t test_vcvtmq_x_s16_f16(float16x8_t a, mve_pred16_t p)
479 {
480 return vcvtmq_x_s16_f16(a, p);
481 }
482
483 // CHECK-LABEL: @test_vcvtmq_x_s32_f32(
484 // CHECK-NEXT: entry:
485 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
486 // CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
487 // CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vcvtm.predicated.v4i32.v4f32.v4i1(i32 0, <4 x i32> undef, <4 x float> [[A:%.*]], <4 x i1> [[TMP1]])
488 // CHECK-NEXT: ret <4 x i32> [[TMP2]]
489 //
test_vcvtmq_x_s32_f32(float32x4_t a,mve_pred16_t p)490 int32x4_t test_vcvtmq_x_s32_f32(float32x4_t a, mve_pred16_t p)
491 {
492 return vcvtmq_x_s32_f32(a, p);
493 }
494
495 // CHECK-LABEL: @test_vcvtmq_x_u16_f16(
496 // CHECK-NEXT: entry:
497 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
498 // CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
499 // CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vcvtm.predicated.v8i16.v8f16.v8i1(i32 1, <8 x i16> undef, <8 x half> [[A:%.*]], <8 x i1> [[TMP1]])
500 // CHECK-NEXT: ret <8 x i16> [[TMP2]]
501 //
test_vcvtmq_x_u16_f16(float16x8_t a,mve_pred16_t p)502 uint16x8_t test_vcvtmq_x_u16_f16(float16x8_t a, mve_pred16_t p)
503 {
504 return vcvtmq_x_u16_f16(a, p);
505 }
506
507 // CHECK-LABEL: @test_vcvtmq_x_u32_f32(
508 // CHECK-NEXT: entry:
509 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
510 // CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
511 // CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vcvtm.predicated.v4i32.v4f32.v4i1(i32 1, <4 x i32> undef, <4 x float> [[A:%.*]], <4 x i1> [[TMP1]])
512 // CHECK-NEXT: ret <4 x i32> [[TMP2]]
513 //
test_vcvtmq_x_u32_f32(float32x4_t a,mve_pred16_t p)514 uint32x4_t test_vcvtmq_x_u32_f32(float32x4_t a, mve_pred16_t p)
515 {
516 return vcvtmq_x_u32_f32(a, p);
517 }
518
519 // CHECK-LABEL: @test_vcvtnq_x_s16_f16(
520 // CHECK-NEXT: entry:
521 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
522 // CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
523 // CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vcvtn.predicated.v8i16.v8f16.v8i1(i32 0, <8 x i16> undef, <8 x half> [[A:%.*]], <8 x i1> [[TMP1]])
524 // CHECK-NEXT: ret <8 x i16> [[TMP2]]
525 //
test_vcvtnq_x_s16_f16(float16x8_t a,mve_pred16_t p)526 int16x8_t test_vcvtnq_x_s16_f16(float16x8_t a, mve_pred16_t p)
527 {
528 return vcvtnq_x_s16_f16(a, p);
529 }
530
531 // CHECK-LABEL: @test_vcvtnq_x_s32_f32(
532 // CHECK-NEXT: entry:
533 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
534 // CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
535 // CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vcvtn.predicated.v4i32.v4f32.v4i1(i32 0, <4 x i32> undef, <4 x float> [[A:%.*]], <4 x i1> [[TMP1]])
536 // CHECK-NEXT: ret <4 x i32> [[TMP2]]
537 //
test_vcvtnq_x_s32_f32(float32x4_t a,mve_pred16_t p)538 int32x4_t test_vcvtnq_x_s32_f32(float32x4_t a, mve_pred16_t p)
539 {
540 return vcvtnq_x_s32_f32(a, p);
541 }
542
543 // CHECK-LABEL: @test_vcvtnq_x_u16_f16(
544 // CHECK-NEXT: entry:
545 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
546 // CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
547 // CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vcvtn.predicated.v8i16.v8f16.v8i1(i32 1, <8 x i16> undef, <8 x half> [[A:%.*]], <8 x i1> [[TMP1]])
548 // CHECK-NEXT: ret <8 x i16> [[TMP2]]
549 //
test_vcvtnq_x_u16_f16(float16x8_t a,mve_pred16_t p)550 uint16x8_t test_vcvtnq_x_u16_f16(float16x8_t a, mve_pred16_t p)
551 {
552 return vcvtnq_x_u16_f16(a, p);
553 }
554
555 // CHECK-LABEL: @test_vcvtnq_x_u32_f32(
556 // CHECK-NEXT: entry:
557 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
558 // CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
559 // CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vcvtn.predicated.v4i32.v4f32.v4i1(i32 1, <4 x i32> undef, <4 x float> [[A:%.*]], <4 x i1> [[TMP1]])
560 // CHECK-NEXT: ret <4 x i32> [[TMP2]]
561 //
test_vcvtnq_x_u32_f32(float32x4_t a,mve_pred16_t p)562 uint32x4_t test_vcvtnq_x_u32_f32(float32x4_t a, mve_pred16_t p)
563 {
564 return vcvtnq_x_u32_f32(a, p);
565 }
566
567 // CHECK-LABEL: @test_vcvtpq_x_s16_f16(
568 // CHECK-NEXT: entry:
569 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
570 // CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
571 // CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vcvtp.predicated.v8i16.v8f16.v8i1(i32 0, <8 x i16> undef, <8 x half> [[A:%.*]], <8 x i1> [[TMP1]])
572 // CHECK-NEXT: ret <8 x i16> [[TMP2]]
573 //
test_vcvtpq_x_s16_f16(float16x8_t a,mve_pred16_t p)574 int16x8_t test_vcvtpq_x_s16_f16(float16x8_t a, mve_pred16_t p)
575 {
576 return vcvtpq_x_s16_f16(a, p);
577 }
578
579 // CHECK-LABEL: @test_vcvtpq_x_s32_f32(
580 // CHECK-NEXT: entry:
581 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
582 // CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
583 // CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vcvtp.predicated.v4i32.v4f32.v4i1(i32 0, <4 x i32> undef, <4 x float> [[A:%.*]], <4 x i1> [[TMP1]])
584 // CHECK-NEXT: ret <4 x i32> [[TMP2]]
585 //
test_vcvtpq_x_s32_f32(float32x4_t a,mve_pred16_t p)586 int32x4_t test_vcvtpq_x_s32_f32(float32x4_t a, mve_pred16_t p)
587 {
588 return vcvtpq_x_s32_f32(a, p);
589 }
590
591 // CHECK-LABEL: @test_vcvtpq_x_u16_f16(
592 // CHECK-NEXT: entry:
593 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
594 // CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
595 // CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vcvtp.predicated.v8i16.v8f16.v8i1(i32 1, <8 x i16> undef, <8 x half> [[A:%.*]], <8 x i1> [[TMP1]])
596 // CHECK-NEXT: ret <8 x i16> [[TMP2]]
597 //
test_vcvtpq_x_u16_f16(float16x8_t a,mve_pred16_t p)598 uint16x8_t test_vcvtpq_x_u16_f16(float16x8_t a, mve_pred16_t p)
599 {
600 return vcvtpq_x_u16_f16(a, p);
601 }
602
603 // CHECK-LABEL: @test_vcvtpq_x_u32_f32(
604 // CHECK-NEXT: entry:
605 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
606 // CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
607 // CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vcvtp.predicated.v4i32.v4f32.v4i1(i32 1, <4 x i32> undef, <4 x float> [[A:%.*]], <4 x i1> [[TMP1]])
608 // CHECK-NEXT: ret <4 x i32> [[TMP2]]
609 //
test_vcvtpq_x_u32_f32(float32x4_t a,mve_pred16_t p)610 uint32x4_t test_vcvtpq_x_u32_f32(float32x4_t a, mve_pred16_t p)
611 {
612 return vcvtpq_x_u32_f32(a, p);
613 }
614
615