1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
2 // RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
3 // RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
4 
5 #include <arm_mve.h>
6 
7 // CHECK-LABEL: @test_vhcaddq_rot90_s8(
8 // CHECK-NEXT:  entry:
9 // CHECK-NEXT:    [[TMP0:%.*]] = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 0, i32 0, <16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]])
10 // CHECK-NEXT:    ret <16 x i8> [[TMP0]]
11 //
test_vhcaddq_rot90_s8(int8x16_t a,int8x16_t b)12 int8x16_t test_vhcaddq_rot90_s8(int8x16_t a, int8x16_t b)
13 {
14 #ifdef POLYMORPHIC
15     return vhcaddq_rot90(a, b);
16 #else
17     return vhcaddq_rot90_s8(a, b);
18 #endif
19 }
20 
21 // CHECK-LABEL: @test_vhcaddq_rot90_s16(
22 // CHECK-NEXT:  entry:
23 // CHECK-NEXT:    [[TMP0:%.*]] = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 0, i32 0, <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]])
24 // CHECK-NEXT:    ret <8 x i16> [[TMP0]]
25 //
test_vhcaddq_rot90_s16(int16x8_t a,int16x8_t b)26 int16x8_t test_vhcaddq_rot90_s16(int16x8_t a, int16x8_t b)
27 {
28 #ifdef POLYMORPHIC
29     return vhcaddq_rot90(a, b);
30 #else
31     return vhcaddq_rot90_s16(a, b);
32 #endif
33 }
34 
35 // CHECK-LABEL: @test_vhcaddq_rot90_s32(
36 // CHECK-NEXT:  entry:
37 // CHECK-NEXT:    [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 0, i32 0, <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]])
38 // CHECK-NEXT:    ret <4 x i32> [[TMP0]]
39 //
test_vhcaddq_rot90_s32(int32x4_t a,int32x4_t b)40 int32x4_t test_vhcaddq_rot90_s32(int32x4_t a, int32x4_t b)
41 {
42 #ifdef POLYMORPHIC
43     return vhcaddq_rot90(a, b);
44 #else
45     return vhcaddq_rot90_s32(a, b);
46 #endif
47 }
48 
49 // CHECK-LABEL: @test_vhcaddq_rot270_s8(
50 // CHECK-NEXT:  entry:
51 // CHECK-NEXT:    [[TMP0:%.*]] = call <16 x i8> @llvm.arm.mve.vcaddq.v16i8(i32 0, i32 1, <16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]])
52 // CHECK-NEXT:    ret <16 x i8> [[TMP0]]
53 //
test_vhcaddq_rot270_s8(int8x16_t a,int8x16_t b)54 int8x16_t test_vhcaddq_rot270_s8(int8x16_t a, int8x16_t b)
55 {
56 #ifdef POLYMORPHIC
57     return vhcaddq_rot270(a, b);
58 #else
59     return vhcaddq_rot270_s8(a, b);
60 #endif
61 }
62 
63 // CHECK-LABEL: @test_vhcaddq_rot270_s16(
64 // CHECK-NEXT:  entry:
65 // CHECK-NEXT:    [[TMP0:%.*]] = call <8 x i16> @llvm.arm.mve.vcaddq.v8i16(i32 0, i32 1, <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]])
66 // CHECK-NEXT:    ret <8 x i16> [[TMP0]]
67 //
test_vhcaddq_rot270_s16(int16x8_t a,int16x8_t b)68 int16x8_t test_vhcaddq_rot270_s16(int16x8_t a, int16x8_t b)
69 {
70 #ifdef POLYMORPHIC
71     return vhcaddq_rot270(a, b);
72 #else
73     return vhcaddq_rot270_s16(a, b);
74 #endif
75 }
76 
77 // CHECK-LABEL: @test_vhcaddq_rot270_s32(
78 // CHECK-NEXT:  entry:
79 // CHECK-NEXT:    [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vcaddq.v4i32(i32 0, i32 1, <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]])
80 // CHECK-NEXT:    ret <4 x i32> [[TMP0]]
81 //
test_vhcaddq_rot270_s32(int32x4_t a,int32x4_t b)82 int32x4_t test_vhcaddq_rot270_s32(int32x4_t a, int32x4_t b)
83 {
84 #ifdef POLYMORPHIC
85     return vhcaddq_rot270(a, b);
86 #else
87     return vhcaddq_rot270_s32(a, b);
88 #endif
89 }
90 
91 // CHECK-LABEL: @test_vhcaddq_rot90_x_s8(
92 // CHECK-NEXT:  entry:
93 // CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
94 // CHECK-NEXT:    [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])
95 // CHECK-NEXT:    [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 0, i32 0, <16 x i8> undef, <16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], <16 x i1> [[TMP1]])
96 // CHECK-NEXT:    ret <16 x i8> [[TMP2]]
97 //
test_vhcaddq_rot90_x_s8(int8x16_t a,int8x16_t b,mve_pred16_t p)98 int8x16_t test_vhcaddq_rot90_x_s8(int8x16_t a, int8x16_t b, mve_pred16_t p)
99 {
100 #ifdef POLYMORPHIC
101     return vhcaddq_rot90_x(a, b, p);
102 #else
103     return vhcaddq_rot90_x_s8(a, b, p);
104 #endif
105 }
106 
107 // CHECK-LABEL: @test_vhcaddq_rot90_x_s16(
108 // CHECK-NEXT:  entry:
109 // CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
110 // CHECK-NEXT:    [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
111 // CHECK-NEXT:    [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 0, i32 0, <8 x i16> undef, <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], <8 x i1> [[TMP1]])
112 // CHECK-NEXT:    ret <8 x i16> [[TMP2]]
113 //
test_vhcaddq_rot90_x_s16(int16x8_t a,int16x8_t b,mve_pred16_t p)114 int16x8_t test_vhcaddq_rot90_x_s16(int16x8_t a, int16x8_t b, mve_pred16_t p)
115 {
116 #ifdef POLYMORPHIC
117     return vhcaddq_rot90_x(a, b, p);
118 #else
119     return vhcaddq_rot90_x_s16(a, b, p);
120 #endif
121 }
122 
123 // CHECK-LABEL: @test_vhcaddq_rot90_x_s32(
124 // CHECK-NEXT:  entry:
125 // CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
126 // CHECK-NEXT:    [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
127 // CHECK-NEXT:    [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 0, i32 0, <4 x i32> undef, <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i1> [[TMP1]])
128 // CHECK-NEXT:    ret <4 x i32> [[TMP2]]
129 //
test_vhcaddq_rot90_x_s32(int32x4_t a,int32x4_t b,mve_pred16_t p)130 int32x4_t test_vhcaddq_rot90_x_s32(int32x4_t a, int32x4_t b, mve_pred16_t p)
131 {
132 #ifdef POLYMORPHIC
133     return vhcaddq_rot90_x(a, b, p);
134 #else
135     return vhcaddq_rot90_x_s32(a, b, p);
136 #endif
137 }
138 
139 // CHECK-LABEL: @test_vhcaddq_rot270_x_s8(
140 // CHECK-NEXT:  entry:
141 // CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
142 // CHECK-NEXT:    [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])
143 // CHECK-NEXT:    [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 0, i32 1, <16 x i8> undef, <16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], <16 x i1> [[TMP1]])
144 // CHECK-NEXT:    ret <16 x i8> [[TMP2]]
145 //
test_vhcaddq_rot270_x_s8(int8x16_t a,int8x16_t b,mve_pred16_t p)146 int8x16_t test_vhcaddq_rot270_x_s8(int8x16_t a, int8x16_t b, mve_pred16_t p)
147 {
148 #ifdef POLYMORPHIC
149     return vhcaddq_rot270_x(a, b, p);
150 #else
151     return vhcaddq_rot270_x_s8(a, b, p);
152 #endif
153 }
154 
155 // CHECK-LABEL: @test_vhcaddq_rot270_x_s16(
156 // CHECK-NEXT:  entry:
157 // CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
158 // CHECK-NEXT:    [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
159 // CHECK-NEXT:    [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 0, i32 1, <8 x i16> undef, <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], <8 x i1> [[TMP1]])
160 // CHECK-NEXT:    ret <8 x i16> [[TMP2]]
161 //
test_vhcaddq_rot270_x_s16(int16x8_t a,int16x8_t b,mve_pred16_t p)162 int16x8_t test_vhcaddq_rot270_x_s16(int16x8_t a, int16x8_t b, mve_pred16_t p)
163 {
164 #ifdef POLYMORPHIC
165     return vhcaddq_rot270_x(a, b, p);
166 #else
167     return vhcaddq_rot270_x_s16(a, b, p);
168 #endif
169 }
170 
171 // CHECK-LABEL: @test_vhcaddq_rot270_x_s32(
172 // CHECK-NEXT:  entry:
173 // CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
174 // CHECK-NEXT:    [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
175 // CHECK-NEXT:    [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 0, i32 1, <4 x i32> undef, <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i1> [[TMP1]])
176 // CHECK-NEXT:    ret <4 x i32> [[TMP2]]
177 //
test_vhcaddq_rot270_x_s32(int32x4_t a,int32x4_t b,mve_pred16_t p)178 int32x4_t test_vhcaddq_rot270_x_s32(int32x4_t a, int32x4_t b, mve_pred16_t p)
179 {
180 #ifdef POLYMORPHIC
181     return vhcaddq_rot270_x(a, b, p);
182 #else
183     return vhcaddq_rot270_x_s32(a, b, p);
184 #endif
185 }
186 
187 // CHECK-LABEL: @test_vhcaddq_rot90_m_s8(
188 // CHECK-NEXT:  entry:
189 // CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
190 // CHECK-NEXT:    [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])
191 // CHECK-NEXT:    [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 0, i32 0, <16 x i8> [[INACTIVE:%.*]], <16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], <16 x i1> [[TMP1]])
192 // CHECK-NEXT:    ret <16 x i8> [[TMP2]]
193 //
test_vhcaddq_rot90_m_s8(int8x16_t inactive,int8x16_t a,int8x16_t b,mve_pred16_t p)194 int8x16_t test_vhcaddq_rot90_m_s8(int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
195 {
196 #ifdef POLYMORPHIC
197     return vhcaddq_rot90_m(inactive, a, b, p);
198 #else
199     return vhcaddq_rot90_m_s8(inactive, a, b, p);
200 #endif
201 }
202 
203 // CHECK-LABEL: @test_vhcaddq_rot90_m_s16(
204 // CHECK-NEXT:  entry:
205 // CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
206 // CHECK-NEXT:    [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
207 // CHECK-NEXT:    [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 0, i32 0, <8 x i16> [[INACTIVE:%.*]], <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], <8 x i1> [[TMP1]])
208 // CHECK-NEXT:    ret <8 x i16> [[TMP2]]
209 //
test_vhcaddq_rot90_m_s16(int16x8_t inactive,int16x8_t a,int16x8_t b,mve_pred16_t p)210 int16x8_t test_vhcaddq_rot90_m_s16(int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
211 {
212 #ifdef POLYMORPHIC
213     return vhcaddq_rot90_m(inactive, a, b, p);
214 #else
215     return vhcaddq_rot90_m_s16(inactive, a, b, p);
216 #endif
217 }
218 
219 // CHECK-LABEL: @test_vhcaddq_rot90_m_s32(
220 // CHECK-NEXT:  entry:
221 // CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
222 // CHECK-NEXT:    [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
223 // CHECK-NEXT:    [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 0, i32 0, <4 x i32> [[INACTIVE:%.*]], <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i1> [[TMP1]])
224 // CHECK-NEXT:    ret <4 x i32> [[TMP2]]
225 //
test_vhcaddq_rot90_m_s32(int32x4_t inactive,int32x4_t a,int32x4_t b,mve_pred16_t p)226 int32x4_t test_vhcaddq_rot90_m_s32(int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
227 {
228 #ifdef POLYMORPHIC
229     return vhcaddq_rot90_m(inactive, a, b, p);
230 #else
231     return vhcaddq_rot90_m_s32(inactive, a, b, p);
232 #endif
233 }
234 
235 // CHECK-LABEL: @test_vhcaddq_rot270_m_s8(
236 // CHECK-NEXT:  entry:
237 // CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
238 // CHECK-NEXT:    [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])
239 // CHECK-NEXT:    [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 0, i32 1, <16 x i8> [[INACTIVE:%.*]], <16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], <16 x i1> [[TMP1]])
240 // CHECK-NEXT:    ret <16 x i8> [[TMP2]]
241 //
test_vhcaddq_rot270_m_s8(int8x16_t inactive,int8x16_t a,int8x16_t b,mve_pred16_t p)242 int8x16_t test_vhcaddq_rot270_m_s8(int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
243 {
244 #ifdef POLYMORPHIC
245     return vhcaddq_rot270_m(inactive, a, b, p);
246 #else
247     return vhcaddq_rot270_m_s8(inactive, a, b, p);
248 #endif
249 }
250 
251 // CHECK-LABEL: @test_vhcaddq_rot270_m_s16(
252 // CHECK-NEXT:  entry:
253 // CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
254 // CHECK-NEXT:    [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
255 // CHECK-NEXT:    [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vcaddq.predicated.v8i16.v8i1(i32 0, i32 1, <8 x i16> [[INACTIVE:%.*]], <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], <8 x i1> [[TMP1]])
256 // CHECK-NEXT:    ret <8 x i16> [[TMP2]]
257 //
test_vhcaddq_rot270_m_s16(int16x8_t inactive,int16x8_t a,int16x8_t b,mve_pred16_t p)258 int16x8_t test_vhcaddq_rot270_m_s16(int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p)
259 {
260 #ifdef POLYMORPHIC
261     return vhcaddq_rot270_m(inactive, a, b, p);
262 #else
263     return vhcaddq_rot270_m_s16(inactive, a, b, p);
264 #endif
265 }
266 
267 // CHECK-LABEL: @test_vhcaddq_rot270_m_s32(
268 // CHECK-NEXT:  entry:
269 // CHECK-NEXT:    [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
270 // CHECK-NEXT:    [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
271 // CHECK-NEXT:    [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vcaddq.predicated.v4i32.v4i1(i32 0, i32 1, <4 x i32> [[INACTIVE:%.*]], <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i1> [[TMP1]])
272 // CHECK-NEXT:    ret <4 x i32> [[TMP2]]
273 //
test_vhcaddq_rot270_m_s32(int32x4_t inactive,int32x4_t a,int32x4_t b,mve_pred16_t p)274 int32x4_t test_vhcaddq_rot270_m_s32(int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
275 {
276 #ifdef POLYMORPHIC
277     return vhcaddq_rot270_m(inactive, a, b, p);
278 #else
279     return vhcaddq_rot270_m_s32(inactive, a, b, p);
280 #endif
281 }
282