1 //===- AArch64AsmPrinter.cpp - AArch64 LLVM assembly writer ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains a printer that converts from our internal representation
10 // of machine-dependent LLVM code to the AArch64 assembly language.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "AArch64.h"
15 #include "AArch64MCInstLower.h"
16 #include "AArch64MachineFunctionInfo.h"
17 #include "AArch64RegisterInfo.h"
18 #include "AArch64Subtarget.h"
19 #include "AArch64TargetObjectFile.h"
20 #include "MCTargetDesc/AArch64AddressingModes.h"
21 #include "MCTargetDesc/AArch64InstPrinter.h"
22 #include "MCTargetDesc/AArch64MCExpr.h"
23 #include "MCTargetDesc/AArch64MCTargetDesc.h"
24 #include "MCTargetDesc/AArch64TargetStreamer.h"
25 #include "TargetInfo/AArch64TargetInfo.h"
26 #include "Utils/AArch64BaseInfo.h"
27 #include "llvm/ADT/SmallString.h"
28 #include "llvm/ADT/SmallVector.h"
29 #include "llvm/ADT/StringRef.h"
30 #include "llvm/ADT/Triple.h"
31 #include "llvm/ADT/Twine.h"
32 #include "llvm/BinaryFormat/COFF.h"
33 #include "llvm/BinaryFormat/ELF.h"
34 #include "llvm/CodeGen/AsmPrinter.h"
35 #include "llvm/CodeGen/FaultMaps.h"
36 #include "llvm/CodeGen/MachineBasicBlock.h"
37 #include "llvm/CodeGen/MachineFunction.h"
38 #include "llvm/CodeGen/MachineInstr.h"
39 #include "llvm/CodeGen/MachineJumpTableInfo.h"
40 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
41 #include "llvm/CodeGen/MachineOperand.h"
42 #include "llvm/CodeGen/StackMaps.h"
43 #include "llvm/CodeGen/TargetRegisterInfo.h"
44 #include "llvm/IR/DataLayout.h"
45 #include "llvm/IR/DebugInfoMetadata.h"
46 #include "llvm/MC/MCAsmInfo.h"
47 #include "llvm/MC/MCContext.h"
48 #include "llvm/MC/MCInst.h"
49 #include "llvm/MC/MCInstBuilder.h"
50 #include "llvm/MC/MCSectionELF.h"
51 #include "llvm/MC/MCStreamer.h"
52 #include "llvm/MC/MCSymbol.h"
53 #include "llvm/Support/Casting.h"
54 #include "llvm/Support/ErrorHandling.h"
55 #include "llvm/Support/TargetRegistry.h"
56 #include "llvm/Support/raw_ostream.h"
57 #include "llvm/Target/TargetMachine.h"
58 #include "llvm/Transforms/Instrumentation/HWAddressSanitizer.h"
59 #include <algorithm>
60 #include <cassert>
61 #include <cstdint>
62 #include <map>
63 #include <memory>
64
65 using namespace llvm;
66
67 #define DEBUG_TYPE "asm-printer"
68
69 namespace {
70
71 class AArch64AsmPrinter : public AsmPrinter {
72 AArch64MCInstLower MCInstLowering;
73 StackMaps SM;
74 FaultMaps FM;
75 const AArch64Subtarget *STI;
76
77 public:
AArch64AsmPrinter(TargetMachine & TM,std::unique_ptr<MCStreamer> Streamer)78 AArch64AsmPrinter(TargetMachine &TM, std::unique_ptr<MCStreamer> Streamer)
79 : AsmPrinter(TM, std::move(Streamer)), MCInstLowering(OutContext, *this),
80 SM(*this), FM(*this) {}
81
getPassName() const82 StringRef getPassName() const override { return "AArch64 Assembly Printer"; }
83
84 /// Wrapper for MCInstLowering.lowerOperand() for the
85 /// tblgen'erated pseudo lowering.
lowerOperand(const MachineOperand & MO,MCOperand & MCOp) const86 bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const {
87 return MCInstLowering.lowerOperand(MO, MCOp);
88 }
89
90 void emitStartOfAsmFile(Module &M) override;
91 void emitJumpTableInfo() override;
92
93 void emitFunctionEntryLabel() override;
94
95 void LowerJumpTableDest(MCStreamer &OutStreamer, const MachineInstr &MI);
96
97 void LowerSTACKMAP(MCStreamer &OutStreamer, StackMaps &SM,
98 const MachineInstr &MI);
99 void LowerPATCHPOINT(MCStreamer &OutStreamer, StackMaps &SM,
100 const MachineInstr &MI);
101 void LowerSTATEPOINT(MCStreamer &OutStreamer, StackMaps &SM,
102 const MachineInstr &MI);
103 void LowerFAULTING_OP(const MachineInstr &MI);
104
105 void LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI);
106 void LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr &MI);
107 void LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI);
108
109 typedef std::tuple<unsigned, bool, uint32_t> HwasanMemaccessTuple;
110 std::map<HwasanMemaccessTuple, MCSymbol *> HwasanMemaccessSymbols;
111 void LowerHWASAN_CHECK_MEMACCESS(const MachineInstr &MI);
112 void EmitHwasanMemaccessSymbols(Module &M);
113
114 void EmitSled(const MachineInstr &MI, SledKind Kind);
115
116 /// tblgen'erated driver function for lowering simple MI->MC
117 /// pseudo instructions.
118 bool emitPseudoExpansionLowering(MCStreamer &OutStreamer,
119 const MachineInstr *MI);
120
121 void emitInstruction(const MachineInstr *MI) override;
122
123 void emitFunctionHeaderComment() override;
124
getAnalysisUsage(AnalysisUsage & AU) const125 void getAnalysisUsage(AnalysisUsage &AU) const override {
126 AsmPrinter::getAnalysisUsage(AU);
127 AU.setPreservesAll();
128 }
129
runOnMachineFunction(MachineFunction & MF)130 bool runOnMachineFunction(MachineFunction &MF) override {
131 AArch64FI = MF.getInfo<AArch64FunctionInfo>();
132 STI = static_cast<const AArch64Subtarget*>(&MF.getSubtarget());
133
134 SetupMachineFunction(MF);
135
136 if (STI->isTargetCOFF()) {
137 bool Internal = MF.getFunction().hasInternalLinkage();
138 COFF::SymbolStorageClass Scl = Internal ? COFF::IMAGE_SYM_CLASS_STATIC
139 : COFF::IMAGE_SYM_CLASS_EXTERNAL;
140 int Type =
141 COFF::IMAGE_SYM_DTYPE_FUNCTION << COFF::SCT_COMPLEX_TYPE_SHIFT;
142
143 OutStreamer->BeginCOFFSymbolDef(CurrentFnSym);
144 OutStreamer->EmitCOFFSymbolStorageClass(Scl);
145 OutStreamer->EmitCOFFSymbolType(Type);
146 OutStreamer->EndCOFFSymbolDef();
147 }
148
149 // Emit the rest of the function body.
150 emitFunctionBody();
151
152 // Emit the XRay table for this function.
153 emitXRayTable();
154
155 // We didn't modify anything.
156 return false;
157 }
158
159 private:
160 void printOperand(const MachineInstr *MI, unsigned OpNum, raw_ostream &O);
161 bool printAsmMRegister(const MachineOperand &MO, char Mode, raw_ostream &O);
162 bool printAsmRegInClass(const MachineOperand &MO,
163 const TargetRegisterClass *RC, unsigned AltName,
164 raw_ostream &O);
165
166 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
167 const char *ExtraCode, raw_ostream &O) override;
168 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
169 const char *ExtraCode, raw_ostream &O) override;
170
171 void PrintDebugValueComment(const MachineInstr *MI, raw_ostream &OS);
172
173 void emitFunctionBodyEnd() override;
174
175 MCSymbol *GetCPISymbol(unsigned CPID) const override;
176 void emitEndOfAsmFile(Module &M) override;
177
178 AArch64FunctionInfo *AArch64FI = nullptr;
179
180 /// Emit the LOHs contained in AArch64FI.
181 void EmitLOHs();
182
183 /// Emit instruction to set float register to zero.
184 void EmitFMov0(const MachineInstr &MI);
185
186 using MInstToMCSymbol = std::map<const MachineInstr *, MCSymbol *>;
187
188 MInstToMCSymbol LOHInstToLabel;
189 };
190
191 } // end anonymous namespace
192
emitStartOfAsmFile(Module & M)193 void AArch64AsmPrinter::emitStartOfAsmFile(Module &M) {
194 if (!TM.getTargetTriple().isOSBinFormatELF())
195 return;
196
197 // Assemble feature flags that may require creation of a note section.
198 unsigned Flags = 0;
199 if (const auto *BTE = mdconst::extract_or_null<ConstantInt>(
200 M.getModuleFlag("branch-target-enforcement")))
201 if (BTE->getZExtValue())
202 Flags |= ELF::GNU_PROPERTY_AARCH64_FEATURE_1_BTI;
203
204 if (const auto *Sign = mdconst::extract_or_null<ConstantInt>(
205 M.getModuleFlag("sign-return-address")))
206 if (Sign->getZExtValue())
207 Flags |= ELF::GNU_PROPERTY_AARCH64_FEATURE_1_PAC;
208
209 if (Flags == 0)
210 return;
211
212 // Emit a .note.gnu.property section with the flags.
213 if (auto *TS = static_cast<AArch64TargetStreamer *>(
214 OutStreamer->getTargetStreamer()))
215 TS->emitNoteSection(Flags);
216 }
217
emitFunctionHeaderComment()218 void AArch64AsmPrinter::emitFunctionHeaderComment() {
219 const AArch64FunctionInfo *FI = MF->getInfo<AArch64FunctionInfo>();
220 Optional<std::string> OutlinerString = FI->getOutliningStyle();
221 if (OutlinerString != None)
222 OutStreamer->GetCommentOS() << ' ' << OutlinerString;
223 }
224
LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr & MI)225 void AArch64AsmPrinter::LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI)
226 {
227 const Function &F = MF->getFunction();
228 if (F.hasFnAttribute("patchable-function-entry")) {
229 unsigned Num;
230 if (F.getFnAttribute("patchable-function-entry")
231 .getValueAsString()
232 .getAsInteger(10, Num))
233 return;
234 emitNops(Num);
235 return;
236 }
237
238 EmitSled(MI, SledKind::FUNCTION_ENTER);
239 }
240
LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr & MI)241 void AArch64AsmPrinter::LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr &MI)
242 {
243 EmitSled(MI, SledKind::FUNCTION_EXIT);
244 }
245
LowerPATCHABLE_TAIL_CALL(const MachineInstr & MI)246 void AArch64AsmPrinter::LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI)
247 {
248 EmitSled(MI, SledKind::TAIL_CALL);
249 }
250
EmitSled(const MachineInstr & MI,SledKind Kind)251 void AArch64AsmPrinter::EmitSled(const MachineInstr &MI, SledKind Kind)
252 {
253 static const int8_t NoopsInSledCount = 7;
254 // We want to emit the following pattern:
255 //
256 // .Lxray_sled_N:
257 // ALIGN
258 // B #32
259 // ; 7 NOP instructions (28 bytes)
260 // .tmpN
261 //
262 // We need the 28 bytes (7 instructions) because at runtime, we'd be patching
263 // over the full 32 bytes (8 instructions) with the following pattern:
264 //
265 // STP X0, X30, [SP, #-16]! ; push X0 and the link register to the stack
266 // LDR W0, #12 ; W0 := function ID
267 // LDR X16,#12 ; X16 := addr of __xray_FunctionEntry or __xray_FunctionExit
268 // BLR X16 ; call the tracing trampoline
269 // ;DATA: 32 bits of function ID
270 // ;DATA: lower 32 bits of the address of the trampoline
271 // ;DATA: higher 32 bits of the address of the trampoline
272 // LDP X0, X30, [SP], #16 ; pop X0 and the link register from the stack
273 //
274 OutStreamer->emitCodeAlignment(4);
275 auto CurSled = OutContext.createTempSymbol("xray_sled_", true);
276 OutStreamer->emitLabel(CurSled);
277 auto Target = OutContext.createTempSymbol();
278
279 // Emit "B #32" instruction, which jumps over the next 28 bytes.
280 // The operand has to be the number of 4-byte instructions to jump over,
281 // including the current instruction.
282 EmitToStreamer(*OutStreamer, MCInstBuilder(AArch64::B).addImm(8));
283
284 for (int8_t I = 0; I < NoopsInSledCount; I++)
285 EmitToStreamer(*OutStreamer, MCInstBuilder(AArch64::HINT).addImm(0));
286
287 OutStreamer->emitLabel(Target);
288 recordSled(CurSled, MI, Kind, 2);
289 }
290
LowerHWASAN_CHECK_MEMACCESS(const MachineInstr & MI)291 void AArch64AsmPrinter::LowerHWASAN_CHECK_MEMACCESS(const MachineInstr &MI) {
292 Register Reg = MI.getOperand(0).getReg();
293 bool IsShort =
294 MI.getOpcode() == AArch64::HWASAN_CHECK_MEMACCESS_SHORTGRANULES;
295 uint32_t AccessInfo = MI.getOperand(1).getImm();
296 MCSymbol *&Sym =
297 HwasanMemaccessSymbols[HwasanMemaccessTuple(Reg, IsShort, AccessInfo)];
298 if (!Sym) {
299 // FIXME: Make this work on non-ELF.
300 if (!TM.getTargetTriple().isOSBinFormatELF())
301 report_fatal_error("llvm.hwasan.check.memaccess only supported on ELF");
302
303 std::string SymName = "__hwasan_check_x" + utostr(Reg - AArch64::X0) + "_" +
304 utostr(AccessInfo);
305 if (IsShort)
306 SymName += "_short_v2";
307 Sym = OutContext.getOrCreateSymbol(SymName);
308 }
309
310 EmitToStreamer(*OutStreamer,
311 MCInstBuilder(AArch64::BL)
312 .addExpr(MCSymbolRefExpr::create(Sym, OutContext)));
313 }
314
EmitHwasanMemaccessSymbols(Module & M)315 void AArch64AsmPrinter::EmitHwasanMemaccessSymbols(Module &M) {
316 if (HwasanMemaccessSymbols.empty())
317 return;
318
319 const Triple &TT = TM.getTargetTriple();
320 assert(TT.isOSBinFormatELF());
321 std::unique_ptr<MCSubtargetInfo> STI(
322 TM.getTarget().createMCSubtargetInfo(TT.str(), "", ""));
323
324 MCSymbol *HwasanTagMismatchV1Sym =
325 OutContext.getOrCreateSymbol("__hwasan_tag_mismatch");
326 MCSymbol *HwasanTagMismatchV2Sym =
327 OutContext.getOrCreateSymbol("__hwasan_tag_mismatch_v2");
328
329 const MCSymbolRefExpr *HwasanTagMismatchV1Ref =
330 MCSymbolRefExpr::create(HwasanTagMismatchV1Sym, OutContext);
331 const MCSymbolRefExpr *HwasanTagMismatchV2Ref =
332 MCSymbolRefExpr::create(HwasanTagMismatchV2Sym, OutContext);
333
334 for (auto &P : HwasanMemaccessSymbols) {
335 unsigned Reg = std::get<0>(P.first);
336 bool IsShort = std::get<1>(P.first);
337 uint32_t AccessInfo = std::get<2>(P.first);
338 const MCSymbolRefExpr *HwasanTagMismatchRef =
339 IsShort ? HwasanTagMismatchV2Ref : HwasanTagMismatchV1Ref;
340 MCSymbol *Sym = P.second;
341
342 bool HasMatchAllTag =
343 (AccessInfo >> HWASanAccessInfo::HasMatchAllShift) & 1;
344 uint8_t MatchAllTag =
345 (AccessInfo >> HWASanAccessInfo::MatchAllShift) & 0xff;
346 unsigned Size =
347 1 << ((AccessInfo >> HWASanAccessInfo::AccessSizeShift) & 0xf);
348 bool CompileKernel =
349 (AccessInfo >> HWASanAccessInfo::CompileKernelShift) & 1;
350
351 OutStreamer->SwitchSection(OutContext.getELFSection(
352 ".text.hot", ELF::SHT_PROGBITS,
353 ELF::SHF_EXECINSTR | ELF::SHF_ALLOC | ELF::SHF_GROUP, 0,
354 Sym->getName()));
355
356 OutStreamer->emitSymbolAttribute(Sym, MCSA_ELF_TypeFunction);
357 OutStreamer->emitSymbolAttribute(Sym, MCSA_Weak);
358 OutStreamer->emitSymbolAttribute(Sym, MCSA_Hidden);
359 OutStreamer->emitLabel(Sym);
360
361 OutStreamer->emitInstruction(MCInstBuilder(AArch64::SBFMXri)
362 .addReg(AArch64::X16)
363 .addReg(Reg)
364 .addImm(4)
365 .addImm(55),
366 *STI);
367 OutStreamer->emitInstruction(
368 MCInstBuilder(AArch64::LDRBBroX)
369 .addReg(AArch64::W16)
370 .addReg(IsShort ? AArch64::X20 : AArch64::X9)
371 .addReg(AArch64::X16)
372 .addImm(0)
373 .addImm(0),
374 *STI);
375 OutStreamer->emitInstruction(
376 MCInstBuilder(AArch64::SUBSXrs)
377 .addReg(AArch64::XZR)
378 .addReg(AArch64::X16)
379 .addReg(Reg)
380 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSR, 56)),
381 *STI);
382 MCSymbol *HandleMismatchOrPartialSym = OutContext.createTempSymbol();
383 OutStreamer->emitInstruction(
384 MCInstBuilder(AArch64::Bcc)
385 .addImm(AArch64CC::NE)
386 .addExpr(MCSymbolRefExpr::create(HandleMismatchOrPartialSym,
387 OutContext)),
388 *STI);
389 MCSymbol *ReturnSym = OutContext.createTempSymbol();
390 OutStreamer->emitLabel(ReturnSym);
391 OutStreamer->emitInstruction(
392 MCInstBuilder(AArch64::RET).addReg(AArch64::LR), *STI);
393 OutStreamer->emitLabel(HandleMismatchOrPartialSym);
394
395 if (HasMatchAllTag) {
396 OutStreamer->emitInstruction(MCInstBuilder(AArch64::UBFMXri)
397 .addReg(AArch64::X16)
398 .addReg(Reg)
399 .addImm(56)
400 .addImm(63),
401 *STI);
402 OutStreamer->emitInstruction(MCInstBuilder(AArch64::SUBSXri)
403 .addReg(AArch64::XZR)
404 .addReg(AArch64::X16)
405 .addImm(MatchAllTag)
406 .addImm(0),
407 *STI);
408 OutStreamer->emitInstruction(
409 MCInstBuilder(AArch64::Bcc)
410 .addImm(AArch64CC::EQ)
411 .addExpr(MCSymbolRefExpr::create(ReturnSym, OutContext)),
412 *STI);
413 }
414
415 if (IsShort) {
416 OutStreamer->emitInstruction(MCInstBuilder(AArch64::SUBSWri)
417 .addReg(AArch64::WZR)
418 .addReg(AArch64::W16)
419 .addImm(15)
420 .addImm(0),
421 *STI);
422 MCSymbol *HandleMismatchSym = OutContext.createTempSymbol();
423 OutStreamer->emitInstruction(
424 MCInstBuilder(AArch64::Bcc)
425 .addImm(AArch64CC::HI)
426 .addExpr(MCSymbolRefExpr::create(HandleMismatchSym, OutContext)),
427 *STI);
428
429 OutStreamer->emitInstruction(
430 MCInstBuilder(AArch64::ANDXri)
431 .addReg(AArch64::X17)
432 .addReg(Reg)
433 .addImm(AArch64_AM::encodeLogicalImmediate(0xf, 64)),
434 *STI);
435 if (Size != 1)
436 OutStreamer->emitInstruction(MCInstBuilder(AArch64::ADDXri)
437 .addReg(AArch64::X17)
438 .addReg(AArch64::X17)
439 .addImm(Size - 1)
440 .addImm(0),
441 *STI);
442 OutStreamer->emitInstruction(MCInstBuilder(AArch64::SUBSWrs)
443 .addReg(AArch64::WZR)
444 .addReg(AArch64::W16)
445 .addReg(AArch64::W17)
446 .addImm(0),
447 *STI);
448 OutStreamer->emitInstruction(
449 MCInstBuilder(AArch64::Bcc)
450 .addImm(AArch64CC::LS)
451 .addExpr(MCSymbolRefExpr::create(HandleMismatchSym, OutContext)),
452 *STI);
453
454 OutStreamer->emitInstruction(
455 MCInstBuilder(AArch64::ORRXri)
456 .addReg(AArch64::X16)
457 .addReg(Reg)
458 .addImm(AArch64_AM::encodeLogicalImmediate(0xf, 64)),
459 *STI);
460 OutStreamer->emitInstruction(MCInstBuilder(AArch64::LDRBBui)
461 .addReg(AArch64::W16)
462 .addReg(AArch64::X16)
463 .addImm(0),
464 *STI);
465 OutStreamer->emitInstruction(
466 MCInstBuilder(AArch64::SUBSXrs)
467 .addReg(AArch64::XZR)
468 .addReg(AArch64::X16)
469 .addReg(Reg)
470 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSR, 56)),
471 *STI);
472 OutStreamer->emitInstruction(
473 MCInstBuilder(AArch64::Bcc)
474 .addImm(AArch64CC::EQ)
475 .addExpr(MCSymbolRefExpr::create(ReturnSym, OutContext)),
476 *STI);
477
478 OutStreamer->emitLabel(HandleMismatchSym);
479 }
480
481 OutStreamer->emitInstruction(MCInstBuilder(AArch64::STPXpre)
482 .addReg(AArch64::SP)
483 .addReg(AArch64::X0)
484 .addReg(AArch64::X1)
485 .addReg(AArch64::SP)
486 .addImm(-32),
487 *STI);
488 OutStreamer->emitInstruction(MCInstBuilder(AArch64::STPXi)
489 .addReg(AArch64::FP)
490 .addReg(AArch64::LR)
491 .addReg(AArch64::SP)
492 .addImm(29),
493 *STI);
494
495 if (Reg != AArch64::X0)
496 OutStreamer->emitInstruction(MCInstBuilder(AArch64::ORRXrs)
497 .addReg(AArch64::X0)
498 .addReg(AArch64::XZR)
499 .addReg(Reg)
500 .addImm(0),
501 *STI);
502 OutStreamer->emitInstruction(
503 MCInstBuilder(AArch64::MOVZXi)
504 .addReg(AArch64::X1)
505 .addImm(AccessInfo & HWASanAccessInfo::RuntimeMask)
506 .addImm(0),
507 *STI);
508
509 if (CompileKernel) {
510 // The Linux kernel's dynamic loader doesn't support GOT relative
511 // relocations, but it doesn't support late binding either, so just call
512 // the function directly.
513 OutStreamer->emitInstruction(
514 MCInstBuilder(AArch64::B).addExpr(HwasanTagMismatchRef), *STI);
515 } else {
516 // Intentionally load the GOT entry and branch to it, rather than possibly
517 // late binding the function, which may clobber the registers before we
518 // have a chance to save them.
519 OutStreamer->emitInstruction(
520 MCInstBuilder(AArch64::ADRP)
521 .addReg(AArch64::X16)
522 .addExpr(AArch64MCExpr::create(
523 HwasanTagMismatchRef, AArch64MCExpr::VariantKind::VK_GOT_PAGE,
524 OutContext)),
525 *STI);
526 OutStreamer->emitInstruction(
527 MCInstBuilder(AArch64::LDRXui)
528 .addReg(AArch64::X16)
529 .addReg(AArch64::X16)
530 .addExpr(AArch64MCExpr::create(
531 HwasanTagMismatchRef, AArch64MCExpr::VariantKind::VK_GOT_LO12,
532 OutContext)),
533 *STI);
534 OutStreamer->emitInstruction(
535 MCInstBuilder(AArch64::BR).addReg(AArch64::X16), *STI);
536 }
537 }
538 }
539
emitEndOfAsmFile(Module & M)540 void AArch64AsmPrinter::emitEndOfAsmFile(Module &M) {
541 EmitHwasanMemaccessSymbols(M);
542
543 const Triple &TT = TM.getTargetTriple();
544 if (TT.isOSBinFormatMachO()) {
545 // Funny Darwin hack: This flag tells the linker that no global symbols
546 // contain code that falls through to other global symbols (e.g. the obvious
547 // implementation of multiple entry points). If this doesn't occur, the
548 // linker can safely perform dead code stripping. Since LLVM never
549 // generates code that does this, it is always safe to set.
550 OutStreamer->emitAssemblerFlag(MCAF_SubsectionsViaSymbols);
551 }
552
553 // Emit stack and fault map information.
554 emitStackMaps(SM);
555 FM.serializeToFaultMapSection();
556
557 }
558
EmitLOHs()559 void AArch64AsmPrinter::EmitLOHs() {
560 SmallVector<MCSymbol *, 3> MCArgs;
561
562 for (const auto &D : AArch64FI->getLOHContainer()) {
563 for (const MachineInstr *MI : D.getArgs()) {
564 MInstToMCSymbol::iterator LabelIt = LOHInstToLabel.find(MI);
565 assert(LabelIt != LOHInstToLabel.end() &&
566 "Label hasn't been inserted for LOH related instruction");
567 MCArgs.push_back(LabelIt->second);
568 }
569 OutStreamer->emitLOHDirective(D.getKind(), MCArgs);
570 MCArgs.clear();
571 }
572 }
573
emitFunctionBodyEnd()574 void AArch64AsmPrinter::emitFunctionBodyEnd() {
575 if (!AArch64FI->getLOHRelated().empty())
576 EmitLOHs();
577 }
578
579 /// GetCPISymbol - Return the symbol for the specified constant pool entry.
GetCPISymbol(unsigned CPID) const580 MCSymbol *AArch64AsmPrinter::GetCPISymbol(unsigned CPID) const {
581 // Darwin uses a linker-private symbol name for constant-pools (to
582 // avoid addends on the relocation?), ELF has no such concept and
583 // uses a normal private symbol.
584 if (!getDataLayout().getLinkerPrivateGlobalPrefix().empty())
585 return OutContext.getOrCreateSymbol(
586 Twine(getDataLayout().getLinkerPrivateGlobalPrefix()) + "CPI" +
587 Twine(getFunctionNumber()) + "_" + Twine(CPID));
588
589 return AsmPrinter::GetCPISymbol(CPID);
590 }
591
printOperand(const MachineInstr * MI,unsigned OpNum,raw_ostream & O)592 void AArch64AsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNum,
593 raw_ostream &O) {
594 const MachineOperand &MO = MI->getOperand(OpNum);
595 switch (MO.getType()) {
596 default:
597 llvm_unreachable("<unknown operand type>");
598 case MachineOperand::MO_Register: {
599 Register Reg = MO.getReg();
600 assert(Register::isPhysicalRegister(Reg));
601 assert(!MO.getSubReg() && "Subregs should be eliminated!");
602 O << AArch64InstPrinter::getRegisterName(Reg);
603 break;
604 }
605 case MachineOperand::MO_Immediate: {
606 O << MO.getImm();
607 break;
608 }
609 case MachineOperand::MO_GlobalAddress: {
610 PrintSymbolOperand(MO, O);
611 break;
612 }
613 case MachineOperand::MO_BlockAddress: {
614 MCSymbol *Sym = GetBlockAddressSymbol(MO.getBlockAddress());
615 Sym->print(O, MAI);
616 break;
617 }
618 }
619 }
620
printAsmMRegister(const MachineOperand & MO,char Mode,raw_ostream & O)621 bool AArch64AsmPrinter::printAsmMRegister(const MachineOperand &MO, char Mode,
622 raw_ostream &O) {
623 Register Reg = MO.getReg();
624 switch (Mode) {
625 default:
626 return true; // Unknown mode.
627 case 'w':
628 Reg = getWRegFromXReg(Reg);
629 break;
630 case 'x':
631 Reg = getXRegFromWReg(Reg);
632 break;
633 }
634
635 O << AArch64InstPrinter::getRegisterName(Reg);
636 return false;
637 }
638
639 // Prints the register in MO using class RC using the offset in the
640 // new register class. This should not be used for cross class
641 // printing.
printAsmRegInClass(const MachineOperand & MO,const TargetRegisterClass * RC,unsigned AltName,raw_ostream & O)642 bool AArch64AsmPrinter::printAsmRegInClass(const MachineOperand &MO,
643 const TargetRegisterClass *RC,
644 unsigned AltName, raw_ostream &O) {
645 assert(MO.isReg() && "Should only get here with a register!");
646 const TargetRegisterInfo *RI = STI->getRegisterInfo();
647 Register Reg = MO.getReg();
648 unsigned RegToPrint = RC->getRegister(RI->getEncodingValue(Reg));
649 assert(RI->regsOverlap(RegToPrint, Reg));
650 O << AArch64InstPrinter::getRegisterName(RegToPrint, AltName);
651 return false;
652 }
653
PrintAsmOperand(const MachineInstr * MI,unsigned OpNum,const char * ExtraCode,raw_ostream & O)654 bool AArch64AsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
655 const char *ExtraCode, raw_ostream &O) {
656 const MachineOperand &MO = MI->getOperand(OpNum);
657
658 // First try the generic code, which knows about modifiers like 'c' and 'n'.
659 if (!AsmPrinter::PrintAsmOperand(MI, OpNum, ExtraCode, O))
660 return false;
661
662 // Does this asm operand have a single letter operand modifier?
663 if (ExtraCode && ExtraCode[0]) {
664 if (ExtraCode[1] != 0)
665 return true; // Unknown modifier.
666
667 switch (ExtraCode[0]) {
668 default:
669 return true; // Unknown modifier.
670 case 'w': // Print W register
671 case 'x': // Print X register
672 if (MO.isReg())
673 return printAsmMRegister(MO, ExtraCode[0], O);
674 if (MO.isImm() && MO.getImm() == 0) {
675 unsigned Reg = ExtraCode[0] == 'w' ? AArch64::WZR : AArch64::XZR;
676 O << AArch64InstPrinter::getRegisterName(Reg);
677 return false;
678 }
679 printOperand(MI, OpNum, O);
680 return false;
681 case 'b': // Print B register.
682 case 'h': // Print H register.
683 case 's': // Print S register.
684 case 'd': // Print D register.
685 case 'q': // Print Q register.
686 case 'z': // Print Z register.
687 if (MO.isReg()) {
688 const TargetRegisterClass *RC;
689 switch (ExtraCode[0]) {
690 case 'b':
691 RC = &AArch64::FPR8RegClass;
692 break;
693 case 'h':
694 RC = &AArch64::FPR16RegClass;
695 break;
696 case 's':
697 RC = &AArch64::FPR32RegClass;
698 break;
699 case 'd':
700 RC = &AArch64::FPR64RegClass;
701 break;
702 case 'q':
703 RC = &AArch64::FPR128RegClass;
704 break;
705 case 'z':
706 RC = &AArch64::ZPRRegClass;
707 break;
708 default:
709 return true;
710 }
711 return printAsmRegInClass(MO, RC, AArch64::NoRegAltName, O);
712 }
713 printOperand(MI, OpNum, O);
714 return false;
715 }
716 }
717
718 // According to ARM, we should emit x and v registers unless we have a
719 // modifier.
720 if (MO.isReg()) {
721 Register Reg = MO.getReg();
722
723 // If this is a w or x register, print an x register.
724 if (AArch64::GPR32allRegClass.contains(Reg) ||
725 AArch64::GPR64allRegClass.contains(Reg))
726 return printAsmMRegister(MO, 'x', O);
727
728 unsigned AltName = AArch64::NoRegAltName;
729 const TargetRegisterClass *RegClass;
730 if (AArch64::ZPRRegClass.contains(Reg)) {
731 RegClass = &AArch64::ZPRRegClass;
732 } else if (AArch64::PPRRegClass.contains(Reg)) {
733 RegClass = &AArch64::PPRRegClass;
734 } else {
735 RegClass = &AArch64::FPR128RegClass;
736 AltName = AArch64::vreg;
737 }
738
739 // If this is a b, h, s, d, or q register, print it as a v register.
740 return printAsmRegInClass(MO, RegClass, AltName, O);
741 }
742
743 printOperand(MI, OpNum, O);
744 return false;
745 }
746
PrintAsmMemoryOperand(const MachineInstr * MI,unsigned OpNum,const char * ExtraCode,raw_ostream & O)747 bool AArch64AsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
748 unsigned OpNum,
749 const char *ExtraCode,
750 raw_ostream &O) {
751 if (ExtraCode && ExtraCode[0] && ExtraCode[0] != 'a')
752 return true; // Unknown modifier.
753
754 const MachineOperand &MO = MI->getOperand(OpNum);
755 assert(MO.isReg() && "unexpected inline asm memory operand");
756 O << "[" << AArch64InstPrinter::getRegisterName(MO.getReg()) << "]";
757 return false;
758 }
759
PrintDebugValueComment(const MachineInstr * MI,raw_ostream & OS)760 void AArch64AsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
761 raw_ostream &OS) {
762 unsigned NOps = MI->getNumOperands();
763 assert(NOps == 4);
764 OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
765 // cast away const; DIetc do not take const operands for some reason.
766 OS << MI->getDebugVariable()->getName();
767 OS << " <- ";
768 // Frame address. Currently handles register +- offset only.
769 assert(MI->getDebugOperand(0).isReg() && MI->isDebugOffsetImm());
770 OS << '[';
771 printOperand(MI, 0, OS);
772 OS << '+';
773 printOperand(MI, 1, OS);
774 OS << ']';
775 OS << "+";
776 printOperand(MI, NOps - 2, OS);
777 }
778
emitJumpTableInfo()779 void AArch64AsmPrinter::emitJumpTableInfo() {
780 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
781 if (!MJTI) return;
782
783 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
784 if (JT.empty()) return;
785
786 const Function &F = MF->getFunction();
787 const TargetLoweringObjectFile &TLOF = getObjFileLowering();
788 bool JTInDiffSection =
789 !STI->isTargetCOFF() ||
790 !TLOF.shouldPutJumpTableInFunctionSection(
791 MJTI->getEntryKind() == MachineJumpTableInfo::EK_LabelDifference32,
792 F);
793 if (JTInDiffSection) {
794 // Drop it in the readonly section.
795 MCSection *ReadOnlySec = TLOF.getSectionForJumpTable(F, TM);
796 OutStreamer->SwitchSection(ReadOnlySec);
797 }
798
799 auto AFI = MF->getInfo<AArch64FunctionInfo>();
800 for (unsigned JTI = 0, e = JT.size(); JTI != e; ++JTI) {
801 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
802
803 // If this jump table was deleted, ignore it.
804 if (JTBBs.empty()) continue;
805
806 unsigned Size = AFI->getJumpTableEntrySize(JTI);
807 emitAlignment(Align(Size));
808 OutStreamer->emitLabel(GetJTISymbol(JTI));
809
810 const MCSymbol *BaseSym = AArch64FI->getJumpTableEntryPCRelSymbol(JTI);
811 const MCExpr *Base = MCSymbolRefExpr::create(BaseSym, OutContext);
812
813 for (auto *JTBB : JTBBs) {
814 const MCExpr *Value =
815 MCSymbolRefExpr::create(JTBB->getSymbol(), OutContext);
816
817 // Each entry is:
818 // .byte/.hword (LBB - Lbase)>>2
819 // or plain:
820 // .word LBB - Lbase
821 Value = MCBinaryExpr::createSub(Value, Base, OutContext);
822 if (Size != 4)
823 Value = MCBinaryExpr::createLShr(
824 Value, MCConstantExpr::create(2, OutContext), OutContext);
825
826 OutStreamer->emitValue(Value, Size);
827 }
828 }
829 }
830
emitFunctionEntryLabel()831 void AArch64AsmPrinter::emitFunctionEntryLabel() {
832 if (MF->getFunction().getCallingConv() == CallingConv::AArch64_VectorCall ||
833 MF->getFunction().getCallingConv() ==
834 CallingConv::AArch64_SVE_VectorCall ||
835 STI->getRegisterInfo()->hasSVEArgsOrReturn(MF)) {
836 auto *TS =
837 static_cast<AArch64TargetStreamer *>(OutStreamer->getTargetStreamer());
838 TS->emitDirectiveVariantPCS(CurrentFnSym);
839 }
840
841 return AsmPrinter::emitFunctionEntryLabel();
842 }
843
844 /// Small jump tables contain an unsigned byte or half, representing the offset
845 /// from the lowest-addressed possible destination to the desired basic
846 /// block. Since all instructions are 4-byte aligned, this is further compressed
847 /// by counting in instructions rather than bytes (i.e. divided by 4). So, to
848 /// materialize the correct destination we need:
849 ///
850 /// adr xDest, .LBB0_0
851 /// ldrb wScratch, [xTable, xEntry] (with "lsl #1" for ldrh).
852 /// add xDest, xDest, xScratch (with "lsl #2" for smaller entries)
LowerJumpTableDest(llvm::MCStreamer & OutStreamer,const llvm::MachineInstr & MI)853 void AArch64AsmPrinter::LowerJumpTableDest(llvm::MCStreamer &OutStreamer,
854 const llvm::MachineInstr &MI) {
855 Register DestReg = MI.getOperand(0).getReg();
856 Register ScratchReg = MI.getOperand(1).getReg();
857 Register ScratchRegW =
858 STI->getRegisterInfo()->getSubReg(ScratchReg, AArch64::sub_32);
859 Register TableReg = MI.getOperand(2).getReg();
860 Register EntryReg = MI.getOperand(3).getReg();
861 int JTIdx = MI.getOperand(4).getIndex();
862 int Size = AArch64FI->getJumpTableEntrySize(JTIdx);
863
864 // This has to be first because the compression pass based its reachability
865 // calculations on the start of the JumpTableDest instruction.
866 auto Label =
867 MF->getInfo<AArch64FunctionInfo>()->getJumpTableEntryPCRelSymbol(JTIdx);
868
869 // If we don't already have a symbol to use as the base, use the ADR
870 // instruction itself.
871 if (!Label) {
872 Label = MF->getContext().createTempSymbol();
873 AArch64FI->setJumpTableEntryInfo(JTIdx, Size, Label);
874 OutStreamer.emitLabel(Label);
875 }
876
877 auto LabelExpr = MCSymbolRefExpr::create(Label, MF->getContext());
878 EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::ADR)
879 .addReg(DestReg)
880 .addExpr(LabelExpr));
881
882 // Load the number of instruction-steps to offset from the label.
883 unsigned LdrOpcode;
884 switch (Size) {
885 case 1: LdrOpcode = AArch64::LDRBBroX; break;
886 case 2: LdrOpcode = AArch64::LDRHHroX; break;
887 case 4: LdrOpcode = AArch64::LDRSWroX; break;
888 default:
889 llvm_unreachable("Unknown jump table size");
890 }
891
892 EmitToStreamer(OutStreamer, MCInstBuilder(LdrOpcode)
893 .addReg(Size == 4 ? ScratchReg : ScratchRegW)
894 .addReg(TableReg)
895 .addReg(EntryReg)
896 .addImm(0)
897 .addImm(Size == 1 ? 0 : 1));
898
899 // Add to the already materialized base label address, multiplying by 4 if
900 // compressed.
901 EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::ADDXrs)
902 .addReg(DestReg)
903 .addReg(DestReg)
904 .addReg(ScratchReg)
905 .addImm(Size == 4 ? 0 : 2));
906 }
907
LowerSTACKMAP(MCStreamer & OutStreamer,StackMaps & SM,const MachineInstr & MI)908 void AArch64AsmPrinter::LowerSTACKMAP(MCStreamer &OutStreamer, StackMaps &SM,
909 const MachineInstr &MI) {
910 unsigned NumNOPBytes = StackMapOpers(&MI).getNumPatchBytes();
911
912 auto &Ctx = OutStreamer.getContext();
913 MCSymbol *MILabel = Ctx.createTempSymbol();
914 OutStreamer.emitLabel(MILabel);
915
916 SM.recordStackMap(*MILabel, MI);
917 assert(NumNOPBytes % 4 == 0 && "Invalid number of NOP bytes requested!");
918
919 // Scan ahead to trim the shadow.
920 const MachineBasicBlock &MBB = *MI.getParent();
921 MachineBasicBlock::const_iterator MII(MI);
922 ++MII;
923 while (NumNOPBytes > 0) {
924 if (MII == MBB.end() || MII->isCall() ||
925 MII->getOpcode() == AArch64::DBG_VALUE ||
926 MII->getOpcode() == TargetOpcode::PATCHPOINT ||
927 MII->getOpcode() == TargetOpcode::STACKMAP)
928 break;
929 ++MII;
930 NumNOPBytes -= 4;
931 }
932
933 // Emit nops.
934 for (unsigned i = 0; i < NumNOPBytes; i += 4)
935 EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::HINT).addImm(0));
936 }
937
938 // Lower a patchpoint of the form:
939 // [<def>], <id>, <numBytes>, <target>, <numArgs>
LowerPATCHPOINT(MCStreamer & OutStreamer,StackMaps & SM,const MachineInstr & MI)940 void AArch64AsmPrinter::LowerPATCHPOINT(MCStreamer &OutStreamer, StackMaps &SM,
941 const MachineInstr &MI) {
942 auto &Ctx = OutStreamer.getContext();
943 MCSymbol *MILabel = Ctx.createTempSymbol();
944 OutStreamer.emitLabel(MILabel);
945 SM.recordPatchPoint(*MILabel, MI);
946
947 PatchPointOpers Opers(&MI);
948
949 int64_t CallTarget = Opers.getCallTarget().getImm();
950 unsigned EncodedBytes = 0;
951 if (CallTarget) {
952 assert((CallTarget & 0xFFFFFFFFFFFF) == CallTarget &&
953 "High 16 bits of call target should be zero.");
954 Register ScratchReg = MI.getOperand(Opers.getNextScratchIdx()).getReg();
955 EncodedBytes = 16;
956 // Materialize the jump address:
957 EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::MOVZXi)
958 .addReg(ScratchReg)
959 .addImm((CallTarget >> 32) & 0xFFFF)
960 .addImm(32));
961 EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::MOVKXi)
962 .addReg(ScratchReg)
963 .addReg(ScratchReg)
964 .addImm((CallTarget >> 16) & 0xFFFF)
965 .addImm(16));
966 EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::MOVKXi)
967 .addReg(ScratchReg)
968 .addReg(ScratchReg)
969 .addImm(CallTarget & 0xFFFF)
970 .addImm(0));
971 EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::BLR).addReg(ScratchReg));
972 }
973 // Emit padding.
974 unsigned NumBytes = Opers.getNumPatchBytes();
975 assert(NumBytes >= EncodedBytes &&
976 "Patchpoint can't request size less than the length of a call.");
977 assert((NumBytes - EncodedBytes) % 4 == 0 &&
978 "Invalid number of NOP bytes requested!");
979 for (unsigned i = EncodedBytes; i < NumBytes; i += 4)
980 EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::HINT).addImm(0));
981 }
982
LowerSTATEPOINT(MCStreamer & OutStreamer,StackMaps & SM,const MachineInstr & MI)983 void AArch64AsmPrinter::LowerSTATEPOINT(MCStreamer &OutStreamer, StackMaps &SM,
984 const MachineInstr &MI) {
985 StatepointOpers SOpers(&MI);
986 if (unsigned PatchBytes = SOpers.getNumPatchBytes()) {
987 assert(PatchBytes % 4 == 0 && "Invalid number of NOP bytes requested!");
988 for (unsigned i = 0; i < PatchBytes; i += 4)
989 EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::HINT).addImm(0));
990 } else {
991 // Lower call target and choose correct opcode
992 const MachineOperand &CallTarget = SOpers.getCallTarget();
993 MCOperand CallTargetMCOp;
994 unsigned CallOpcode;
995 switch (CallTarget.getType()) {
996 case MachineOperand::MO_GlobalAddress:
997 case MachineOperand::MO_ExternalSymbol:
998 MCInstLowering.lowerOperand(CallTarget, CallTargetMCOp);
999 CallOpcode = AArch64::BL;
1000 break;
1001 case MachineOperand::MO_Immediate:
1002 CallTargetMCOp = MCOperand::createImm(CallTarget.getImm());
1003 CallOpcode = AArch64::BL;
1004 break;
1005 case MachineOperand::MO_Register:
1006 CallTargetMCOp = MCOperand::createReg(CallTarget.getReg());
1007 CallOpcode = AArch64::BLR;
1008 break;
1009 default:
1010 llvm_unreachable("Unsupported operand type in statepoint call target");
1011 break;
1012 }
1013
1014 EmitToStreamer(OutStreamer,
1015 MCInstBuilder(CallOpcode).addOperand(CallTargetMCOp));
1016 }
1017
1018 auto &Ctx = OutStreamer.getContext();
1019 MCSymbol *MILabel = Ctx.createTempSymbol();
1020 OutStreamer.emitLabel(MILabel);
1021 SM.recordStatepoint(*MILabel, MI);
1022 }
1023
LowerFAULTING_OP(const MachineInstr & FaultingMI)1024 void AArch64AsmPrinter::LowerFAULTING_OP(const MachineInstr &FaultingMI) {
1025 // FAULTING_LOAD_OP <def>, <faltinf type>, <MBB handler>,
1026 // <opcode>, <operands>
1027
1028 Register DefRegister = FaultingMI.getOperand(0).getReg();
1029 FaultMaps::FaultKind FK =
1030 static_cast<FaultMaps::FaultKind>(FaultingMI.getOperand(1).getImm());
1031 MCSymbol *HandlerLabel = FaultingMI.getOperand(2).getMBB()->getSymbol();
1032 unsigned Opcode = FaultingMI.getOperand(3).getImm();
1033 unsigned OperandsBeginIdx = 4;
1034
1035 auto &Ctx = OutStreamer->getContext();
1036 MCSymbol *FaultingLabel = Ctx.createTempSymbol();
1037 OutStreamer->emitLabel(FaultingLabel);
1038
1039 assert(FK < FaultMaps::FaultKindMax && "Invalid Faulting Kind!");
1040 FM.recordFaultingOp(FK, FaultingLabel, HandlerLabel);
1041
1042 MCInst MI;
1043 MI.setOpcode(Opcode);
1044
1045 if (DefRegister != (Register)0)
1046 MI.addOperand(MCOperand::createReg(DefRegister));
1047
1048 for (auto I = FaultingMI.operands_begin() + OperandsBeginIdx,
1049 E = FaultingMI.operands_end();
1050 I != E; ++I) {
1051 MCOperand Dest;
1052 lowerOperand(*I, Dest);
1053 MI.addOperand(Dest);
1054 }
1055
1056 OutStreamer->AddComment("on-fault: " + HandlerLabel->getName());
1057 OutStreamer->emitInstruction(MI, getSubtargetInfo());
1058 }
1059
EmitFMov0(const MachineInstr & MI)1060 void AArch64AsmPrinter::EmitFMov0(const MachineInstr &MI) {
1061 Register DestReg = MI.getOperand(0).getReg();
1062 if (STI->hasZeroCycleZeroingFP() && !STI->hasZeroCycleZeroingFPWorkaround()) {
1063 // Convert H/S/D register to corresponding Q register
1064 if (AArch64::H0 <= DestReg && DestReg <= AArch64::H31)
1065 DestReg = AArch64::Q0 + (DestReg - AArch64::H0);
1066 else if (AArch64::S0 <= DestReg && DestReg <= AArch64::S31)
1067 DestReg = AArch64::Q0 + (DestReg - AArch64::S0);
1068 else {
1069 assert(AArch64::D0 <= DestReg && DestReg <= AArch64::D31);
1070 DestReg = AArch64::Q0 + (DestReg - AArch64::D0);
1071 }
1072 MCInst MOVI;
1073 MOVI.setOpcode(AArch64::MOVIv2d_ns);
1074 MOVI.addOperand(MCOperand::createReg(DestReg));
1075 MOVI.addOperand(MCOperand::createImm(0));
1076 EmitToStreamer(*OutStreamer, MOVI);
1077 } else {
1078 MCInst FMov;
1079 switch (MI.getOpcode()) {
1080 default: llvm_unreachable("Unexpected opcode");
1081 case AArch64::FMOVH0:
1082 FMov.setOpcode(AArch64::FMOVWHr);
1083 FMov.addOperand(MCOperand::createReg(DestReg));
1084 FMov.addOperand(MCOperand::createReg(AArch64::WZR));
1085 break;
1086 case AArch64::FMOVS0:
1087 FMov.setOpcode(AArch64::FMOVWSr);
1088 FMov.addOperand(MCOperand::createReg(DestReg));
1089 FMov.addOperand(MCOperand::createReg(AArch64::WZR));
1090 break;
1091 case AArch64::FMOVD0:
1092 FMov.setOpcode(AArch64::FMOVXDr);
1093 FMov.addOperand(MCOperand::createReg(DestReg));
1094 FMov.addOperand(MCOperand::createReg(AArch64::XZR));
1095 break;
1096 }
1097 EmitToStreamer(*OutStreamer, FMov);
1098 }
1099 }
1100
1101 // Simple pseudo-instructions have their lowering (with expansion to real
1102 // instructions) auto-generated.
1103 #include "AArch64GenMCPseudoLowering.inc"
1104
emitInstruction(const MachineInstr * MI)1105 void AArch64AsmPrinter::emitInstruction(const MachineInstr *MI) {
1106 // Do any auto-generated pseudo lowerings.
1107 if (emitPseudoExpansionLowering(*OutStreamer, MI))
1108 return;
1109
1110 if (AArch64FI->getLOHRelated().count(MI)) {
1111 // Generate a label for LOH related instruction
1112 MCSymbol *LOHLabel = createTempSymbol("loh");
1113 // Associate the instruction with the label
1114 LOHInstToLabel[MI] = LOHLabel;
1115 OutStreamer->emitLabel(LOHLabel);
1116 }
1117
1118 AArch64TargetStreamer *TS =
1119 static_cast<AArch64TargetStreamer *>(OutStreamer->getTargetStreamer());
1120 // Do any manual lowerings.
1121 switch (MI->getOpcode()) {
1122 default:
1123 break;
1124 case AArch64::HINT: {
1125 // CurrentPatchableFunctionEntrySym can be CurrentFnBegin only for
1126 // -fpatchable-function-entry=N,0. The entry MBB is guaranteed to be
1127 // non-empty. If MI is the initial BTI, place the
1128 // __patchable_function_entries label after BTI.
1129 if (CurrentPatchableFunctionEntrySym &&
1130 CurrentPatchableFunctionEntrySym == CurrentFnBegin &&
1131 MI == &MF->front().front()) {
1132 int64_t Imm = MI->getOperand(0).getImm();
1133 if ((Imm & 32) && (Imm & 6)) {
1134 MCInst Inst;
1135 MCInstLowering.Lower(MI, Inst);
1136 EmitToStreamer(*OutStreamer, Inst);
1137 CurrentPatchableFunctionEntrySym = createTempSymbol("patch");
1138 OutStreamer->emitLabel(CurrentPatchableFunctionEntrySym);
1139 return;
1140 }
1141 }
1142 break;
1143 }
1144 case AArch64::MOVMCSym: {
1145 Register DestReg = MI->getOperand(0).getReg();
1146 const MachineOperand &MO_Sym = MI->getOperand(1);
1147 MachineOperand Hi_MOSym(MO_Sym), Lo_MOSym(MO_Sym);
1148 MCOperand Hi_MCSym, Lo_MCSym;
1149
1150 Hi_MOSym.setTargetFlags(AArch64II::MO_G1 | AArch64II::MO_S);
1151 Lo_MOSym.setTargetFlags(AArch64II::MO_G0 | AArch64II::MO_NC);
1152
1153 MCInstLowering.lowerOperand(Hi_MOSym, Hi_MCSym);
1154 MCInstLowering.lowerOperand(Lo_MOSym, Lo_MCSym);
1155
1156 MCInst MovZ;
1157 MovZ.setOpcode(AArch64::MOVZXi);
1158 MovZ.addOperand(MCOperand::createReg(DestReg));
1159 MovZ.addOperand(Hi_MCSym);
1160 MovZ.addOperand(MCOperand::createImm(16));
1161 EmitToStreamer(*OutStreamer, MovZ);
1162
1163 MCInst MovK;
1164 MovK.setOpcode(AArch64::MOVKXi);
1165 MovK.addOperand(MCOperand::createReg(DestReg));
1166 MovK.addOperand(MCOperand::createReg(DestReg));
1167 MovK.addOperand(Lo_MCSym);
1168 MovK.addOperand(MCOperand::createImm(0));
1169 EmitToStreamer(*OutStreamer, MovK);
1170 return;
1171 }
1172 case AArch64::MOVIv2d_ns:
1173 // If the target has <rdar://problem/16473581>, lower this
1174 // instruction to movi.16b instead.
1175 if (STI->hasZeroCycleZeroingFPWorkaround() &&
1176 MI->getOperand(1).getImm() == 0) {
1177 MCInst TmpInst;
1178 TmpInst.setOpcode(AArch64::MOVIv16b_ns);
1179 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1180 TmpInst.addOperand(MCOperand::createImm(MI->getOperand(1).getImm()));
1181 EmitToStreamer(*OutStreamer, TmpInst);
1182 return;
1183 }
1184 break;
1185
1186 case AArch64::DBG_VALUE: {
1187 if (isVerbose() && OutStreamer->hasRawTextSupport()) {
1188 SmallString<128> TmpStr;
1189 raw_svector_ostream OS(TmpStr);
1190 PrintDebugValueComment(MI, OS);
1191 OutStreamer->emitRawText(StringRef(OS.str()));
1192 }
1193 return;
1194
1195 case AArch64::EMITBKEY: {
1196 ExceptionHandling ExceptionHandlingType = MAI->getExceptionHandlingType();
1197 if (ExceptionHandlingType != ExceptionHandling::DwarfCFI &&
1198 ExceptionHandlingType != ExceptionHandling::ARM)
1199 return;
1200
1201 if (needsCFIMoves() == CFI_M_None)
1202 return;
1203
1204 OutStreamer->emitCFIBKeyFrame();
1205 return;
1206 }
1207 }
1208
1209 // Tail calls use pseudo instructions so they have the proper code-gen
1210 // attributes (isCall, isReturn, etc.). We lower them to the real
1211 // instruction here.
1212 case AArch64::TCRETURNri:
1213 case AArch64::TCRETURNriBTI:
1214 case AArch64::TCRETURNriALL: {
1215 MCInst TmpInst;
1216 TmpInst.setOpcode(AArch64::BR);
1217 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1218 EmitToStreamer(*OutStreamer, TmpInst);
1219 return;
1220 }
1221 case AArch64::TCRETURNdi: {
1222 MCOperand Dest;
1223 MCInstLowering.lowerOperand(MI->getOperand(0), Dest);
1224 MCInst TmpInst;
1225 TmpInst.setOpcode(AArch64::B);
1226 TmpInst.addOperand(Dest);
1227 EmitToStreamer(*OutStreamer, TmpInst);
1228 return;
1229 }
1230 case AArch64::SpeculationBarrierISBDSBEndBB: {
1231 // Print DSB SYS + ISB
1232 MCInst TmpInstDSB;
1233 TmpInstDSB.setOpcode(AArch64::DSB);
1234 TmpInstDSB.addOperand(MCOperand::createImm(0xf));
1235 EmitToStreamer(*OutStreamer, TmpInstDSB);
1236 MCInst TmpInstISB;
1237 TmpInstISB.setOpcode(AArch64::ISB);
1238 TmpInstISB.addOperand(MCOperand::createImm(0xf));
1239 EmitToStreamer(*OutStreamer, TmpInstISB);
1240 return;
1241 }
1242 case AArch64::SpeculationBarrierSBEndBB: {
1243 // Print SB
1244 MCInst TmpInstSB;
1245 TmpInstSB.setOpcode(AArch64::SB);
1246 EmitToStreamer(*OutStreamer, TmpInstSB);
1247 return;
1248 }
1249 case AArch64::TLSDESC_CALLSEQ: {
1250 /// lower this to:
1251 /// adrp x0, :tlsdesc:var
1252 /// ldr x1, [x0, #:tlsdesc_lo12:var]
1253 /// add x0, x0, #:tlsdesc_lo12:var
1254 /// .tlsdesccall var
1255 /// blr x1
1256 /// (TPIDR_EL0 offset now in x0)
1257 const MachineOperand &MO_Sym = MI->getOperand(0);
1258 MachineOperand MO_TLSDESC_LO12(MO_Sym), MO_TLSDESC(MO_Sym);
1259 MCOperand Sym, SymTLSDescLo12, SymTLSDesc;
1260 MO_TLSDESC_LO12.setTargetFlags(AArch64II::MO_TLS | AArch64II::MO_PAGEOFF);
1261 MO_TLSDESC.setTargetFlags(AArch64II::MO_TLS | AArch64II::MO_PAGE);
1262 MCInstLowering.lowerOperand(MO_Sym, Sym);
1263 MCInstLowering.lowerOperand(MO_TLSDESC_LO12, SymTLSDescLo12);
1264 MCInstLowering.lowerOperand(MO_TLSDESC, SymTLSDesc);
1265
1266 MCInst Adrp;
1267 Adrp.setOpcode(AArch64::ADRP);
1268 Adrp.addOperand(MCOperand::createReg(AArch64::X0));
1269 Adrp.addOperand(SymTLSDesc);
1270 EmitToStreamer(*OutStreamer, Adrp);
1271
1272 MCInst Ldr;
1273 Ldr.setOpcode(AArch64::LDRXui);
1274 Ldr.addOperand(MCOperand::createReg(AArch64::X1));
1275 Ldr.addOperand(MCOperand::createReg(AArch64::X0));
1276 Ldr.addOperand(SymTLSDescLo12);
1277 Ldr.addOperand(MCOperand::createImm(0));
1278 EmitToStreamer(*OutStreamer, Ldr);
1279
1280 MCInst Add;
1281 Add.setOpcode(AArch64::ADDXri);
1282 Add.addOperand(MCOperand::createReg(AArch64::X0));
1283 Add.addOperand(MCOperand::createReg(AArch64::X0));
1284 Add.addOperand(SymTLSDescLo12);
1285 Add.addOperand(MCOperand::createImm(AArch64_AM::getShiftValue(0)));
1286 EmitToStreamer(*OutStreamer, Add);
1287
1288 // Emit a relocation-annotation. This expands to no code, but requests
1289 // the following instruction gets an R_AARCH64_TLSDESC_CALL.
1290 MCInst TLSDescCall;
1291 TLSDescCall.setOpcode(AArch64::TLSDESCCALL);
1292 TLSDescCall.addOperand(Sym);
1293 EmitToStreamer(*OutStreamer, TLSDescCall);
1294
1295 MCInst Blr;
1296 Blr.setOpcode(AArch64::BLR);
1297 Blr.addOperand(MCOperand::createReg(AArch64::X1));
1298 EmitToStreamer(*OutStreamer, Blr);
1299
1300 return;
1301 }
1302
1303 case AArch64::JumpTableDest32:
1304 case AArch64::JumpTableDest16:
1305 case AArch64::JumpTableDest8:
1306 LowerJumpTableDest(*OutStreamer, *MI);
1307 return;
1308
1309 case AArch64::FMOVH0:
1310 case AArch64::FMOVS0:
1311 case AArch64::FMOVD0:
1312 EmitFMov0(*MI);
1313 return;
1314
1315 case TargetOpcode::STACKMAP:
1316 return LowerSTACKMAP(*OutStreamer, SM, *MI);
1317
1318 case TargetOpcode::PATCHPOINT:
1319 return LowerPATCHPOINT(*OutStreamer, SM, *MI);
1320
1321 case TargetOpcode::STATEPOINT:
1322 return LowerSTATEPOINT(*OutStreamer, SM, *MI);
1323
1324 case TargetOpcode::FAULTING_OP:
1325 return LowerFAULTING_OP(*MI);
1326
1327 case TargetOpcode::PATCHABLE_FUNCTION_ENTER:
1328 LowerPATCHABLE_FUNCTION_ENTER(*MI);
1329 return;
1330
1331 case TargetOpcode::PATCHABLE_FUNCTION_EXIT:
1332 LowerPATCHABLE_FUNCTION_EXIT(*MI);
1333 return;
1334
1335 case TargetOpcode::PATCHABLE_TAIL_CALL:
1336 LowerPATCHABLE_TAIL_CALL(*MI);
1337 return;
1338
1339 case AArch64::HWASAN_CHECK_MEMACCESS:
1340 case AArch64::HWASAN_CHECK_MEMACCESS_SHORTGRANULES:
1341 LowerHWASAN_CHECK_MEMACCESS(*MI);
1342 return;
1343
1344 case AArch64::SEH_StackAlloc:
1345 TS->EmitARM64WinCFIAllocStack(MI->getOperand(0).getImm());
1346 return;
1347
1348 case AArch64::SEH_SaveFPLR:
1349 TS->EmitARM64WinCFISaveFPLR(MI->getOperand(0).getImm());
1350 return;
1351
1352 case AArch64::SEH_SaveFPLR_X:
1353 assert(MI->getOperand(0).getImm() < 0 &&
1354 "Pre increment SEH opcode must have a negative offset");
1355 TS->EmitARM64WinCFISaveFPLRX(-MI->getOperand(0).getImm());
1356 return;
1357
1358 case AArch64::SEH_SaveReg:
1359 TS->EmitARM64WinCFISaveReg(MI->getOperand(0).getImm(),
1360 MI->getOperand(1).getImm());
1361 return;
1362
1363 case AArch64::SEH_SaveReg_X:
1364 assert(MI->getOperand(1).getImm() < 0 &&
1365 "Pre increment SEH opcode must have a negative offset");
1366 TS->EmitARM64WinCFISaveRegX(MI->getOperand(0).getImm(),
1367 -MI->getOperand(1).getImm());
1368 return;
1369
1370 case AArch64::SEH_SaveRegP:
1371 if (MI->getOperand(1).getImm() == 30 && MI->getOperand(0).getImm() >= 19 &&
1372 MI->getOperand(0).getImm() <= 28) {
1373 assert((MI->getOperand(0).getImm() - 19) % 2 == 0 &&
1374 "Register paired with LR must be odd");
1375 TS->EmitARM64WinCFISaveLRPair(MI->getOperand(0).getImm(),
1376 MI->getOperand(2).getImm());
1377 return;
1378 }
1379 assert((MI->getOperand(1).getImm() - MI->getOperand(0).getImm() == 1) &&
1380 "Non-consecutive registers not allowed for save_regp");
1381 TS->EmitARM64WinCFISaveRegP(MI->getOperand(0).getImm(),
1382 MI->getOperand(2).getImm());
1383 return;
1384
1385 case AArch64::SEH_SaveRegP_X:
1386 assert((MI->getOperand(1).getImm() - MI->getOperand(0).getImm() == 1) &&
1387 "Non-consecutive registers not allowed for save_regp_x");
1388 assert(MI->getOperand(2).getImm() < 0 &&
1389 "Pre increment SEH opcode must have a negative offset");
1390 TS->EmitARM64WinCFISaveRegPX(MI->getOperand(0).getImm(),
1391 -MI->getOperand(2).getImm());
1392 return;
1393
1394 case AArch64::SEH_SaveFReg:
1395 TS->EmitARM64WinCFISaveFReg(MI->getOperand(0).getImm(),
1396 MI->getOperand(1).getImm());
1397 return;
1398
1399 case AArch64::SEH_SaveFReg_X:
1400 assert(MI->getOperand(1).getImm() < 0 &&
1401 "Pre increment SEH opcode must have a negative offset");
1402 TS->EmitARM64WinCFISaveFRegX(MI->getOperand(0).getImm(),
1403 -MI->getOperand(1).getImm());
1404 return;
1405
1406 case AArch64::SEH_SaveFRegP:
1407 assert((MI->getOperand(1).getImm() - MI->getOperand(0).getImm() == 1) &&
1408 "Non-consecutive registers not allowed for save_regp");
1409 TS->EmitARM64WinCFISaveFRegP(MI->getOperand(0).getImm(),
1410 MI->getOperand(2).getImm());
1411 return;
1412
1413 case AArch64::SEH_SaveFRegP_X:
1414 assert((MI->getOperand(1).getImm() - MI->getOperand(0).getImm() == 1) &&
1415 "Non-consecutive registers not allowed for save_regp_x");
1416 assert(MI->getOperand(2).getImm() < 0 &&
1417 "Pre increment SEH opcode must have a negative offset");
1418 TS->EmitARM64WinCFISaveFRegPX(MI->getOperand(0).getImm(),
1419 -MI->getOperand(2).getImm());
1420 return;
1421
1422 case AArch64::SEH_SetFP:
1423 TS->EmitARM64WinCFISetFP();
1424 return;
1425
1426 case AArch64::SEH_AddFP:
1427 TS->EmitARM64WinCFIAddFP(MI->getOperand(0).getImm());
1428 return;
1429
1430 case AArch64::SEH_Nop:
1431 TS->EmitARM64WinCFINop();
1432 return;
1433
1434 case AArch64::SEH_PrologEnd:
1435 TS->EmitARM64WinCFIPrologEnd();
1436 return;
1437
1438 case AArch64::SEH_EpilogStart:
1439 TS->EmitARM64WinCFIEpilogStart();
1440 return;
1441
1442 case AArch64::SEH_EpilogEnd:
1443 TS->EmitARM64WinCFIEpilogEnd();
1444 return;
1445 }
1446
1447 // Finally, do the automated lowerings for everything else.
1448 MCInst TmpInst;
1449 MCInstLowering.Lower(MI, TmpInst);
1450 EmitToStreamer(*OutStreamer, TmpInst);
1451 }
1452
1453 // Force static initialization.
LLVMInitializeAArch64AsmPrinter()1454 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAArch64AsmPrinter() {
1455 RegisterAsmPrinter<AArch64AsmPrinter> X(getTheAArch64leTarget());
1456 RegisterAsmPrinter<AArch64AsmPrinter> Y(getTheAArch64beTarget());
1457 RegisterAsmPrinter<AArch64AsmPrinter> Z(getTheARM64Target());
1458 RegisterAsmPrinter<AArch64AsmPrinter> W(getTheARM64_32Target());
1459 RegisterAsmPrinter<AArch64AsmPrinter> V(getTheAArch64_32Target());
1460 }
1461