1 //===-- PPCInstrInfo.h - PowerPC Instruction Information --------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the PowerPC implementation of the TargetInstrInfo class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H 14 #define LLVM_LIB_TARGET_POWERPC_PPCINSTRINFO_H 15 16 #include "PPCRegisterInfo.h" 17 #include "llvm/CodeGen/TargetInstrInfo.h" 18 19 #define GET_INSTRINFO_HEADER 20 #include "PPCGenInstrInfo.inc" 21 22 namespace llvm { 23 24 /// PPCII - This namespace holds all of the PowerPC target-specific 25 /// per-instruction flags. These must match the corresponding definitions in 26 /// PPC.td and PPCInstrFormats.td. 27 namespace PPCII { 28 enum { 29 // PPC970 Instruction Flags. These flags describe the characteristics of the 30 // PowerPC 970 (aka G5) dispatch groups and how they are formed out of 31 // raw machine instructions. 32 33 /// PPC970_First - This instruction starts a new dispatch group, so it will 34 /// always be the first one in the group. 35 PPC970_First = 0x1, 36 37 /// PPC970_Single - This instruction starts a new dispatch group and 38 /// terminates it, so it will be the sole instruction in the group. 39 PPC970_Single = 0x2, 40 41 /// PPC970_Cracked - This instruction is cracked into two pieces, requiring 42 /// two dispatch pipes to be available to issue. 43 PPC970_Cracked = 0x4, 44 45 /// PPC970_Mask/Shift - This is a bitmask that selects the pipeline type that 46 /// an instruction is issued to. 47 PPC970_Shift = 3, 48 PPC970_Mask = 0x07 << PPC970_Shift 49 }; 50 enum PPC970_Unit { 51 /// These are the various PPC970 execution unit pipelines. Each instruction 52 /// is one of these. 53 PPC970_Pseudo = 0 << PPC970_Shift, // Pseudo instruction 54 PPC970_FXU = 1 << PPC970_Shift, // Fixed Point (aka Integer/ALU) Unit 55 PPC970_LSU = 2 << PPC970_Shift, // Load Store Unit 56 PPC970_FPU = 3 << PPC970_Shift, // Floating Point Unit 57 PPC970_CRU = 4 << PPC970_Shift, // Control Register Unit 58 PPC970_VALU = 5 << PPC970_Shift, // Vector ALU 59 PPC970_VPERM = 6 << PPC970_Shift, // Vector Permute Unit 60 PPC970_BRU = 7 << PPC970_Shift // Branch Unit 61 }; 62 63 enum { 64 /// Shift count to bypass PPC970 flags 65 NewDef_Shift = 6, 66 67 /// This instruction is an X-Form memory operation. 68 XFormMemOp = 0x1 << NewDef_Shift, 69 /// This instruction is prefixed. 70 Prefixed = 0x1 << (NewDef_Shift+1) 71 }; 72 } // end namespace PPCII 73 74 // Instructions that have an immediate form might be convertible to that 75 // form if the correct input is a result of a load immediate. In order to 76 // know whether the transformation is special, we might need to know some 77 // of the details of the two forms. 78 struct ImmInstrInfo { 79 // Is the immediate field in the immediate form signed or unsigned? 80 uint64_t SignedImm : 1; 81 // Does the immediate need to be a multiple of some value? 82 uint64_t ImmMustBeMultipleOf : 5; 83 // Is R0/X0 treated specially by the original r+r instruction? 84 // If so, in which operand? 85 uint64_t ZeroIsSpecialOrig : 3; 86 // Is R0/X0 treated specially by the new r+i instruction? 87 // If so, in which operand? 88 uint64_t ZeroIsSpecialNew : 3; 89 // Is the operation commutative? 90 uint64_t IsCommutative : 1; 91 // The operand number to check for add-immediate def. 92 uint64_t OpNoForForwarding : 3; 93 // The operand number for the immediate. 94 uint64_t ImmOpNo : 3; 95 // The opcode of the new instruction. 96 uint64_t ImmOpcode : 16; 97 // The size of the immediate. 98 uint64_t ImmWidth : 5; 99 // The immediate should be truncated to N bits. 100 uint64_t TruncateImmTo : 5; 101 // Is the instruction summing the operand 102 uint64_t IsSummingOperands : 1; 103 }; 104 105 // Information required to convert an instruction to just a materialized 106 // immediate. 107 struct LoadImmediateInfo { 108 unsigned Imm : 16; 109 unsigned Is64Bit : 1; 110 unsigned SetCR : 1; 111 }; 112 113 // Index into the OpcodesForSpill array. 114 enum SpillOpcodeKey { 115 SOK_Int4Spill, 116 SOK_Int8Spill, 117 SOK_Float8Spill, 118 SOK_Float4Spill, 119 SOK_CRSpill, 120 SOK_CRBitSpill, 121 SOK_VRVectorSpill, 122 SOK_VSXVectorSpill, 123 SOK_VectorFloat8Spill, 124 SOK_VectorFloat4Spill, 125 SOK_SpillToVSR, 126 SOK_SPESpill, 127 SOK_LastOpcodeSpill // This must be last on the enum. 128 }; 129 130 // Define list of load and store spill opcodes. 131 #define Pwr8LoadOpcodes \ 132 { \ 133 PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \ 134 PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXVD2X, PPC::LXSDX, PPC::LXSSPX, \ 135 PPC::SPILLTOVSR_LD, PPC::EVLDD \ 136 } 137 138 #define Pwr9LoadOpcodes \ 139 { \ 140 PPC::LWZ, PPC::LD, PPC::LFD, PPC::LFS, PPC::RESTORE_CR, \ 141 PPC::RESTORE_CRBIT, PPC::LVX, PPC::LXV, PPC::DFLOADf64, \ 142 PPC::DFLOADf32, PPC::SPILLTOVSR_LD \ 143 } 144 145 #define Pwr8StoreOpcodes \ 146 { \ 147 PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \ 148 PPC::STVX, PPC::STXVD2X, PPC::STXSDX, PPC::STXSSPX, \ 149 PPC::SPILLTOVSR_ST, PPC::EVSTDD \ 150 } 151 152 #define Pwr9StoreOpcodes \ 153 { \ 154 PPC::STW, PPC::STD, PPC::STFD, PPC::STFS, PPC::SPILL_CR, PPC::SPILL_CRBIT, \ 155 PPC::STVX, PPC::STXV, PPC::DFSTOREf64, PPC::DFSTOREf32, \ 156 PPC::SPILLTOVSR_ST \ 157 } 158 159 // Initialize arrays for load and store spill opcodes on supported subtargets. 160 #define StoreOpcodesForSpill \ 161 { Pwr8StoreOpcodes, Pwr9StoreOpcodes } 162 #define LoadOpcodesForSpill \ 163 { Pwr8LoadOpcodes, Pwr9LoadOpcodes } 164 165 class PPCSubtarget; 166 class PPCInstrInfo : public PPCGenInstrInfo { 167 PPCSubtarget &Subtarget; 168 const PPCRegisterInfo RI; 169 const unsigned StoreSpillOpcodesArray[2][SOK_LastOpcodeSpill] = 170 StoreOpcodesForSpill; 171 const unsigned LoadSpillOpcodesArray[2][SOK_LastOpcodeSpill] = 172 LoadOpcodesForSpill; 173 174 void StoreRegToStackSlot(MachineFunction &MF, unsigned SrcReg, bool isKill, 175 int FrameIdx, const TargetRegisterClass *RC, 176 SmallVectorImpl<MachineInstr *> &NewMIs) const; 177 void LoadRegFromStackSlot(MachineFunction &MF, const DebugLoc &DL, 178 unsigned DestReg, int FrameIdx, 179 const TargetRegisterClass *RC, 180 SmallVectorImpl<MachineInstr *> &NewMIs) const; 181 182 // Replace the instruction with single LI if possible. \p DefMI must be LI or 183 // LI8. 184 bool simplifyToLI(MachineInstr &MI, MachineInstr &DefMI, 185 unsigned OpNoForForwarding, MachineInstr **KilledDef) const; 186 // If the inst is imm-form and its register operand is produced by a ADDI, put 187 // the imm into the inst directly and remove the ADDI if possible. 188 bool transformToNewImmFormFedByAdd(MachineInstr &MI, MachineInstr &DefMI, 189 unsigned OpNoForForwarding) const; 190 // If the inst is x-form and has imm-form and one of its operand is produced 191 // by a LI, put the imm into the inst directly and remove the LI if possible. 192 bool transformToImmFormFedByLI(MachineInstr &MI, const ImmInstrInfo &III, 193 unsigned ConstantOpNo, 194 MachineInstr &DefMI) const; 195 // If the inst is x-form and has imm-form and one of its operand is produced 196 // by an add-immediate, try to transform it when possible. 197 bool transformToImmFormFedByAdd(MachineInstr &MI, const ImmInstrInfo &III, 198 unsigned ConstantOpNo, MachineInstr &DefMI, 199 bool KillDefMI) const; 200 // Try to find that, if the instruction 'MI' contains any operand that 201 // could be forwarded from some inst that feeds it. If yes, return the 202 // Def of that operand. And OpNoForForwarding is the operand index in 203 // the 'MI' for that 'Def'. If we see another use of this Def between 204 // the Def and the MI, SeenIntermediateUse becomes 'true'. 205 MachineInstr *getForwardingDefMI(MachineInstr &MI, 206 unsigned &OpNoForForwarding, 207 bool &SeenIntermediateUse) const; 208 209 // Can the user MI have it's source at index \p OpNoForForwarding 210 // forwarded from an add-immediate that feeds it? 211 bool isUseMIElgibleForForwarding(MachineInstr &MI, const ImmInstrInfo &III, 212 unsigned OpNoForForwarding) const; 213 bool isDefMIElgibleForForwarding(MachineInstr &DefMI, 214 const ImmInstrInfo &III, 215 MachineOperand *&ImmMO, 216 MachineOperand *&RegMO) const; 217 bool isImmElgibleForForwarding(const MachineOperand &ImmMO, 218 const MachineInstr &DefMI, 219 const ImmInstrInfo &III, 220 int64_t &Imm, 221 int64_t BaseImm = 0) const; 222 bool isRegElgibleForForwarding(const MachineOperand &RegMO, 223 const MachineInstr &DefMI, 224 const MachineInstr &MI, bool KillDefMI, 225 bool &IsFwdFeederRegKilled) const; 226 unsigned getSpillTarget() const; 227 const unsigned *getStoreOpcodesForSpillArray() const; 228 const unsigned *getLoadOpcodesForSpillArray() const; 229 int16_t getFMAOpIdxInfo(unsigned Opcode) const; 230 void reassociateFMA(MachineInstr &Root, MachineCombinerPattern Pattern, 231 SmallVectorImpl<MachineInstr *> &InsInstrs, 232 SmallVectorImpl<MachineInstr *> &DelInstrs, 233 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const; 234 virtual void anchor(); 235 236 protected: 237 /// Commutes the operands in the given instruction. 238 /// The commutable operands are specified by their indices OpIdx1 and OpIdx2. 239 /// 240 /// Do not call this method for a non-commutable instruction or for 241 /// non-commutable pair of operand indices OpIdx1 and OpIdx2. 242 /// Even though the instruction is commutable, the method may still 243 /// fail to commute the operands, null pointer is returned in such cases. 244 /// 245 /// For example, we can commute rlwimi instructions, but only if the 246 /// rotate amt is zero. We also have to munge the immediates a bit. 247 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI, 248 unsigned OpIdx1, 249 unsigned OpIdx2) const override; 250 251 public: 252 explicit PPCInstrInfo(PPCSubtarget &STI); 253 254 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 255 /// such, whenever a client has an instance of instruction info, it should 256 /// always be able to get register info as well (through this method). 257 /// getRegisterInfo()258 const PPCRegisterInfo &getRegisterInfo() const { return RI; } 259 isXFormMemOp(unsigned Opcode)260 bool isXFormMemOp(unsigned Opcode) const { 261 return get(Opcode).TSFlags & PPCII::XFormMemOp; 262 } isPrefixed(unsigned Opcode)263 bool isPrefixed(unsigned Opcode) const { 264 return get(Opcode).TSFlags & PPCII::Prefixed; 265 } 266 isSameClassPhysRegCopy(unsigned Opcode)267 static bool isSameClassPhysRegCopy(unsigned Opcode) { 268 unsigned CopyOpcodes[] = {PPC::OR, PPC::OR8, PPC::FMR, 269 PPC::VOR, PPC::XXLOR, PPC::XXLORf, 270 PPC::XSCPSGNDP, PPC::MCRF, PPC::CROR, 271 PPC::EVOR, -1U}; 272 for (int i = 0; CopyOpcodes[i] != -1U; i++) 273 if (Opcode == CopyOpcodes[i]) 274 return true; 275 return false; 276 } 277 278 ScheduleHazardRecognizer * 279 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, 280 const ScheduleDAG *DAG) const override; 281 ScheduleHazardRecognizer * 282 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II, 283 const ScheduleDAG *DAG) const override; 284 285 unsigned getInstrLatency(const InstrItineraryData *ItinData, 286 const MachineInstr &MI, 287 unsigned *PredCost = nullptr) const override; 288 289 int getOperandLatency(const InstrItineraryData *ItinData, 290 const MachineInstr &DefMI, unsigned DefIdx, 291 const MachineInstr &UseMI, 292 unsigned UseIdx) const override; getOperandLatency(const InstrItineraryData * ItinData,SDNode * DefNode,unsigned DefIdx,SDNode * UseNode,unsigned UseIdx)293 int getOperandLatency(const InstrItineraryData *ItinData, 294 SDNode *DefNode, unsigned DefIdx, 295 SDNode *UseNode, unsigned UseIdx) const override { 296 return PPCGenInstrInfo::getOperandLatency(ItinData, DefNode, DefIdx, 297 UseNode, UseIdx); 298 } 299 hasLowDefLatency(const TargetSchedModel & SchedModel,const MachineInstr & DefMI,unsigned DefIdx)300 bool hasLowDefLatency(const TargetSchedModel &SchedModel, 301 const MachineInstr &DefMI, 302 unsigned DefIdx) const override { 303 // Machine LICM should hoist all instructions in low-register-pressure 304 // situations; none are sufficiently free to justify leaving in a loop 305 // body. 306 return false; 307 } 308 useMachineCombiner()309 bool useMachineCombiner() const override { 310 return true; 311 } 312 313 /// When getMachineCombinerPatterns() finds patterns, this function generates 314 /// the instructions that could replace the original code sequence 315 void genAlternativeCodeSequence( 316 MachineInstr &Root, MachineCombinerPattern Pattern, 317 SmallVectorImpl<MachineInstr *> &InsInstrs, 318 SmallVectorImpl<MachineInstr *> &DelInstrs, 319 DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override; 320 321 /// Return true when there is potentially a faster code sequence for a fma 322 /// chain ending in \p Root. All potential patterns are output in the \p 323 /// P array. 324 bool getFMAPatterns(MachineInstr &Root, 325 SmallVectorImpl<MachineCombinerPattern> &P) const; 326 327 /// Return true when there is potentially a faster code sequence 328 /// for an instruction chain ending in <Root>. All potential patterns are 329 /// output in the <Pattern> array. 330 bool getMachineCombinerPatterns( 331 MachineInstr &Root, 332 SmallVectorImpl<MachineCombinerPattern> &P) const override; 333 334 bool isAssociativeAndCommutative(const MachineInstr &Inst) const override; 335 336 /// On PowerPC, we try to reassociate FMA chain which will increase 337 /// instruction size. Set extension resource length limit to 1 for edge case. 338 /// Resource Length is calculated by scaled resource usage in getCycles(). 339 /// Because of the division in getCycles(), it returns different cycles due to 340 /// legacy scaled resource usage. So new resource length may be same with 341 /// legacy or 1 bigger than legacy. 342 /// We need to execlude the 1 bigger case even the resource length is not 343 /// perserved for more FMA chain reassociations on PowerPC. getExtendResourceLenLimit()344 int getExtendResourceLenLimit() const override { return 1; } 345 346 void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, 347 MachineInstr &NewMI1, 348 MachineInstr &NewMI2) const override; 349 350 void setSpecialOperandAttr(MachineInstr &MI, uint16_t Flags) const override; 351 352 bool isCoalescableExtInstr(const MachineInstr &MI, 353 Register &SrcReg, Register &DstReg, 354 unsigned &SubIdx) const override; 355 unsigned isLoadFromStackSlot(const MachineInstr &MI, 356 int &FrameIndex) const override; 357 bool isReallyTriviallyReMaterializable(const MachineInstr &MI, 358 AAResults *AA) const override; 359 unsigned isStoreToStackSlot(const MachineInstr &MI, 360 int &FrameIndex) const override; 361 362 bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1, 363 unsigned &SrcOpIdx2) const override; 364 365 void insertNoop(MachineBasicBlock &MBB, 366 MachineBasicBlock::iterator MI) const override; 367 368 369 // Branch analysis. 370 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 371 MachineBasicBlock *&FBB, 372 SmallVectorImpl<MachineOperand> &Cond, 373 bool AllowModify) const override; 374 unsigned removeBranch(MachineBasicBlock &MBB, 375 int *BytesRemoved = nullptr) const override; 376 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 377 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 378 const DebugLoc &DL, 379 int *BytesAdded = nullptr) const override; 380 381 // Select analysis. 382 bool canInsertSelect(const MachineBasicBlock &, ArrayRef<MachineOperand> Cond, 383 Register, Register, Register, int &, int &, 384 int &) const override; 385 void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 386 const DebugLoc &DL, Register DstReg, 387 ArrayRef<MachineOperand> Cond, Register TrueReg, 388 Register FalseReg) const override; 389 390 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 391 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, 392 bool KillSrc) const override; 393 394 void storeRegToStackSlot(MachineBasicBlock &MBB, 395 MachineBasicBlock::iterator MBBI, 396 Register SrcReg, bool isKill, int FrameIndex, 397 const TargetRegisterClass *RC, 398 const TargetRegisterInfo *TRI) const override; 399 400 // Emits a register spill without updating the register class for vector 401 // registers. This ensures that when we spill a vector register the 402 // element order in the register is the same as it was in memory. 403 void storeRegToStackSlotNoUpd(MachineBasicBlock &MBB, 404 MachineBasicBlock::iterator MBBI, 405 unsigned SrcReg, bool isKill, int FrameIndex, 406 const TargetRegisterClass *RC, 407 const TargetRegisterInfo *TRI) const; 408 409 void loadRegFromStackSlot(MachineBasicBlock &MBB, 410 MachineBasicBlock::iterator MBBI, 411 Register DestReg, int FrameIndex, 412 const TargetRegisterClass *RC, 413 const TargetRegisterInfo *TRI) const override; 414 415 // Emits a register reload without updating the register class for vector 416 // registers. This ensures that when we reload a vector register the 417 // element order in the register is the same as it was in memory. 418 void loadRegFromStackSlotNoUpd(MachineBasicBlock &MBB, 419 MachineBasicBlock::iterator MBBI, 420 unsigned DestReg, int FrameIndex, 421 const TargetRegisterClass *RC, 422 const TargetRegisterInfo *TRI) const; 423 424 unsigned getStoreOpcodeForSpill(const TargetRegisterClass *RC) const; 425 426 unsigned getLoadOpcodeForSpill(const TargetRegisterClass *RC) const; 427 428 bool 429 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 430 431 bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg, 432 MachineRegisterInfo *MRI) const override; 433 434 bool onlyFoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, 435 Register Reg) const; 436 437 // If conversion by predication (only supported by some branch instructions). 438 // All of the profitability checks always return true; it is always 439 // profitable to use the predicated branches. isProfitableToIfCvt(MachineBasicBlock & MBB,unsigned NumCycles,unsigned ExtraPredCycles,BranchProbability Probability)440 bool isProfitableToIfCvt(MachineBasicBlock &MBB, 441 unsigned NumCycles, unsigned ExtraPredCycles, 442 BranchProbability Probability) const override { 443 return true; 444 } 445 446 bool isProfitableToIfCvt(MachineBasicBlock &TMBB, 447 unsigned NumT, unsigned ExtraT, 448 MachineBasicBlock &FMBB, 449 unsigned NumF, unsigned ExtraF, 450 BranchProbability Probability) const override; 451 isProfitableToDupForIfCvt(MachineBasicBlock & MBB,unsigned NumCycles,BranchProbability Probability)452 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, 453 BranchProbability Probability) const override { 454 return true; 455 } 456 isProfitableToUnpredicate(MachineBasicBlock & TMBB,MachineBasicBlock & FMBB)457 bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, 458 MachineBasicBlock &FMBB) const override { 459 return false; 460 } 461 462 // Predication support. 463 bool isPredicated(const MachineInstr &MI) const override; 464 465 bool isSchedulingBoundary(const MachineInstr &MI, 466 const MachineBasicBlock *MBB, 467 const MachineFunction &MF) const override; 468 469 bool PredicateInstruction(MachineInstr &MI, 470 ArrayRef<MachineOperand> Pred) const override; 471 472 bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1, 473 ArrayRef<MachineOperand> Pred2) const override; 474 475 bool ClobbersPredicate(MachineInstr &MI, std::vector<MachineOperand> &Pred, 476 bool SkipDead) const override; 477 478 // Comparison optimization. 479 480 bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, 481 Register &SrcReg2, int &Mask, int &Value) const override; 482 483 bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, 484 Register SrcReg2, int Mask, int Value, 485 const MachineRegisterInfo *MRI) const override; 486 487 488 /// Return true if get the base operand, byte offset of an instruction and 489 /// the memory width. Width is the size of memory that is being 490 /// loaded/stored (e.g. 1, 2, 4, 8). 491 bool getMemOperandWithOffsetWidth(const MachineInstr &LdSt, 492 const MachineOperand *&BaseOp, 493 int64_t &Offset, unsigned &Width, 494 const TargetRegisterInfo *TRI) const; 495 496 /// Get the base operand and byte offset of an instruction that reads/writes 497 /// memory. 498 bool getMemOperandsWithOffsetWidth( 499 const MachineInstr &LdSt, 500 SmallVectorImpl<const MachineOperand *> &BaseOps, int64_t &Offset, 501 bool &OffsetIsScalable, unsigned &Width, 502 const TargetRegisterInfo *TRI) const override; 503 504 /// Returns true if the two given memory operations should be scheduled 505 /// adjacent. 506 bool shouldClusterMemOps(ArrayRef<const MachineOperand *> BaseOps1, 507 ArrayRef<const MachineOperand *> BaseOps2, 508 unsigned NumLoads, unsigned NumBytes) const override; 509 510 /// Return true if two MIs access different memory addresses and false 511 /// otherwise 512 bool 513 areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, 514 const MachineInstr &MIb) const override; 515 516 /// GetInstSize - Return the number of bytes of code the specified 517 /// instruction may be. This returns the maximum number of bytes. 518 /// 519 unsigned getInstSizeInBytes(const MachineInstr &MI) const override; 520 521 void getNoop(MCInst &NopInst) const override; 522 523 std::pair<unsigned, unsigned> 524 decomposeMachineOperandsTargetFlags(unsigned TF) const override; 525 526 ArrayRef<std::pair<unsigned, const char *>> 527 getSerializableDirectMachineOperandTargetFlags() const override; 528 529 ArrayRef<std::pair<unsigned, const char *>> 530 getSerializableBitmaskMachineOperandTargetFlags() const override; 531 532 // Expand VSX Memory Pseudo instruction to either a VSX or a FP instruction. 533 bool expandVSXMemPseudo(MachineInstr &MI) const; 534 535 // Lower pseudo instructions after register allocation. 536 bool expandPostRAPseudo(MachineInstr &MI) const override; 537 isVFRegister(unsigned Reg)538 static bool isVFRegister(unsigned Reg) { 539 return Reg >= PPC::VF0 && Reg <= PPC::VF31; 540 } isVRRegister(unsigned Reg)541 static bool isVRRegister(unsigned Reg) { 542 return Reg >= PPC::V0 && Reg <= PPC::V31; 543 } 544 const TargetRegisterClass *updatedRC(const TargetRegisterClass *RC) const; 545 static int getRecordFormOpcode(unsigned Opcode); 546 547 bool isTOCSaveMI(const MachineInstr &MI) const; 548 549 bool isSignOrZeroExtended(const MachineInstr &MI, bool SignExt, 550 const unsigned PhiDepth) const; 551 552 /// Return true if the output of the instruction is always a sign-extended, 553 /// i.e. 0 to 31-th bits are same as 32-th bit. 554 bool isSignExtended(const MachineInstr &MI, const unsigned depth = 0) const { 555 return isSignOrZeroExtended(MI, true, depth); 556 } 557 558 /// Return true if the output of the instruction is always zero-extended, 559 /// i.e. 0 to 31-th bits are all zeros 560 bool isZeroExtended(const MachineInstr &MI, const unsigned depth = 0) const { 561 return isSignOrZeroExtended(MI, false, depth); 562 } 563 564 bool convertToImmediateForm(MachineInstr &MI, 565 MachineInstr **KilledDef = nullptr) const; 566 bool foldFrameOffset(MachineInstr &MI) const; 567 bool combineRLWINM(MachineInstr &MI, MachineInstr **ToErase = nullptr) const; 568 bool isADDIInstrEligibleForFolding(MachineInstr &ADDIMI, int64_t &Imm) const; 569 bool isADDInstrEligibleForFolding(MachineInstr &ADDMI) const; 570 bool isImmInstrEligibleForFolding(MachineInstr &MI, unsigned &BaseReg, 571 unsigned &XFormOpcode, 572 int64_t &OffsetOfImmInstr, 573 ImmInstrInfo &III) const; 574 bool isValidToBeChangedReg(MachineInstr *ADDMI, unsigned Index, 575 MachineInstr *&ADDIMI, int64_t &OffsetAddi, 576 int64_t OffsetImm) const; 577 578 /// Fixup killed/dead flag for register \p RegNo between instructions [\p 579 /// StartMI, \p EndMI]. Some pre-RA or post-RA transformations may violate 580 /// register killed/dead flags semantics, this function can be called to fix 581 /// up. Before calling this function, 582 /// 1. Ensure that \p RegNo liveness is killed after instruction \p EndMI. 583 /// 2. Ensure that there is no new definition between (\p StartMI, \p EndMI) 584 /// and possible definition for \p RegNo is \p StartMI or \p EndMI. For 585 /// pre-RA cases, definition may be \p StartMI through COPY, \p StartMI 586 /// will be adjust to true definition. 587 /// 3. We can do accurate fixup for the case when all instructions between 588 /// [\p StartMI, \p EndMI] are in same basic block. 589 /// 4. For the case when \p StartMI and \p EndMI are not in same basic block, 590 /// we conservatively clear kill flag for all uses of \p RegNo for pre-RA 591 /// and for post-RA, we give an assertion as without reaching definition 592 /// analysis post-RA, \p StartMI and \p EndMI are hard to keep right. 593 void fixupIsDeadOrKill(MachineInstr *StartMI, MachineInstr *EndMI, 594 unsigned RegNo) const; 595 void replaceInstrWithLI(MachineInstr &MI, const LoadImmediateInfo &LII) const; 596 void replaceInstrOperandWithImm(MachineInstr &MI, unsigned OpNo, 597 int64_t Imm) const; 598 599 bool instrHasImmForm(unsigned Opc, bool IsVFReg, ImmInstrInfo &III, 600 bool PostRA) const; 601 602 // In PostRA phase, try to find instruction defines \p Reg before \p MI. 603 // \p SeenIntermediate is set to true if uses between DefMI and \p MI exist. 604 MachineInstr *getDefMIPostRA(unsigned Reg, MachineInstr &MI, 605 bool &SeenIntermediateUse) const; 606 607 /// getRegNumForOperand - some operands use different numbering schemes 608 /// for the same registers. For example, a VSX instruction may have any of 609 /// vs0-vs63 allocated whereas an Altivec instruction could only have 610 /// vs32-vs63 allocated (numbered as v0-v31). This function returns the actual 611 /// register number needed for the opcode/operand number combination. 612 /// The operand number argument will be useful when we need to extend this 613 /// to instructions that use both Altivec and VSX numbering (for different 614 /// operands). getRegNumForOperand(const MCInstrDesc & Desc,unsigned Reg,unsigned OpNo)615 static unsigned getRegNumForOperand(const MCInstrDesc &Desc, unsigned Reg, 616 unsigned OpNo) { 617 int16_t regClass = Desc.OpInfo[OpNo].RegClass; 618 switch (regClass) { 619 // We store F0-F31, VF0-VF31 in MCOperand and it should be F0-F31, 620 // VSX32-VSX63 during encoding/disassembling 621 case PPC::VSSRCRegClassID: 622 case PPC::VSFRCRegClassID: 623 if (isVFRegister(Reg)) 624 return PPC::VSX32 + (Reg - PPC::VF0); 625 break; 626 // We store VSL0-VSL31, V0-V31 in MCOperand and it should be VSL0-VSL31, 627 // VSX32-VSX63 during encoding/disassembling 628 case PPC::VSRCRegClassID: 629 if (isVRRegister(Reg)) 630 return PPC::VSX32 + (Reg - PPC::V0); 631 break; 632 // Other RegClass doesn't need mapping 633 default: 634 break; 635 } 636 return Reg; 637 } 638 639 /// Check \p Opcode is BDNZ (Decrement CTR and branch if it is still nonzero). 640 bool isBDNZ(unsigned Opcode) const; 641 642 /// Find the hardware loop instruction used to set-up the specified loop. 643 /// On PPC, we have two instructions used to set-up the hardware loop 644 /// (MTCTRloop, MTCTR8loop) with corresponding endloop (BDNZ, BDNZ8) 645 /// instructions to indicate the end of a loop. 646 MachineInstr * 647 findLoopInstr(MachineBasicBlock &PreHeader, 648 SmallPtrSet<MachineBasicBlock *, 8> &Visited) const; 649 650 /// Analyze loop L, which must be a single-basic-block loop, and if the 651 /// conditions can be understood enough produce a PipelinerLoopInfo object. 652 std::unique_ptr<TargetInstrInfo::PipelinerLoopInfo> 653 analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const override; 654 }; 655 656 } 657 658 #endif 659